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Advanced high-j dielectric stacks with polySi and metal gates: Recent progress and current challenges
The paper reviews our recent progress and current challenges in implementing advanced gate stacks composed of high-j dielectric materials and metal gates in mainstream Si CMOS technology. In particular, we address stacks of doped polySi gate electrodes on ultrathin layers of high-j dielectrics, dual-workfunction metal-gate technology, and fully silicided gates. Materials and device characterization, processing, and integration issues are discussed.

E. P. Gusev V. Narayanan M. M. Frank

1. Introduction
The enormous growth of microelectronics over the past four decades and, as a result, the signi?cant progress of information technology in general are based, to a large extent, on a simple gift of nature, the SiO2/Si system. This is especially true because ultrathin gate dielectrics in MOSFETs remain the key element in conventional silicon-based microelectronic devices. Since the very beginning of the microelectronics era, the SiO2 gate oxide has played a critical role in device performance and scaling [1–6]. Whereas the thickness of the SiO2 gate oxide in the ?rst transistors was a few hundred nanometers, the functionality and performance of stateof-the-art devices currently rely on gate oxides that are just a few atomic layers (;1–2 nm) thick. Until very recently, the (evolutionary) scaling of the gate dielectric (and ULSI devices in general) has been accomplished by shrinking physical dimensions. As the physical thickness of SiO2-based gate oxides approaches ;2 nm, a number of fundamental problems arise. In this ultrathin regime, some key dielectric parameters degrade: gate leakage current, oxide breakdown, boron penetration from the polysilicon gate electrode, and channel mobility [1, 3]. Each of the parameters is vital for device operation. In other words, the conventional device-scaling scenario involving scaling down SiO2-based dielectrics below 1 nm becomes impractical. The solution is to replace conventional SiO2 gate oxides with a material having higher permittivity. High-j insulators can be grown physically thicker for the same

(or thinner) equivalent electrical oxide thickness (EOT), thus o?ering signi?cant gate leakage reduction, as demonstrated by several research groups [7–10]. Signi?cant progress has been achieved in terms of the screening and selection of high-j insulators, understanding their material and electrical properties, and their integration into CMOS technology [7–10]. After almost a decade of intense research, the family of hafnium-oxide-based materials, such as HfO2, HfSixOy, HfOxNy, and HfSixOyNz, emerges as a leading candidate to replace SiO2 gate dielectrics in advanced CMOS applications [11–23]. It has also become evident in the last few years that only replacing the gate insulator, with no concurrent change of electrode material (currently heavily doped polySi), may not be su?cient for device scaling. Polysilicon gate electrodes are known to su?er from a polySi depletion e?ect (equivalent to a ;0.3– 0.4-nmthick parasitic capacitor), which cannot be ignored for sub-2-nm gate stacks. Therefore, research on dualworkfunction metal-gate electrodes is gaining momentum, since conventional gate stacks are approaching a limit to scaling as a means of improving performance for nano-CMOS (i.e., sub-65-nm) technologies. It is the purpose of this paper to review our current understanding of advanced metal-gate/high-j stacks from the perspective of integrating both basic materials and devices. Reliability is also an important factor, especially for long-term device operation. Some reliability aspects of advanced gate stacks are covered in the paper. More

?Copyright 2006 by International Business Machines Corporation. Copying in printed form for private use is permitted without payment of royalty provided that (1) each reproduction is done without alteration and (2) the Journal reference and IBM copyright notice are included on the ?rst page. The title and abstract, but no other portions, of this paper may be copied or distributed royalty free without further permission by computer-based and other information-service systems. Permission to republish any other portion of this paper must be obtained from the Editor. 0018-8646/06/$5.00 ? 2006 IBM

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detailed results and focused discussion on this important topic can be found in a recent dedicated review by IBM researchers in [24]. The use of high-j dielectrics is one of the most critical challenges in CMOS device scaling, and, as such, it is being aggressively tackled worldwide by many researchers and engineers in academic, industrial, and government laboratories. In this review, we focus speci?cally on the work and progress achieved in the IBM laboratories over the past ?ve years. The paper is organized as follows. In Section 2, we discuss progress and challenges in the integration of high-j materials with polySi gates. Historically, using polySi gates with high-j dielectrics was believed to be a ‘‘simple’’ solution to overcome limits to SiO2 scaling in the tunneling regime when gate leakage became too severe. It was the reason why early work in the high-j area was dominated by devices with polySi electrodes. It was later realized that the polysilicon electrode was not an ideal solution, for reasons of thickness scaling and threshold voltage control; as a result, the focus shifted to metal gates, an even more challenging area. The current status of research and development in this area is reviewed in Section 3. It is demonstrated that metal gates do o?er extraordinary scaling potential to an electrical inversion thickness of almost 1 nm. At the same time, dualworkfunction control of n? and p? Si band edges remains a challenge. As discussed in Section 4, fully silicided (FUSI) gates combine the integration bene?ts of polySi devices and metal-like behavior without polySi depletion e?ects.

2. PolySi/high-j gate stacks and Hf-based gate dielectrics
PolySi-based devices are usually annealed at high temperatures (.1,0008C) in order to activate dopants in the gate and source/drain regions. The requirements of thermal stability in contact with the polySi gate electrode and negligible metal di?usion into the Si channel have virtually ruled out successful integration of high-j materials such as ZrO2 [25, 26] and Al2O3 [27] that once were under intense investigation. Even with Hf-based materials, a number of challenges remain, perhaps most signi?cantly regarding the thermal stability of the dielectric, electrical thickness scaling, carrier mobility, p-FET threshold voltage, and long-term stability/ reliability under device operation conditions. In the following sections we review how such considerations have recently guided the development of Hf-based gate stack materials for polySi-gated devices. Thermal stability In contrast to ZrO2 [25, 26], no detrimental silicide formation occurs with HfO2 in contact with polySi gates. However, polySi/HfO2 gate stacks do undergo substantial

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changes during thermal processing. Dopant activation requires annealing to temperatures of ;1,0008C or more, much higher than crystallization temperatures of amorphous HfO2. Depending on HfO2 thickness, crystallization into predominantly monoclinic polycrystalline ?lms occurs at 300–5008C [28–31]. Also, the formation of additional interfacial SiO2 is often observed [32], degrading gate stack capacitance. This is discussed in more detail in the next subsection. In the early stages of work on HfO2, it was believed that grain boundaries in polycrystalline ?lms might constitute electrical leakage paths, giving rise to dramatically increased gate leakage currents. Experimentally, only minor, if any, increase in leakage with polycrystalline HfO2 has been observed [29]. However, amorphous high-j layers may be preferred for other reasons. For example, it has been suggested that heterogeneous grain orientations in the dielectric layer may give rise to spatially varying electric ?elds and thus cause carrier scattering, thereby degrading mobility. Also, with continuing scaling, the gate length will become comparable to the HfO2 grain diameter. According to the International Technology Roadmap for Semiconductors [33], the physical gate length of high-performance devices is projected to reach 18 nm by 2010. This may cause detrimental device-to-device variations in leakage, threshold voltage, etc. Also, integration issues such as line-edge roughness at the bottom of the gate stack during gate stack etch may then arise. We note, however, that so far there is little experimental evidence to support the above concerns. Finally, grain boundaries in poly- or nano-crystalline material were recently claimed to be responsible for localized unoccupied states below the metal d-statederived conduction band edge in ZrO2 and other transition-metal (and rare-earth) oxide ?lms [34]. Such defect states have been observed by optical and X-ray absorption spectroscopy as well as by photoconductivity measurements [34]. Indeed, band-edge defect states have recently been shown to occur in HfO2 if and only if the dielectrics exhibit crystallinity as detected by infrared spectroscopy, X-ray di?raction (XRD), and vacuum ultraviolet spectroscopic ellipsometry (VUV–SE) [35]. This is exempli?ed by the imaginary part e2 of the dielectric function for HfO2 ?lms grown by atomic layer deposition (ALD), as displayed in Figure 1. When HfO2 thickness (and concomitantly crystallinity) is increased, an absorption feature emerges at ;5.8 eV, i.e., ;0.2– 0.3 eV below the bandgap. The same correlation between crystallinity and electronic defects holds also for other HfO2 growth chemistries [35]. These observations are signi?cant from a device perspective, since they may be related to the ?nding that Frenkel–Poole hopping

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through HfO2 gate dielectrics occurs via trapping sites located a few tenths of an eV below the HfO2 conduction band edge [36]. Ultimately, it is unlikely that such states will be a limiting factor in high-j-based CMOS technologies, since they line up close to the insulator band edge and are therefore not accessible at the low gate voltages employed in high-performance and low-power technologies. However, at present it is not clear whether additional grain-boundary-induced defect states exist deeper in the bandgap. It therefore appears preferable to employ amorphous high-j materials. In order to prevent gate dielectric crystallization and to minimize interfacial SiO2 formation, the thermal stability of the HfO2 dielectric must be increased. This can be achieved by addition of Al [29, 37, 38], Si [31, 35], and/or N [39]. HfA1O gate dielectrics have often been found to reduce carrier mobility, possibly due to ?xed charge near the high-j/channel interface [38]. Therefore, most researchers have recently concentrated on HfSiO and HfSiON. Substantially increased thermal stability is achieved for example at a comparatively low Si content of Si/(Hf ? Si) ? 20%.1 Even after rapid thermal anneals to 1,0008C for 5 s, such ?lms do not exhibit any infrared phonon modes characteristic of monoclinic HfO2, in contrast to what is observed from as-deposited HfO2 ?lms formed under the same conditions. It is likely that the HfSiO remains mostly amorphous, although partial crystallization into the tetragonal or orthorhombic phase cannot be excluded [31]. However, after longer 900– 1,0008C anneals, HfSiO may still crystallize and decompose into HfO2 and SiO2 [28, 31, 39, 40, 41]. Further increased thermal stability can be achieved by additionally introducing N. The tendency to crystallize under extended 1,0008C dopant activation anneals is completely suppressed in HfSiON with a N content of N/(O ? N) . 10% [39]. In addition, boron penetration is more e?ectively prevented by HfSiON than by HfSiO [39, 41]. Electrical thickness scaling In broad terms, the electrical thickness of Hf(Si)O(N)/ SiO(N) gate dielectrics is determined by the sum of the electrical thickness of the high-j layer and the interfacial SiO(N) layer (if present). Therefore, a combination of strategies may be pursued in order to minimize total electrical thickness, each posing its own challenges:
 Minimize high-j thickness, while maintaining a)

3

Optical absorption

2
2

40 nm HfO2 Mostly polycrystalline

1 5 nm HfO2 Low crystallinity 5.5 6.0 Photon energy (eV) 6.5

0

Figure 1
Imaginary part 2 of the dielectric function, determined from VUV–SE data, for 5- and 40-nm-thick ALD-grown HfO2 films. The 40-nm data has been offset vertically for clarity.

 Minimize the interfacial SiO(N) thickness, while

maintaining a) su?cient/appropriate Si surface functionalization to ensure good (near-homogeneous) high-j nucleation and hence a closed layer, and b) high carrier mobility.  Increase N concentration in the interfacial SiO(N) and high-j layers in order to increase the dielectric constant and reduce interfacial layer growth during thermal processing, while maintaining a) low charge trapping and b) high carrier mobility.
In this subsection, we review various surface preparation and process approaches to optimize interfacial layer thickness and high-j nucleation, and in particular to address the scaling bene?t of interfacial nitrogen. The scaling bene?t of HfSiO nitridation is discussed below in conjunction with the impact of N on charge trapping and carrier mobility. Chemically or thermally grown silicon oxide ?lms, preferably with a high density of terminal hydroxyl groups, represent excellent nucleation layers for many ALD- and CVD-based high-j growth processes [42]. However, their thickness typically ranges from 0.5 to more than 1 nm, contributing signi?cantly to the total electrical thickness. This has motivated the development of alternative surface preparation schemes. In an attempt to fabricate atomically sharp Si/high-j interfaces, oxide-free H-terminated Si(H/Si) substrates have been utilized. Such H/Si(100) can be prepared quickly and reproducibly by a hydro?uoric acid (HF) wet etch of SiO2/Si, with subseqent water rinse [43]. Such substrates are remarkably resistant to oxidation in laboratory air, and even in O2- or H2O-containing environments at temperatures as high as 3008C. (For a

a closed high-j layer and b) su?cient Hf content of the gate stack as a whole, ensuring a gate leakage advantage over pure SiON gate dielectrics.
1

M. M. Frank and L. F. Edge, unpublished work.

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comprehensive review of H/Si reactivity with respect to O2, H2O, NH3, and high-j precursors, see [44].) While this low surface reactivity may be advantageous in terms of oxidation resistance, it also causes the poor nucleation characteristics of many ALD-grown high-j ?lms, resulting in nonlinear growth kinetics and the formation of discontinuous and electrically leaky gate stacks. Prominent examples are the popular HfCl4/H2O process for HfO2 growth [30, 42, 45], as well as other water-based ALD processes employing metal precursors that are designed to react with surface ?OH groups, such as ZrCl4 for ZrO2 growth [26, 46] and Al(CH3)3 for Al2O3 growth [44 – 46]. Nucleation can be enhanced, and more linear growth achieved, if in situ activation of the H/Si surface by a more reactive oxygen precursor such as O3 is performed. However, this comes at the expense of substantial interfacial SiO2 formation during growth [47, 48]. A simple way to overcome poor ALD nucleation on H/Si without employing a more reactive O precursor is via initial extended H/Si exposure to Al(CH3)3. During exposures ;1,000 times larger than what is commonly employed in ALD, metal–organic functional groups are introduced onto the Si surface [44, 45, 49]. Such groups are reactive toward the water precursor. On Al–organic functionalized Si, improved HfO2 and Al2O3 nucleation is achieved [44, 45, 49]. (Note that, by contrast, large initial H2O exposures of H/Si leave the H termination nearly una?ected and therefore do not lead to enhanced highj growth [44, 45, 49].) A possible shortcoming of Alorganic functionalization is the excessive Al(CH3)3 exposure times required with currently available ALD equipment. Also, in view of HfAlO-induced mobility degradation [38], tests must be made to determine whether Al located near a HfO2/channel interface is acceptable. Another approach to optimize nucleation and minimize interfacial SiO2 formation on H/Si is based on ALD growth at reduced temperatures (e.g., 50 –1008C). Interfacial SiO2 formation thus is prevented using both the Al(CH3)3/H2O process for Al2O3 growth2 and the tetrakis(ethylmethylamino)hafnium/water process for HfO2 growth2 [50]. To passivate the surface and prevent oxidation, hydrogen may be replaced with other atomic species as surface passivant. For example, monolayer chlorine passivation is achieved by a simple Cl2 gas treatment of H/Si [51], where reaction rates may be enhanced by ultraviolet (UV) light [52]. Preliminary evaluation indicates a minor thickness advantage over SiON interfaces, but nucleation is poor [53].
2

Like oxide-based subtrates, nitride-based interfaces such as high-nitrogen-concentration SiON or pure silicon nitride often are good nucleation layers [30, 54, 55]. In addition, nitridation increases interface permittivity (e.g., kSiO2 ? 3.9; kSi3N4 ? 7–8) and thermal stability. This scaling bene?t can be realized, for example, with interfacial Si(O)N layers fabricated by H/Si anneal in NH3 at 6508C to form thin Si3N4 [55, 56], optionally followed by an oxidizing anneal in NO [57]. PolySi/ HfSiO stacks on such high-nitrogen-content ?lms exhibit lower electrical thickness (EOT) than on 1.1-nm low-Ncontent SiON control substrates, even in cases in which physical thickness is greater [57]. The main concern with high-nitrogen-content interfaces is carrier mobility loss, as discussed below. To conclude, we note that despite promising results with unconventional Si surface treatments (such as chlorination or metal–organic functionalization), most work in the high-j ?eld still relies on hydrogen termination and on SiO2 or low-nitrogen SiON ?lms. Such substrates can be prepared quickly and coste?ectively with conventional manufacturing equipment. Carrier mobility High-j materials have often been observed to degrade carrier mobility in the transistor channel. A number of mechanisms have been held responsible, most signi?cantly remote phonon scattering through emission or absorption of low-energy phonons in the high-j material [58] and remote Coulomb scattering o? ?xed or trapped charges in the gate dielectric. Over time, reported mobilities with nominally similar gate stacks generally have improved. This suggests that certain defects in the high-j materials such as electrical trap sites and impurities giving rise to ?xed charges can be minimized by process engineering. However, remote phonon scattering has been central in the debate regarding mobility degradation since, if signi?cant, it could fundamentally limit the performance of HfO2-based devices. A possible solution is based on the incorporation of Si into the HfO2, modifying the vibrational properties. Since Si– O bonds are sti?er than Hf– O bonds, soft phonon modes are reduced in intensity. The consequent drop in the remote phonon scattering cross section has been predicted to result in near-complete carrier mobility recovery when ZrO2 is replaced by ZrSiO4 [58]. The same physics holds for hafnium silicates, as experimentally proven by Ren and colleagues [59]. The mobility advantage comes at the expense of a reduced dielectric constant (20 – 25 for HfO2 compared to 10–15 for HfSiO), a tradeo? that must be taken into account when optimizing overall device performance by tuning the composition of Hf-based dielectrics.

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M. M. Frank, Y. Wang, M.-T. Ho, R. T. Brewer, and Y. J. Chabal, ‘‘Hydrogen Barrier Layer Preventing Silicon Oxidation During Atomic Layer Deposition of Al2O3 and HfO2,’’ in preparation.

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Carrier mobility and thermal stability have likely been the main characteristics driving the shift in industry focus from polySi/HfO2 to polySi/HfSiO(N) gate stacks. Indeed, even Si concentrations in HfSiO as low as Si/(Hf ? Si) ? 20% have been shown to enable excellent mobilities. For example, we have fabricated polySi/ HfSiO/SiON n-FETs with EOT ? 1.6 nm that exhibit electron peak mobility identical to that of low-N-content SiON control devices [60]. High-?eld electron mobility was degraded by only ;10%. Given a leakage reduction factor of .1,000 compared with SiON control devices with the same EOT, such gate stacks are serious contenders for low-power applications. Whether the observed mobility improvements achieved by the introduction of Si into the HfO2 are due mainly to the drop in remote phonon scattering is still under debate. Reduced charge trapping is another possible cause, since this would reduce the Coulomb scattering rate. The charge-trapping behavior of HfSiO is indeed better than that of HfO2 [59]. Nitrogen is often introduced into high-j gate stacks to enhance thermal stability and reduce electrical thickness, as discussed brie?y above. However, carrier mobility is usually reduced, e.g., for HfSiO on Si3N4 interface layers [56]. This is illustrated in Figure 2, which shows n-FET electron mobility for various HfSiO/Si(O)N gate stacks. Mobility at high ?eld (black symbols) was extracted from full mobility curves (inset) measured using the split C–V technique [61, 62]. With interfacial Si3N4 formed by an NH3 anneal of H/Si at 6508C (N areal density ;2 3 1015 N/cm2), high-?eld mobility is degraded by 20 – 25% compared with low-N-content interfacial SiON layers (;7 3 1014 N/cm2). Even upon introduction of O into the nitride using NO gas anneals at 700 – 8008C, mobility recovers only marginally. When interpreting such data, it is noteworthy that high nitrogen concentrations usually reduce mobility even with conventional SiON gate dielectrics [63]. Since nitrogen is known to create ?xed charge in SiON [64, 65], it seems natural to hold Coulomb scattering by ?xed charges responsible for the mobility loss both in SiON and high-j stacks. However, other physical causes also may underlie the observed Ninduced mobility degradation in high-j gate stacks. Three scenarios may explain an observed mobility reduction: a) Slow interface states (areal density Nit) or b) ?xed charges (areal density Nox) cause Coulomb scattering of channel electrons; or c) charge trapping causes Coulomb scattering or induces hysteresis which distorts the inversion charge and mobility measurement. A combination of electrical measurement techniques aids in assessing which of these mechanisms is dominant in mobility degradation [57]. To address scenario a), Nit was measured by amplitude-sweep charge pumping. Independently of O content, all nitride-based interfaces

Electron mobility (cm 2 /V-s)

NO(800°C) 400 300

30 ? HfSiO on SiON 2 nm HfSiO 3 nm HfSiO (7 2.5 nm HfSiO NH3 –NO(800°C) NH3 –NO(700°C) NH3 SiON 1014 N/cm 2)

Electron mobility (cm 2 /V-s)

240

220

200

200 30 ? HfSiO 100 on NH 3 0 0 2 4 6 8 10 12 Inversion layer charge (1012 cm 2)

180

160

1.8

2.0

2.2

2.4 2.6 Ti nv (nm)

2.8

3.0

3.2

Figure 2
High-field electron mobility (at inversion charge density Ninv 1013 cm 2) as a function of inversion thickness (Tinv) values for various Si(O)N processes (see text) and HfSiO thicknesses. Black: as-measured. White: after Nit correction. Inset: Electron mobility as a function of Ninv for various Si(O)N processes at a HfSiO thickness of 3 nm.

exhibited 3–5 times higher Nit (1.3–1.9 3 1011 cm?2) than low-nitrogen-content control SiON interfaces. In order to establish whether this Nit di?erence is su?cient to explain the mobility loss, a corrected mobility was calculated that would be measured if Nit could be reduced to zero without otherwise modifying the gate stacks.3 After this correction, the mobility trend with N and O content remained virtually unchanged (Figure 2, white symbols), demonstrating that mechanisms other than slow interface states are predominantly responsible for N-induced mobility loss. Scenario b), by contrast, was supported by C–V measurements: threshold voltage Vt is ;0.1 V lower with all Si3N4-based interfaces than with the control SiON interface. This shift corresponds to an areal density of positive ?xed charge of Nox ;8 3 1011 cm?2 (broadly consistent with [56]), independent of O content. Nox thus is signi?cantly higher than Nit and can quantitatively explain the observed mobility loss with reoxidized nitride interfaces [57]. With pure nitride interfaces, distortion of the inversion charge measurement due to transient charging c) occurs in addition [57]. However, ?xed charge likely is the main case of carrier mobility loss with interfacial N [57]. Nitridation of HfSiO layers similarly has often been reported to degrade mobility. However, this is not a universal result. Recent experimental studies indicate that
3

K. Maitra, V. Misra, B. P. Linder, V. Narayanan, E. P. Gusev, M. M. Frank, and E. Cartier, Appl. Phys. Lett. (submitted).

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400

300

2.5 nm SiON (7
200

1014 N/cm 2) 3 nm HfSiON (21% N) on chemical oxide

100

0

0

2

4

6 Ninv (1012 cm

8
2)

10

12

Figure 3
Electron mobility with 3 nm top-nitrided HfSiON with [N/(N ~ 21%, compared with low-N-content SiON. O)]

mobility impact is greatest if nitridation conditions allow N to permeate the entire HfSiO ?lm, while near-surface nitridation preserves mobility [39]. This indicates that N in or close to the interfacial layer has by far the greatest impact on mobility. Possible reasons for this are a) the rapidly decaying electrical ?eld strength around a ?xed charge, giving rise to simultaneously dropping Coulomb scattering cross sections; and b) a lower ?xed charge per N atom in HfSiON than in SiON. Good electron mobility with HfSiON/SiO2 is demonstrated in Figure 3. Appropriate low-temperature plasma nitridation conditions ensured a high proportion of near-surface N [57]. Under such conditions, gate stacks incorporating such HfSiON showed N-induced Tinv reduction by up to 0.1 nm, con?rming the scaling bene?t of N. At N concentrations as high as [N/(N ? O)] ; 21%, the N-induced Vfb/Vt shift to more negative values is smaller than 0.02 V, showing that little positive ?xed charge is created far from the gate electrode. Trap density remains low as well. As expected on the basis of our discussion of the mobility degradation mechanisms with interfacial N, mobility is nearly identical to that of a lowN-content SiON control (Figure 3). Summarizing this section, the replacement of HfO2 by HfSiO has led to mobility improvements, through reduced remote phonon and/or Coulomb scattering. Additional N incorporation helps optimize thermal stability and electrical thickness. However, N near the channel reduces carrier mobility through Coulomb scattering by ?xed charges. N incorporation near the top of the HfSiO is therefore the method of choice. Threshold voltage The threshold voltages of polySi-gated high-j n-FETs and p-FETs usually deviate from the ideal values

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achieved with corresponding SiO(N) devices. Using Hfbased high-j materials, in particular, n-FET Vt is usually found to be more positive by ;0.2 V, while p-FET Vt is more negative by ;0.6 V [66 – 69]. While threshold voltages can be tuned to their optimum values through device engineering, for example by an appropriate choice of halo implant design or by counterdoping, device performance degrades with excessive tuning. It is likely that n-FET devices can be designed in such a way as to o?set the materials-induced shift of ;0.2 V. By contrast, given the ;0.6-V shift for p-FET devices, one cannot rely on implant engineering alone in order to fabricate goodperformance Hf-based polySi/high-j devices. The gate stack itself must be understood and modi?ed. In the following, we ?rst summarize some observations regarding the impact on Vt of processing conditions and materials composition. We then review the current understanding of the underlying physical mechanisms causing the increased p-FET threshold voltage. Finally, we discuss recent attempts to control p-FET Vt and demonstrate that improvement by ;0.3 V can be achieved by appropriate design of the gate stack alone [60], rendering p-FETs with good performance possible. The fact that laboratories worldwide—using a wide variety of process equipment and chemicals to fabricate gate stacks—report nearly identical p-FET Vt shifts of ;0.6 V from the target value suggests that a fundamental physical or chemical phenomenon is responsible. We have tested whether tuning of processing details, in particular choice of dopant, method of doping (implant vs. in situ doping with CVD precursors), and thermal processing, can help control Vt. To this end, the Vfb/Vt shifts were measured after such critical gate-stack fabrication steps [70]. Measurements even with undoped and unactivated polySi gates were made possible by recording electrical data at elevated device temperatures (up to 2008C) in order to ensure su?cient conductivity. The results indicated that Vfb/Vt ratios are largely set during polySi deposition and remain virtually unchanged during gate implantation and thermal activation, independent of the p-type dopant (B, Al, Ga). The p-FET Vt shift is thus a fundamental phenomenon that is not easily prevented by employing modi?ed polySi/Hf(Si)O(N) formation conditions. A reaction of Si with the Hf-based material, occurring already during polySi deposition, appears to be the root cause for the poor Vfb/Vt control. The introduction of Si or N into the Hf-based layer has a limited impact on Vt/Vfb. As expected, when utilizing HfSiO with increasing Si content, Vfb gradually approaches the value observed with SiO2 (Figure 4, inset) [67, 69–72]. However, in order to bring Vt to within less than 0.3 V from the target value, Hf contents below ;20% are required. At such compositions, the dielectric constant is only marginally higher than for SiON, making

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implementation unattractive. As mentioned above, ?xed charge from N incorporated into the gate stacks (in particular, into the bottom interface) is another means of controlling Vt. However, only a limited degree of Vt improvement (by up to ;0.1 V) is achieved in this manner, at the expense of mobility loss [57]. Recent experimental evidence indicates that oxygen plays a prominent role in the p-FET Vt shift phenomenon. It was demonstrated that oxidation of the polySi/high-j stack by lateral indi?usion of oxygen can alleviate the p-FET Vt shift of transistor devices with channel lengths below ;1 lm at the expense of EOT [73]. Also, optical spectroscopy was used to relate trap levels in HfO2 to oxygen de?ciencies [74]. It is likely that these results are related to recent ?ndings for metal/high-j gate stacks, which are discussed in detail in the next section. There, it is demonstrated that p-FET Vt can vary by as much as 0.75 V, depending on O2 partial pressure and temperature during post-deposition gas anneals [75]. Fermi-level pinning has often been invoked as a fundamental mechanism causing the Vt shift, in analogy with a phenomenon that has long impeded successful fabrication of high-quality gate stacks on compound semiconductors [76, 77]. Fermi-level pinning is caused by a high areal density of interface states whose occupation changes as the gate voltage is swept from conditions of accumulation to inversion. The interface states partially screen the electric ?eld from the gate electrode, preventing it from reaching the channel. The extent of gate-induced tuning of the channel carrier occupancy is thus greatly reduced. In the ?rst detailed discussions of the p-FET Vt shift with Hf-based high-j materials [67– 69], it was argued that Fermi-level pinning just below the polySi conduction band is caused by Hf–Si bonds at the high-j/polySi interface. Direct physical evidence for such bonds is scarce, but this picture is broadly consistent with the experimentally observed impact of oxygen de?ciencies on Vt. However, defect levels and ?xed charge in the Hf-based gate dielectric itself may similarly cause Vt shifts. It has been reported, for example, that O vacancy formation in HfO2 is energetically favorable when the HfO2 is in contact with a p-doped polySi gate, since such defect states are stabilized by the transfer of two electrons to the gate electrode [74, 78, 79]; this transfer cannot occur in contact with an n-doped polySi gate. Positive ?xed charge is thus created inside the HfO2, shifting the p-FET Vt to more negative values, which provides an explanation for the experimentally observed Vt behavior. More generally, potential physical causes for ?xed charge are vacancies or interstitials, foreign atoms such as Si, N, or gate dopants di?used into the high-j layer. Si and N are not candidate species causing the p-FET Vt problem, since N-free HfO2/SiO2 stacks su?er from it, and since the intentional introduction of Si partially

0.7

Flat-band voltage shift (V)

0.6 0.5 0.4 0.3 0.2 0.1 0.0 Hf silicate 1.5 nm 2.0 nm 20 40 60 80 100 Si content, Si/(Hf Si) (%) 0.5

Si content: 40% 10–20% 60% 80%

1.0 1.5 2.0 2.5 Equivalent oxide thickness (nm)

3.0

Figure 4
EOT and composition (inset) dependence of V shift for polySifb gated p-FETs with HfSiO gate dielectric. From [70], with permission; ?2004 IEEE.

alleviates the issue (see below). The impact of gate dopants was excluded by the careful experimental studies discussed above [70]. Owing to the accumulating evidence regarding the importance of O, and a better understanding of the electronic structure and formation enthalpy of O vacancies in HfO2, such vacancies are currently considered to be the most likely origin of the Vt shifts. However, more physical characterization experiments are required in order to conclusively distinguish such defects from interfacial Hf–Si bonds. From a technological perspective, it is critical to determine whether the p-FET Vt can be shifted closer to the target value by choosing appropriate processing conditions. As mentioned above, lateral oxidation of the high-j layer brings partial relief for short-channel devices [73]. However, the concomitant growth of SiO2 at the gate electrode interface increases the EOT, O indi?usion and hence Vt are dependent on channel length, and it is unclear whether the O content of the gate stack can be maintained during the entire device fabrication process. These factors limit the implementation of lateral oxidation. Motivated by the Hf–Si bond theory, e?orts have recently concentrated on thin dielectric cap layers inserted between the Hf-based dielectric and the polySi electrode. However, success with this approach has been mixed, notably weakening the Hf–Si bond theory. For example, Si3N4 [70–72], SiC:H [72], and HfON [80] cap layers lead to only very small Vt improvement. With SiO2 cap layers, moderate Vt improvement (by 0.3 V) has been achieved at a cap thickness of 1 nm [71] (though dissimilar results have been reported [72]). However, SiO2 capping severely limits thickness scaling and e?ectively defeats the purpose of introducing high-j materials.

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1.20 Capacitance density ( F/cm 2) 1.00 0.80 0.60 cap/HfSiO/SiON 0.40 0.20 Split C–V 0.00 1.5 1.0 cap/HfSiO/SiO2 (n-FET: etched) Conventional HfSiO 0.5 0.0 0.5 Gate voltage (V) (a) 1.0 1.5 p-FET SiON

n-FET

10 10 Drain current (A) 10 10 10 10 10

4 5 6 7 8 9 10

Vd

1.2 V SiON

Vd

0.05 V

Optimized Highp-FET 1.5 1.0 0.5 0.0 0.5 Gate voltage (V) (b) n-FET 1.0 1.5

Figure 5
(a) Split C–V characteristics for AlN-capped p-FET and AlNcapped/etched n-FET high- stacks on two interfaces compared with conventional HfSiO and SiON. (b) Id–Vg characteristics for AlN-capped p-FET (EOT 1.9 nm) and AlN-capped/etched n-FET (EOT 2.0 nm) high- stacks compared with SiON. From [60], with permission; ?2005 IEEE.

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Several studies have concentrated on Al2O3 cap layers, often grown by ALD. Reported improvements range from 0.1 to 0.3 V on HfSiO [70, 81, 82] to 0.6–0.7 V on HfSiON [83]. These variations indicate that process control may be an issue. The most likely mechanism of Vt improvement is through negative ?xed charge introduced into the Hf-based material by the Al, as is the case for HfAlO gate dielectrics [38]. A possible concern with Al2O3 cap layers is charge trapping under operation conditions, which is a known issue for pure Al2O3 gate dielectrics [14]. In Al2O3/HfSiO stacks, however, the degree of trapping inside the HfSiO appears to be essentially independent of cap thickness [84]. Still, it may be bene?cial to reduce cap thickness to a minimum, since with increasing cap thickness the distance of the trap

sites from the gate electrode increases and, in turn, the Vfb shift induced by trapped charges increases. Recently, aluminum nitride (AlN) was introduced as a novel cap material that reproducibly ensures su?cient Vt improvement at very low cap thickness and high e?ective permittivity [60, 85]. Hf-based stacks were thus engineered such that the n-FET and p-FET Vt are su?ciently low, with excellent device characteristics. To this end, the AlN cap was deposited onto the HfSiO on both p-FETs and n-FETs, and subsequently etched o? the n-FETs. Selective capping of p-FETs only is thus achieved. Separate wafers were employed, but full CMOS integration is possible through a masking/etching scheme. Figure 5(a) shows C–V curves for optimized p-FET and n-FET polySi/(AlN)/HfSiO gate stacks [60]. The physical thickness of the AlN cap is only 0.4 nm; more signi?cantly, because of the high dielectric constant of the AlN, this cap contributes only 0.1 nm to the total EOT, ensuring scalability [85]. The p-FET Vt shift is reduced to only ?0.22 V to ?0.31 V compared with a SiON control, depending on the Si/high-j interface layer. For n-FETs, we ?nd DVt ? 0.21 V, similar to conventional polySi/ Hf(Si)O stacks. Thus, we obtain nearly symmetric C–V characteristics with low Vt. These ?ndings are con?rmed by Id–Vg data [Figure 5(b)]. A small subthreshold swing of 71 mV/dec indicates that the interface state density is low. This was con?rmed by amplitude sweep charge pumping data, which demonstrates that n-FET Dit ; 1010 eV?1-cm?2 and p-FET Dit ; 7 3 1010 eV?1-cm?2 [60]. The p-FET Vt improves slightly with decreasing thickness [60], indicating further scalability. Also, the Vt-optimized high-j-based FETs show good performance: Mobilities and drain currents for p-FETs and n-FETs range between 90 and 110% of those for a SiON control [60]. A narrow distribution of breakdown voltages indicates the uniform quality of the dielectric. Stressinduced n-FET Vt shifts due to charge trapping are su?ciently low to meet the ten-year device lifetime targets. By combining this capped gate stack with moderate implant engineering for ?nal Vt adjustment, short-channel polySi/(AlN)/HfSiO devices with acceptable performance have been manufactured [85]. In conclusion, O vacancies, or perhaps Hf–Si bonds, in Hf-based polySi/high-j gate stacks are the predominant cause of the observed Vt shifts. It is unclear whether O can be reintroduced into the stack without unacceptable SiO2 growth, and whether such O content can be maintained throughout a full CMOS integration ?ow. Though unsuccessful in most cases, cap layers deposited onto the Hf-based dielectric have recently shown promise for Vt control. It has been demonstrated that su?cient Vt improvement with a scalable cap layer can be achieved without signi?cantly degrading drive current. In

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conjunction with implant engineering, this opens up opportunities for polySi/high-j devices. In summary, we have reviewed how thermal stability and mobility requirements have guided the trend of polySi/high-j devices from HfO2 to HfSiO. The incorporation of additional N not only further suppresses high-j crystallization, but also increases the dielectric constant and aids interfacial layer scaling. However, N close to the channel introduces ?xed charge that degrades carrier mobility through Coulomb scattering. Thresholdvoltage o?set of polySi devices incorporating Hf-based high-j dielectrics is probably caused by an O de?ciency of the gate stack. Scalable AlN capping layers have been developed that enable p-FET Vt control without degrading device performance. Combined with channel engineering by ion implantation, selective p-FET implementation of such AlN/HfSiO gate dielectrics holds promise for successful polySi/high-j CMOS fabrication.

Stability on SiO2 in FG
700 C 700 C

13 14 IIIA IVA
B C Si Ge Sn Pb

3 4 5 6 7 8 IIIB IVB VB VIB VIIB
Sc Y La Tin Zr n Hf n W2Nn Vn Nbn Tan Cr Mom Wm Mn n Tc Re p Fe Ru p Os

9 10 VIII
Co p Rh p Ir p Ni p Pd p Pt p

11 12 n IB IIB Al
Cu Ag Zn Cd Ga In Tl CoSi2m

Au Hg RuO2p

Ta2Nn

TaSiNn

TaSiNn (a)

Stability on Al2O3 in FG
700 C 700 C

13 14 IIIA IVA
B C Si Ge Sn Pb

3 4 5 6 7 8 IIIB IVB VB VIB VIIB
Sc Tin Y La Zr n Hf n Vn Nb n Tan

9 10 VIII

11 12 n IB IIB Al
Zn Cd Ga In Tl

3. Metal gates
The previous section has shown that while high-j dielectrics are clearly required to scale beyond the 45-nm node, the integration of Hf-based dielectrics with polySi electrodes su?ers from a number of drawbacks, including high p-FET Vt and di?culty in scaling below Tinv of 2 nm. The use of metal gates helps to overcome some of these hurdles. In this section, we summarize the advances and challenges remaining for metal/high-j stacks. We show that aggressively scaled metal/high-j stacks (Tinv ? 1.4 nm) with high electron mobility can be achieved in a conventional self-aligned process by careful process optimization, including the use of non-nitrogen interface layers, high-temperature processing, and appropriate electrode structures to prevent regrowth. However, Vfb/Vt instability after high-temperature processing remains the biggest challenge to overcome, with oxygen vacancies in the high-j resulting in large Vfb/Vt shifts for highworkfunction (um) metal gates. Thermal stability For compatibility with conventional self-aligned processing, thermally stable metal electrodes were required. This led to our initial evaluation of di?erent metal electrode/dielectric gate stacks by in situ X-ray di?raction (XRD). An electrode was considered unstable if the XRD analysis showed a deviation from the typical linear decrease in di?raction angle (2h) as a function of temperature [86]. This suggested the reaction and/or formation of a new phase with a di?erent crystal structure. On the basis of this criterion, possible stable electrode choices were narrowed down as shown in Figure 6. Most of the low-um elemental metal gates (um ? 4.1 to 4.3 eV), indicated by light shading, were

Cr Mn n Fe Co p Ni p Cu Mom Wm Tc Re p Ru p Os Rh p Ir p (b) Pd p Pt p Ag

Au Hg

Figure 6
(a) Periodic table indicating the thermal stability of different electrode materials on SiO2 evaluated using in situ XRD, resistance, and optical scattering analysis techniques. Superscripts following the chemical symbols indicate the type of workfunction: n n-FET, m midgap, and p p-FET. The shading indicates whether the thermal stability is less than 700 C (light gray) or greater than 700 C (darker gray). (b) Thermal stability of different electrode materials on Al2O3 [nomenclature similar to part (a)]. Adapted from [86], reproduced with permission.

reactive and did not withstand conventional CMOS annealing temperatures. The exceptions were TaN and TaSiN, which were reported to have low n-FET um yet remain stable to high temperatures. On the other hand, most of the midgap (including TiN [87], not shown) and high-um metal gates (um ? 4.9 to 5.2 eV), indicated by darker shading, remained stable to high temperatures (800 –1,0008C). In summary, while most of the p-FET gate metals and alloys were structurally stable at high temperatures, conventional CMOS processing that requires temperatures greater than 9508C may not be an integration option for most elemental n-FET electrodes. These thermal stability constraints were a catalyst for the development of a gate-last or replacement-gate process. Typically, the process requires that after a source/drain (S/D) activation anneal and silicide formation for a conventional polySi/SiON integration

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350 Mobility (cm 2 /V-s) 300 250 200 150 100 50 0 W/HfO2 /SiON T inv 2 nm n-FET 12 polySi/SiON

1 MV/cm) at Tinv of 1.5 nm have been observed for a non-nitrogen-based electrode and dielectric process. However, the viability of the replacement gate process for gate lengths of less than 25 nm remains questionable and depends on the development of an extremely conformal dielectric and electrode deposition process. Metal/SiON vs. metal/high-j stacks Metal/SiON gate stacks may not be well suited for highperformance logic applications because they do not provide an improvement in leakage and also place severe limitations on deposition processes. Low-damage deposition processes such as ALD or CVD are preferred, since physical vapor deposition (PVD) processes result in sputter damage to the thin oxynitride dielectric layer. Such stringent requirements on deposition processes are not required for the integration of metal/HfO2 gate stacks, since these stacks have a physically thicker high-j dielectric (compared with SiON) that results in lower gate leakage; more signi?cantly, these stacks are more thermodynamically stable at elevated temperatures than metal/SiO2 stacks [90]. This allows for the possibility of a ‘‘gate-?rst’’ conventional process integration scheme. Thus, the integration complexity of introducing a metal gate for high-performance CMOS requires that both metal and high-j be introduced at the same time for an overall bene?t to be achieved in scaling and leakage. Unfortunately, aggressively scaled metal/high-j stacks su?er from electron mobility degradation [87, 91] and Vfb/Vt instabilities [75, 92]. Electron mobility In the subsection on thermal stability, it was shown that the low-temperature-processed metal/high-j devices su?er from degraded electron mobility. The e?ect of high-temperature processing on the n-FET mobility of W/HfO2/SiO2 stacks was evaluated using a simple nonself-aligned integration ?ow, with devices processed between 6008C and 1,0008C. It was shown that even with low interface-state densities (Nit), low-temperature (,6008C) processing resulted in extremely low electron mobilities [93]. Increasing the thermal budget resulted in signi?cantly improved mobilities, but at the expense of Tinv due to interlayer (IL) regrowth. Using a non-selfaligned ?ow [94], n-FET-like CVD TaSiN/HfO2 gate stacks were also fabricated, and the mobility compared with CVD W/HfO2 after high-temperature processing (Figure 8). As with the replacement-gate results, it is observed that the presence of N at the interface for both gate electrode stacks clearly degrades the electron mobility. This not entirely unexpected, as nitrogen is also the potential cause of the reduction of mobilities for aggressively scaled polySi/SiON devices. For the nonnitrogen ILs, it was not clear whether the observed

2 4 6 8 10 Inversion carrier density (1012 /cm 2) (a)
Center of trench tr

W 13 ? 15 ? HfOx SiOx

14 ? 16 ?

7?

Si 20 ? (b)

Figure 7
(a) Electron mobility of a CVD W/HfO2/SiON replacement-gate device compared with a polySi/SiON control device. (b) Representative TEM image of the center of a replacement-gate trench.

396

scheme, nitride and oxide are deposited, and this is followed by planarization using chemical–mechanical polishing (CMP). The sacri?cial polySi gate and SiON dielectrics are selectively removed, and the new SiON (or high-j) is grown (or deposited), followed by deposition of the metal gate. After deposition, the highest temperatures to which the gate stacks are exposed are those observed in the back end, which are typically ,5008C. Using the replacement-gate integration scheme and CVD W as a metal gate, CMOS transistors down to 0.1 lm were successfully fabricated [88]. It was shown that while the hole mobility of p-FETs remains as good and in some cases better than that of polySi/SiON controls, the electron mobility for W/SiO2, W/SiON [88], and W/HfO2/SiON [Figure 7(a)] were degraded by more than 20% compared with polySi/SiON gate stacks of similar Tinv. It was also clear that the presence of N in the gate stack further degrades the electron mobility for a lowtemperature integration process [88]. Figure 7(b) is a representative TEM image of the center of a 1-lm trench for a W/HfO2/SiON stack. The thickness variation of the HfO2 (intended to be 2.5 nm) clearly demonstrates the conformality issues to be overcome for gate lengths of less than 45 nm. Signi?cant advances have been made with the replacement-gate process [89], in which high electron mobility (250 cm2/V-s at peak and 190 cm2/V-s at

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improvement in mobility was due only to the thickening of the IL or whether the composition of the IL had also been modi?ed and also played a role. It has been suggested that the Hf intermixes with a non-nitrogen IL (from comparison of high-resolution TEM and electrical measurements) to form a higher-j Hf-silicate IL [93] that results in higher mobility than HfO2, since it has a weaker coupling of the SO phonons compared with HfO2 [95]. However, a number of research groups have chemically analyzed the IL using low-loss electron energy loss spectroscopy [96] and medium-energy ion scattering [97] and show no evidence for Hf-silicate formation upon annealing. Alternatively, it has also been suggested that the IL is Si-rich, resulting in a dielectric constant greater than that of SiO2 [98]. In summary, the composition of the IL is currently a topic of intense debate in the high-j community, and its impact on the mobility of high-j stacks is not well understood. To understand the e?ect of processing temperature on electron mobility and to decouple the role of the IL thickening from mobility improvement of metal/HfO2 stacks, we have used PVD TaSiN, a well-known oxygen di?usion barrier which is known to minimize IL thickening, so that the contribution of the IL to mobility improvement remains constant. For the explicit purpose of dopant activation at low temperature, we used the solid phase epitaxial regrowth (SPER) [99] process, which uses high-energy As implants for S/D amorphization followed by a 6008C anneal, in combination with NiSi S/D and gate contacts to fabricate self-aligned n-FETs at low temperatures. Some wafers were subjected to an additional 8008C, 5 s and 1,0008C, 5 s anneal after SPER and prior to NiSi formation to observe the impact of high-temperature activation. Figure 9(a) shows that substantial improvement in mobility (25%, peak) is observed for both TaSiN/HfO2/SiON and a control TaSiN/SiON stack only after 1,0008C anneals with little change in Tinv. It is clear that the mobility increase is neither related to IL regrowth (Tinv remains about the same; see the ?gure caption), nor a?ected by Nit variations, as the mobility curves are corrected for Nit [100]. These results show unequivocally that the high thermal budget modi?es the dielectric stack without interfacial regrowth to enhance the mobility. The mobility enhancement can be related to the formation of a relaxed IL/Si interface at T . 9508C [101] or, in addition, especially for the high-j gate stacks, to structural relaxation and modi?cation of the HfO2/IL interface. We have recently obtained high-mobility devices at aggressive Tinv, for self-aligned metal-gated high-j transistors [102] with oxide starting surfaces by capping di?erent thin metal gate stacks such as PVD TiN, ALD

400 W L

After 1,000?C, 5 s RTA TaSiN/HfO2 /SiON W/HfO2 /SiON W/HfO2 /SiO2 Universal

300 Mobility (cm 2 /V-s)

20 m 5 m

200 T inv ~ 2 nm 100 T inv ~ 1.7 nm 0 0.0 T inv ~ 1.6 nm

5.0 1012 Inversion charge (Q/cm 2)

1.0

1013

Figure 8
Electron mobility comparison of TaSiN/HfO2/SiON, W/HfO2/SiON, and W/HfO2 /SiO2 stacks after high-temperature annealing. Adapted from [94], reproduced with permission; ?2004 IEEE.

TaN, and CVD W with polySi [Figures 9(b), 9(c)]. To prevent reactions between W and polySi at T . 8008C, a TiN barrier layer was inserted between the W and polySi layers. PolySi/TiN/HfO2 gate stacks were shown to have record electron mobilities at a Tinv of 1.4 nm better than previously reported [103, 104]. We believe that by careful process optimization such as the use of nonnitrogen interface layers, high-temperature processing, low Nit (,3 3 1010 cm?2-eV?1), and appropriate electrode and electrode structures to prevent interfacial regrowth, we have largely minimized undesirable sources of Coulomb scattering. This results in high mobility in aggressively scaled metal/high-j stacks that are competitive or better than aggressive polySi/SiON stacks [Figure 10(a)]. We also show that these high-mobility stacks still maintain more than 4–5 orders of leakage reduction compared with polySi/SiON [Figure 10(b)]. Metal gate screening of the soft optical phonon modes in the high-j (the primary reason for reduced mobility of polySi/high-j as proposed by Fischetti et al. [95] and experimentally veri?ed by Ren et al. [59]) has been proposed as a possible reason for improvement in mobility [103]. However, we have recently shown with low-temperature mobility measurements of aggressively scaled metal-gated high-j stacks4 that electron mobility is still limited by HfO2 SO-phonon scattering.
K. Maitra, V. Narayanan, and E. Cartier, ‘‘Investigation of Metal Gate Screening in Aggressively Scaled HfO2/metal n-MOSFETs by Low Temperature Mobility Measurements,’’ to be submitted to IEEE Electron Device Lett. (2006).
4

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350 TaSiN/SiON 300 Capacitance density ( F/cm 2) Mobility (cm 2 /V-s) 250 200 150 100 50 0 TaSiN/HfO2 /SiON SPER 1,000 C SPER 800 C SPER (600 C) 0 5 10 Ninv (1012 cm 2) (a)

2.5

300

Electron mobility (cm 2 /V-s)

2.0

250 200

1.5

150 100 50 CVD W PVD TiN ALD TaN

1.0 CVD W PVD TiN ALD TaN HfO2 /SiO2 0.0 0.0 0.5 1.0 Gate voltage (V) (b)

0.5

0 0 5 10 Ninv (1012 /cm 2 ) (c) 15

Figure 9
(a) Comparison of electron mobilities for TaSiN/HfO2 /SiON and TaSiN/SiON gate stacks, for three different process temperatures. Inversion thickness (Tinv) values corresponding to these process temperatures are respectively 1.7 nm, 1.5 nm, and 1.6 nm for the HfO2/SiON stacks and 2.3 nm, 2.3 nm, and 2.4 nm for the SiON stacks. (b) Inversion split-C–V characteristics and (c) electron mobility curves of self-aligned metal/HfO2/SiO2 n-FET gate stacks after a 1,000 C, 5-s RTA. Tinv values for CVD W, PVD TiN, and ALD TaN are 2.05 nm, 1.4 nm, and 1.7 nm, respectively. Channel doping was Na 1 1017 cm 3 for all stacks. Adapted from [102], reproduced with permission; ?2006 IEEE.

0.1 Electron mobility (cm 2 /V-s) 250

0.6

EOT (nm) 1.1

1.6

2.1

107 105 10 102 103 103 104 101 105 10 10
1

200

150

This work HfO2 /TaN Ref. [103] HfO2 /TiN Ref. [104] Ref. [91] Ref. [93] Ref. [89] PolySi/SiON control PolySi/SiON Ref. [104]

Measured at Vt

1V Metal/highPolySi/SiON

Jg (A/cm 2)

HfO2 /W

3 5

100

@ 1 MV/cm 0.5 1.0 1.5 T inv (nm) (a) 2.0 2.5 10

1.0

1.5

2.0 2.5 T inv (nm) (b)

3.0

Figure 10
(a) Comparison of electron mobility (at 1 MV/cm) vs. inversion thickness (Tinv) for different metal-gated HfO2 gate stacks. Adapted from [102], reproduced with permission; ?2006 IEEE. (b) Comparison of gate leakage as a function of Tinv for metal/high- and polySi/SiON gate stacks.

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Tinv scaling Figures 9(b) and 10(a) show a signi?cant di?erence in Tinv for di?erent electrode stacks that are processed under nominally identical process conditions. After a hightemperature process, W-gated devices capped by TiN and polySi are at least 0.5 nm thicker in Tinv than an equivalent polySi/TiN device. Since the W is completely

encapsulated during the S/D activation by TiN/polySi and nitride spacers, the increased Tinv can only be attributed to residual oxygen present in the W [105] that is released upon annealing as atomic species and oxidizes the Si substrate surface. This kind of regrowth has been observed with other relatively high-workfunction and refractory metals such as Re [75] and suggests that

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Capacitance density ( F/cm 2)

Capacitance density ( F/cm 2)

2.4 2.0 1.6 1.2 0.8 0.4 0.0 0.5 RTA: 900 C, 5 s Area: 100 m 100 m 0.0 0.5 1.0 1.5 Gate voltage (V) (a) PolySi/TaSiN PolySi/TiN/Re PolySi/TaSiN/Re 2.0

3.0 2.5 2.0 1.5 1.0 0.5

Capacitance density ( F/cm 2)

Gate dielectric: HfO2/SiON

Gate dielectric: HfO2/SiO2 100 kHz Area: 4 m 4 m

2.5 2.0 1.5

n-Si/ChemOx/ 2.5 nm HfO2/Re HfO2 Si Re Si HfO2

+ Re Vfb ~ 0.2 V

Vfb ~ 0.9 V

1.0 0.5 0.0

As-deposited Area: 100 m 100 m 1 2 Gate voltage (V) (c) O2/N2 anneal 550 C, 100 ppm O2 350 C, 10 ppm O2

[Vo]

0.0 1.0 0.5 0.0 0.5 1.0 1.5 2.0 2.5 Gate voltage (V) (b) e-beam Re (as-deposited) CVD Re (as-deposited) e-beam Re (after 450 C FGA)

(d)

Figure 11
(a) High-frequency (100-kHz) C–V characteristics of different polySi-capped metal gated stacks clearly showing the midgap-like Vfb for both TaSiN and Re gate stacks after 900 C, 5-s RTA. (b) Comparison of C–V characteristics of Re/HfO2/SiO2 gate stacks with CVD Re (grown at 500 C) and e-beam-evaporated Re (25 C), respectively. Adapted from [75], reproduced with permission. (c) High-frequency (100-kHz) C–V characteristics of SiO2/HfO2 /CVD Re showing that flatband voltage shifts can be induced in oxidizing ambient without incurring interfacial oxide regrowth, if low temperatures and low O2 partial pressures are used. (No passivation was performed on these devices, causing C–V stretch-out). (d) Schematics explaining the impact of oxygen vacancies, [VO ], and of “dipole” formation due to electron transfer from the HfO2 to the Re. The magnitude of the Vfb shift depends on the oxygen vacancy concentration and the distribution in the HfO2 layer. Adapted from [75], reproduced with permission; ?2005 IEEE.

possible hurdles may exist for the scaling of high-um p-FET electrodes. Vt / Vfb stability—Role of oxygen vacancies A key problem that a?ects metal-gate/high-j stacks is the Vt/Vfb stability of metal gates when in contact with Hfbased dielectrics. This remains probably the toughest challenge for the introduction of metal gates and can be summed up as follows: The Vt/Vfb values for metal/high-j stacks predicted using the metal workfunction are accurate for low-temperature-processed devices, but thermal processing induces signi?cant drift, usually toward a midgap e?ective workfunction ( EWF). An illustration of this e?ect is shown in Figure 11(a) for PVD TaSiN/HfO2 and CVD Re/HfO2 devices, in which, after hightemperature anneals, the di?erence in Vfb (a measure of the EWF for aggressively scaled devices) is less than 100 mV. The reported um of these materials is 4.4 eV [106] and 4.9 eV [107]. We reported previously by using the barrier height technique to evaluate um that some of these Vfb shifts that are observed upon annealing are due to ?xed charge [108] as interpreted by the di?erence between the um obtained from the barrier height technique (which yields values similar to reported um values) and that extracted from C–Vs. However, it is becoming increasingly apparent industrywide that for high-um metal gates, the observed EWF on HfO2 can be shifted by more than 500 mV from the expected um

upon exposure to moderately high temperatures and/or reducing ambients. This shift in Vfb is qualitatively similar to the high Vfb shift observed for p?polySi/HfO2 gate stacks, where the shift was attributed to Fermi-level pinning [68, 69, 109]. Using Re/HfO2 gate stacks [75], we illustrate this e?ect and show that for room-temperaturedeposited e-beam Re, reducing ambients at moderate temperature can shift the Vfb of MOS capacitors by ;700 mV [Figure 11(b)]. The Vfb for the forming-gasannealed e-beam Re/HfO2 stacks is very similar to asdeposited CVD Re/HfO2 ?lms that are grown at 5008C under reducing conditions. These kinds of similar shifts have also been observed for Ru/HfO2 [75] and Pt/HfO2 [92]. However, we have also shown that by using appropriate low-temperature oxidizing ambients, some of this Vfb shift is recoverable without interfacial regrowth [Figure 11(c)] [75]. Thus, we strongly believe that the Vfb modulation is related to the oxygen vacancy concentration [Vo] in the HfO2 near the Re contact. Recently Shiraishi et al. [78, 79] have attributed the Fermi-level pinning e?ect for p?polySi/HfO2 to the generation of an interfacial dipole formed by the evolution of charged oxygen vacancies. By a similar analogy, we believe that the introduction of a high-um metal gate adjacent to the HfO2 allows for the following reaction: O0 ! V?? ? 2e? ? ? O2 : Since this reaction is o thermally activated, there is no driving force at room temperature for the reaction to proceed (consistent with

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10

1

NiSi gate

high temperatures, have unusually high Vfb shifts that might be related to the oxygen vacancy concentrations in the HfO2 or HfSiO gate dielectric. Charge trapping and NBTI Unlike polySi/HfO2 stacks which su?er from signi?cant charge-trapping concerns [14, 113, 114], metal/high-j gate stacks have been shown to have very good Vt stability under constant stress conditions; this is illustrated in Figure 12 [115]. Compared with W/HfO2, both FUSI/HfO2 and polySi/HfO2 su?er from signi?cant charge trapping. This degradation is very unlikely to come from the FUSI process, since it is not seen on SiO2 control devices with FUSI gates. These observations combined with the metal gate data strongly indicate that reaction(s) between polySi gates and high-j dielectrics may be responsible for defect creation that leads to enhanced charge trapping, with most of these trapping e?ects being eliminated by the use of metal gates. Degradation related to NBTI (negative biased temperature instability) in scaled W/HfO2 replacementgate p-FETs has also been shown to be comparable to polySi/SiON, suggesting that NBTI is not a problem for aggressive metal-gate/high-j stacks [116]. To conclude this section, substantial mobility improvements in metal-gated high-j systems at an aggressive Tinv of 1.4 nm which are as good as or better than those of aggressive polySi/SiON stacks have been achieved. High-temperature processing and nitrogen in the interface layer appear to in?uence this improvement strongly, though careful process optimization has helped in overcoming mobility as a problem for aggressive stacks. Workfunction stability remains the most signi?cant challenge to overcome, with oxygen vacancies in the high-j resulting in large Vfb/Vt shifts for highworkfunction metal gates. Low-workfunction metal gates are either unstable at high temperatures or are still signi?cantly shifted from the Si conduction band edge. We therefore believe that signi?cant changes to conventional integration schemes would be required in order to obtain high-mobility and band-edge workfunction metal/high-j stacks.

Vt (V)

10

2

PolySi gate W gate

10

3

3 nm HfO2 /SiOxNy interface Vstress 1.5 V, 140 C 101 103 Stress time (s) 105

Figure 12
Comparison of Vt instability in polySi, fully silicided (FUSI), and metal gate stacks with the same high- stressed under identical conditions. Adapted from [115], reproduced with permission; ?2004 IEEE.

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the as-deposited e-beam Re/HfO2 measurements). It has been predicted theoretically that the oxygen vacancy defect level in the HfO2 is aligned close to the silicon conduction band [110]. Therefore, at moderately high temperatures, the presence of a high-um metal with its Fermi level aligned close to the valence band of Si provides the necessary driving force to generate charged oxygen vacancies and lose 2e? to the metal. This results in a dipole layer that changes the e?ective gate workfunction and the corresponding Vfb by pulling it toward midgap, as illustrated in Figure 11(d). By introducing oxygen to the system, we can e?ectively neutralize the oxygen vacancies near the metal/high-j interface, thereby recovering the high um of the metal gate, as shown in Figure 11(c). It has also been suggested that these shifts could be attributed to metal-induced gap states (MIGS), an intrinsic e?ect in which the EWF is modulated by the charge neutrality level and pinning parameter [111], which are well known for HfO2. Recently, Lim et al. [112] have shown quite convincingly that for as-deposited highum gate metals, the EWF can be well predicted by the MIGS model; however, upon even moderate annealing the realized EWF can be explained only by the vacancy model. Thus, oxygen movement and its role in modulating oxygen vacancy (Vo) formation in the high-j is strongly coupled with the gate electrode and is responsible for the low EWFs that are observed for materials that have high um. In summary, most of the n-FET metals or alloys are either unstable at high temperatures or at best have EWFs that are more than 200 mV from the Si conduction band edge (for example TaSiN, TaSi2.5, or TaC). On the other hand, p-FET metals and alloys, though stable at

4. Gate stacks with FUSI metal gates
As discussed above, using metal gates o?ers many bene?ts for CMOS scaling, in particular lower Tinv due to eliminated polySi depletion. The process ?ow described in Section 3 included metallic material deposited directly on gate dielectric regardless of the ‘‘gate-?rst’’ or ‘‘gate-last’’ integration scheme. An alternative attractive approach to fabricating metallic gates is to convert a conventional polySi gate into a silicide material which, after silicidation transformation, is in direct contact with the dielectric ?lm. Most metal silicide materials are known to have

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1. Gate definition (polySi contact dry etch) Gate oxide STI STI polySi STI STI

4. Passivation overlayer

2. Form spacers

5. CMP planarization

3. S/D silicidation Silicide

6. Cap removal followed by FUSI

Figure 13
Schematic integration scheme for fully silicided (FUSI) gate dielectrics utilizing the CMP approach. In this approach, source/drain and gate are silicided separately.

metal-like low electrical resistivities, typically of the order of 10–100 lX-cm [117–119]. Low resistivity and selectivity to form silicides only in the areas where metal is in direct contact with silicon (the so-called ‘‘selfaligned’’ process) have made them a key contact element of modern ULSI transistors [117]. As a result of many years of focused research and development in this area, silicide materials and processes are fairly well understood. One should mention that the idea of complete silicidation of a polySi gate was proposed in the late 1970s [117 –120]. At that time, the polysilicon depletion e?ect was not a big issue, and the focus was more on ?nding low-resistance contact materials with high reliability. The situation has changed drastically over the past several years with the requirement of reducing electrical thickness of the gate stack in inversion without gate leakage penalty. Several groups have explored full silicidation (FUSI) of conventional polySi gates and observed an encouraging e?ect of reduced Tinv for the same physical structure and thickness of the dielectric stack [21, 121 –144]. Several integration routes to fabricate fully silicided gates have been reported, some involving CMP steps and others not. One popular approach is shown schematically in Figure 13. The integration scheme remains a conventional front-end-of-line (FEOL) process ?ow including polysilicon gate de?nition and patterning, ion implantation into extension regions, spacer formation, source/drain ion implantation and silicide contacts, and an oxide passivation layer. After that, FUSI-speci?c steps include 1) CMP planarization of the passivation

overlayer; 2) removal of the cap layer on top of the polySi gate; and 3) metal deposition at the thickness su?cient to fully silicide the polySi gate after moderate annealing, typically at 400 – 6008C. In this approach, source/drain and gate silicidation are performed separately. To sum up, FUSI gate integration is clearly similar to the conventional CMOS process ?ow, and therefore o?ers several advantages over the more complex standard metal gates described above. In fact, short-channel FUSI devices have been demonstrated for 65-nm- and 45-nm-technology nodes. With respect to silicide materials for FUSI gates, most of the ones explored so far are common silicides that are already in use for source/drain contacts or other microelectronics processes, such as molybdenum silicides [119, 120, 138], tungsten silicides [122], titanium silicides [136], hafnium silicides [134], platinum silicides [131, 133], cobalt silicides [123, 141] and nickel silicides [21, 121, 124–144], germanides, and alloys. Nickel-based silicide materials are emerging as a leading candidate for FUSI gates for several reasons: 1) low resistivity (;15 – 25 lX-cm; 2) low volume expansion (less than 20%); and 3) the fact that this material has already been introduced into Si FEOL processing for sub-90-nmtechnology nodes. More signi?cantly, nickel silicide is formed by Ni indi?usion into the polySi gate, therefore allowing complete silicidation without forming voids. As an illustration, a comparison of cobalt silicide and nickel silicide gates is shown in Figure 14. In contrast to nickel silicidation, silicon atoms are the main di?using species during cobalt monosilicide formation, resulting in

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70 nm (a)

80 nm (b)

Figure 14
Cross-sectional SEM image of short-channel fully silicided (FUSI) devices with (a) CoSi2 and (b) NiSi gates.

160 140 Capacitance (pF) 120 100 80 60 40 20 0 2

Tqm gain ~ 1.5 A

T inv gain ~ 5 A

~ 0.55 V

FUSI n polySi control 100 1 0 Gate bias (V) (a) 1 100 n-FETs 2

160 140 Capacitance (pF) 120 100 80 60 40 20 0

T inv gain ~ 5 A

Tqm < 1 A

FUSI p polySi control 100 2 1 0 Gate bias (V) (b)

~ 0.55 V

100 p-FETs 2

1

Figure 15
High-frequency (100-kHz) C–V measurements on (a) n-FET and (b) p-FET devices with fully silicided (FUSI) and polySi devices with SiON gate dielectrics. Tinv gain due to polySi-depletion elimination and Vt shifts are shown. Tqm IBM equivalent oxide thickness metric [1].

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void formation at the gate dielectric interface. Generally speaking, silicidation is a complex multistep process involving di?usion and phase transformation. Depending on the ratio of nickel to silicon, di?erent phases can be

formed (e.g., Ni3Si, Ni31Si12, Ni2Si, N3Si2, NiSi, NiSi2), with di?erent workfunctions, as is discussed below. In terms of electrical properties, FUSI gates show a metallic behavior (due to complete silicidation) with no signature of polySi depletion for both high-j and SiO2 gate dielectrics (Figure 15). Accumulation and inversion capacitances are equal, and this is true for both n-FET and p-FET devices. Some slight increase of the capacitance in accumulation is also observed, as expected [145] when polySi gates are replaced with a metal gate. The gain of Tinv due to the FUSI process is approximately 0.3– 0.5 nm, especially over the polySi/high-j devices without polySi pre-doping (Figure 15). The combination of polySi-depletion elimination and the high permittivity of the high-j layers results in very signi?cant (six to seven orders of magnitude) gate leakage current reduction, plotted against Tinv (Figure 16). A high-j layer (with polySi gates) contributes to a gate leakage reduction of approximately 103–105, while FUSI gates o?er additional reduction by a factor of ;100. As discussed in the two previous sections, threshold voltage control (especially for low-Vt high-performance devices) is a challenge for both metal-gate (band-edge metals) and polySi/high-j devices (the so-called p-FET Vt problem). Achieving band-edge workfunctions for CMOS is one of the key issues with FUSI gates as well. Undoped NiSi gates show a mid-gap workfunction, as evidenced, for example, from Vt shift by ;0.5 V from n? Si and p? Si controls (Figure 15). Several techniques have been proposed to adjust the workfunction of FUSI gates toward band edges: 1) pre-doping of polySi gates with common n? and p? dopants before gate silicidation [126, 129–132, 135, 140, 141, 144]; 2) changing the composition of FUSI gates, in particular alloying Ni with other elements (for example, Pt or Ge for p-FET shifts and Al for n-FETs) [130, 131, 133, 137, 140]; 3) using di?erent silicide phases [21, 140, 143, 144];

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106 104 Vf b ) 102 10 0 10 10 10 10 10
2 4 6

Ev PolySi/SiO2 benchmark 106 –107 FUSI/highp + polySi Ei P As Sb

NiSi

Jg (A/cm 2) @ (1 V

B n + polySi 103–105 due to highPolySi/high30 35 40 Ec

Al

Pt

Pt + Al

~ 5 A due to FUSI
8 10

WFs vary as a function of implant dose or alloy concentration

FUSI/high10 15 20 25 T inv (A)

Figure 17
Workfunction control for fully silicided (FUSI) gates by polySi pre-doping with typical n-type and p-type dopants.

Figure 16
Gate leakage current density as a function of inversion thickness for polySi-gated devices with SiO2 and high- dielectrics and fully silicided (FUSI) devices with high- dielectrics. From [131], reproduced with permission; ?2004 IEEE.

Ni–Pt–Si

Ni31Si12

Vf b shift from midgap (mV)

100 0 NiSi 100 200 300 400 500

4) utilizing ultrathin cap materials between the gate dielectric and the FUSI gate, similar to the idea discussed in the polySi/high-j section [140]; 5) bottom interface engineering [140]; and 6) channel pre-doping. With the help of polysilicon pre-doping [e.g., As, Sb, P ion implantation (I/I) for n-FETs and Al, B I/I for p-FETs] of FUSI gates on SiO2-based gate dielectrics, Vt can be adjusted [126] within ;150 meV (for p-FETs) and 300 meV (for n-FETs) from the mid-gap value of the undoped NiSi (Figure 17). The dopant dose should be carefully optimized because some EOT loss and adhesion problems are observed at high ion implant doses. In other words, there is a tradeo? between the value of the Vt shift and the degree of delamination (for n-type dopants) and also EOT loss. Besides, polySi pre-doping becomes less e?cient in the case of FUSI gates on high-j dielectrics because of the so-called Fermi-level pinning problem discussed in detail in Section 2. For FUSI gates this problem can be mitigated by using 1) metal-rich phases of nickel silicides; 2) platinum silicides or platinum alloys; and/or 3) more stable silicate and nitrided silicate materials. It has been demonstrated that di?erent phases of nickel silicides exhibit workfunctions ranging from ;4.3 eV (for NiSi2) to ;4.7 eV (for Ni2Si) [21]. This phase-controlled full silicidation o?ers an extra ‘‘knob’’ to tune the workfunctions of FUSI gates. Another factor in adjusting Vt is to alloy nickel silicides with elements that help to move the workfunction toward band edges. For example, devices with NiPtSi FUSI gates show threshold voltages close to a ‘‘quarter-gap’’ p-FET value, whereas alloying with aluminum shifts the workfunction almost to the n? band edge (Figure 18). The mechanism of this

Quarter gap p+ polySi ~ 5.1 eV

Valence band edge ~ 5.2 eV
(a)

550 500 450 400 350 300 250 200 150 100 50 0

Conduction band edge n + polySi (4.2 eV) <100 mV

Vf b shift (mV)

Quarter gap HfO2

NiSi

Ni(metal1)Si (b)

Figure 18
Workfunction adjustments for fully silicided (FUSI) gates by alloying polySi (a) with Pt and Ni-rich silicides for p-FETs and (b) with Al for n-FETs.

Vt modulation is not fully understood at present. It is believed to be possibly due to segregation of the alloying element at the FUSI/dielectric interface. Device performance improvement is an ultimate goal of device scaling, and innovations in materials and device architecture are enabling it. In terms of performance, long-channel FUSI-gated HfSixOy devices show carrier mobilities close to that of the SiO2 control [131]. This fact combined with reduced Tinv (Figures 15 and 16) results in signi?cant drive current improvements [131]. Figure 19 shows (over)drive current in the linear regime as a function of gate leakage. The upper x-axis also shows an equivalent gate oxide thickness extracted from gate current density assuming SiO2 tunneling behavior. At a given gate leakage, the n-FET performance gain is ;25% for NiSi/HfSixOy and ;15% for NiSi/SiO2. Another way

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3.5 17.0 16.0 ( A) 15.0 14.0 13.0 12.0 11.0 10.0 10
8

Tox (from gate leakage) (A) 3.0 2.5 2.0 1.5 25% Ion gain 15% Ion gain

1.0

gate leakage reduction (at a given Tinv); Vt control for both n-FETs and p-FETs, and negligible charge trapping.

5. Summary
There is no doubt that enormous progress has been achieved in the area of advanced gate stacks over the past several years. Initial demonstrations of high-j devices in the late 1990s did show signi?cant leakage current reduction due to higher permittivity of the stack. However, these early devices were barely usable. They su?ered from signi?cant mobility degradation, threshold voltage instability caused by unacceptable charge trapping, limiting scaling potential below 2 nm (Tinv), reliability concerns, and an unclear integration path. Most of these issues (which seemed fundamental in the early days) have now been solved. High-j/metal-gate devices are much more competitive now for highperformance technologies. They exhibit high mobility at thin Tinv and no signi?cant charge trapping. Controllable and reliable Vt control still remains as a potential issue, but several options have been identi?ed to solve this problem. Interface optimization is an important task for high-performance (high-mobility) devices.

Id(lin) /

Leakage reduction 103 102 10

PolySi/SiO2 model PolySi/SiO2 NiSi/SiO2 NiSi/HfSi xOy 102

10 6 10 4 10 2 10 0 Gate leakage density (A/cm 2)

Figure 19
Normalized constant overdrive (at Vt 0.8 V) current for NiSi/SiO2 and NiSi/HfSiO n-FETs. Performance gain over polySi/SiO2 at a given gate leakage is shown by arrows. (Id(lin): linear drive current.) Reproduced from [131], with permission; ?2004 IEEE.

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to interpret the data shown in Figure 19 is that, for a given drive current (the equivalent of ;1 nm SiO2 gate dielectric), NiSi/HfSixOy shows approximately six orders of magnitude lower gate leakage. As indicated in the previous sections, charge (electron) trapping is a well-known phenomenon and a serious reliability concern in high-j-based devices. It causes Vt instabilities and drive current degradation. FUSI-gated devices exhibit charge-trapping behavior similar to that of the polySi/ high-j stacks, as evaluated by means of the constant-stress voltage technique [113]. Speci?cally, FUSI on HfO2 shows signi?cant Vt instability, whereas charge trapping in both doped and undoped FUSI on HfSixOy is negligible. This important observation was also complemented by charge-pumping measurements. Finally, we comment on scaling issues of FUSI/high-j gates. ‘‘Gate-last’’ FUSI devices are subjected to processing (starting from polysilicon deposition) and a thermal budget similar to that of polySi/high-j stacks. Hence, one could expect similar issues with regrowth and reactions at high temperatures which should be carefully managed. One conventional way to scale down the electrical equivalent thickness of the stack is to combine an optimized thin SiO2-like interface and a reduced high-j layer thickness. Electrical thicknesses in inversion (Tinv) as thin as 1.6 nm have been achieved for NiSi/HfSiO devices [140]. In summary, the FUSI device is an attractive metalgate integration option that o?ers a number of device bene?ts such as sub-2-nm Tinv; performance gain over polySi/SiO2 at a given gate leakage; six to seven orders of

Acknowledgments
The high-j/metal-gate project is truly a collaborative work of many researchers and engineers at several IBM locations: the Thomas J. Watson Research Center in Yorktown Heights, the East Fishkill Semiconductor Research and Development Center, and the Zurich Research Laboratory. This progress review represents results accumulated over several years of very fruitful work of the IBM high-j/metal-gate team, speci?cally N. Bojarczuk, C. Cabral, Jr., A. Callegari, E. Cartier, M. Chudzik, S. A. Cohen, S. L. Cohen, M. Copel, S. Guha, M. Gribelyuk, P. Jamison, R. Jammy, Y. H. Kim, B. P. Linder, V. Paruchuri, M. Steen, and S. Zafar. The authors would also like to thank D. Abraham, R. Amos, J. Arnold, G. Biery, D. Buchanan, R. Carruthers, T. C. Chen, C. D’Emic, D. DiMaria, B. Doris, S. Fang, M. Fischetti, W. Haensch, R. Haight, J. P. Han, M. Ieong, J. Kedzierski, P. Kozlowski, V. Ku, A. Kumar, D. Lacey, D. La Tulipe, K.-L. Lee, Y. Li, B. H. Lee, R. Ludeke, K. Maitra, R. McFeely, D. Medeiros, P. Nguyen, N. V. Nguyen (at NIST), N. Moumen, R. Mo, H. Nayfeh, J. Newbury, H. Okorn-Schmidt, P. Oldiges, Y. Ostrovski, Z. Ren, P. Ronsheim, E. Sikorski, G. Singco, G. Shahidi, J. Stathis, A. Steegen, X. Wang, and Y. Zhang for their help, discussions, and support. Collaboration with researchers from the IBM Zurich Research Laboratory, W. Andreoni, A. Curioni, J. Fompeyrine, R. Germann, J. P. Locquet, and C. Rossel, is also acknowledged.

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March 3, 2006; Internet publication August 6, 2006

Received October 20, 2005; accepted for publication

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Evgeni P. Gusev QUALCOMM MEMS Technologies, 2581 Junction Avenue, San Jose, California 95134. Dr. Gusev received his M.S. (applied physics/molecular physics) and Ph.D. (solid-state physics) degrees from the Moscow Engineering Physics Institute (MEPhI) in 1988 and 1991. After graduation, he worked at MEPhI as a Research Associate for two years. In 1993, he joined the Laboratory for Surface Modi?cation at Rutgers University, where he performed research on fundamental aspects of gate dielectrics, ?rst as a Postdoctoral Fellow and then as a Research Assistant Professor. In 1997, he held an appointment as Visiting Professor at the Research Center for Nanodevices and Systems, Hiroshima University, Japan. Dr. Gusev subsequently joined IBM, where he was responsible for several projects related to gate stack processing, characterization, and device integration at both the Semiconductor Research and Development Center (SRDC) in East Fishkill, New York, and the Thomas J. Watson Research Center in Yorktown Heights, New York. In 2005 he joined the QUALCOMM Technology Development Center in San Jose as the Director of the Department of Materials and Device Research and Development. Dr. Gusev has also contributed to the technical R&D community, with nine edited books, more than 140 publications, and 20 issued and ?led patents. He is a member of several professional committees, panels, and societies.

Vijay Narayanan IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (vijayna@us.ibm.com). Dr. Narayanan is a Research Sta? Member in the Silicon Technology Department at the IBM Thomas J. Watson Research Center. He received his B.Tech. degree in metallurgical engineering from the Indian Institute of Technology, Madras (1995), and his M.S. (1996) and Ph.D. (1999) degrees in materials science and engineering from Carnegie Mellon University, where his dissertation concentrated on understanding the origins of line and planar defects during the epitaxial growth of gallium phosphide on di?erent orientations of Si. In 1999, Dr. Narayanan joined the Department of Chemical and Materials Engineering at Arizona State University as a postdoctoral research associate, with a focus on the initial stages of nucleation and growth of III–V nitrides on sapphire and Si substrates grown by MOCVD. Dr. Narayanan joined IBM in 2001. His current research concerns advanced gate stack technologies including, high-j–metal gate devices for the 45-nm-technology node and beyond. He is an author or co-author of more than 30 peerreviewed journal and conference papers, and he holds six U.S. patents.

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Martin M. Frank IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (mmfrank@us.ibm.com). Dr. Frank is a Research Sta? Member in the Silicon Technology Department at the Thomas J. Watson Research Center. He received a Diplom degree in physics from Ruhr-Universitat Bochum, Germany, in 1996. He then ¨ performed graduate research on oxide-supported metal nanoparticles at Fritz-Haber-Institut der Max-Planck-Gesellschaft in Berlin, Germany, as a scholar of the German National Merit Foundation, and received a Ph.D. degree in physics from Humboldt-Universitat zu Berlin in 2000. During a subsequent ¨ postdoctoral appointment at Rutgers University, in collaboration with Agere Systems at Lucent Technologies’ Bell Laboratories, he studied dielectric and semiconductor growth on silicon and compound semiconductor surfaces, and metal electrode deposition onto self-assembled monolayers. Dr. Frank joined IBM in 2003. His current research concentrates on high-j gate stacks on silicon and on high-carrier-mobility materials. During an assignment to the Interuniversity MicroElectronics Center (IMEC) in Leuven, Belgium, he also commenced studies of photoresist chemistry. Dr. Frank is an author or coauthor of more than 40 papers and one patent. In 2000, he received the Otto Hahn Medal for outstanding scienti?c achievements.

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