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GL850G Datasheet


Genesys Logic, Inc.

GL850G
USB 2.0 Hub Controller Datasheet

Revision 1.16 Mar. 15, 2010

GL850G Datasheet

Copyright
Copyright ? 2010 Genesys Logic, Inc. All rights reserved. No part of the materials shall be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc.

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Genesys Logic, Inc. owns and retains of its right, title and interest in and to all materials provided herein. Genesys Logic, Inc. reserves all rights, including, but not limited to, all patent rights, trademarks, copyrights and any other propriety rights. No license is granted hereunder.

Disclaimer
All Materials are provided “as is”. Genesys Logic, Inc. makes no warranties, express, implied or otherwise, regarding their accuracy, merchantability, fitness for any particular purpose, and non-infringement of intellectual property. In no event shall Genesys Logic, Inc. be liable for any damages, including, without limitation, any direct, indirect, consequential, or incidental damages. The materials may contain errors or omissions. Genesys Logic, Inc. may make changes to the materials or to the products described herein at anytime without notice.

Genesys Logic, Inc.
12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel : (886-2) 8913-1888 Fax : (886-2) 6629-6168 http ://www.genesyslogic.com

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Page 2

GL850G Datasheet

Revision History
Revision 1.00 1.01 1.02 1.03 1.04 Date 05/10/2006 First formal release 08/30/2006 Update DC supply current, table6.6, P.23 11/03/2006 Modify 93C46 configuration, table 5.1, P.19 01/17/2007 Modify table 6.1-maximum ratings, P.21 08/08/2007 Modify table 6.6-DC Supply Current, P.23 Add SSOP 28 package assignment ,Ch3, P.11~14 Add –low/high-enabled power switches, Ch5.2.7, P.23 03/10/2008 Add built-in 5V to 3.3V power regulator, Ch5.2.5, P.21 Modify power on reset description, Ch5.2.1, P.18 Add description of port configuration, Ch5.2.8 and Ch5.2.9, P.23 Add QFN 28pin: pinout, p.12 pin List, p.13 01/07/2008 pin descriptions, p.14 ~15 package dimension, p.30 ordering information, p.32 02/19/2009 Modify SSOP 28 pin, QFN 28 pinout, pin list, pin description, p.11~15 03/18/2009 Modify electrical characteristics, Ch6, p.26~27 04//15/2009 Modify table 6.6-DC supply current, p.27 04/27/2009 Modify part number of QFN 28, table8.1- ordering information, p.31 Modify pin name SEL48/SEL27 pinout / pin list/ description, p.10, p.13, p.15 04/29/2009 Modify Fosc 12 MHz ± 0.05% to 12 MHz ± 50ppm, maximum ratings, table-6.1, p.26 Modify Fosc 12 MHz ± 50ppm to 12 MHz ± 0.05%, maximum ratings, table 06/12/2009 6.1, p.26 Modify power on reset diagram, figure 5.3, p.21 08/12/2009 Modify Ch6.4 power consumption, table 6.6 - DC supply current , p.28 Update table 3.4 - pin description, p.16 Update table 6.2 - operating ranges, p.29 09/02/2009 Update table 6.3 - power dissipation, p.29 Update Ch8 order information, p.35 Update Ch2 features, p.9 Add note to table 3.2, p.14 09/22/2009 Add note to table 3.4, p.15 Add note to table 5.2, p.27 Update table 6.3 - power dissipation, p.30 Modify description of reference clock configuration, Ch5.2.10, p.28 03/15/2010 Modify Ch7 Package Dimension, p.32-33 Modify Ch8 Ordering Information, p.35 Description

1.05

1.06

1.07 1.08 1.09 1.10 1.11

1.12 1.13

1.14

1.15

1.16

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Page 3

GL850G Datasheet

Table of Contents
CHAPTER 1 GENERAL DESCRIPTION ........................................................................ 8 CHAPTER 2 FEATURES.................................................................................................... 9 CHAPTER 3 PIN ASSIGNMENT .................................................................................... 11 3.1 Pinouts ......................................................................................................................... 11 3.2 Pin List......................................................................................................................... 14 3.3 Pin Descriptions .......................................................................................................... 15 CHAPTER 4 BLOCK DIAGRAM ................................................................................... 18 CHAPTER 5 FUNCTION DESCRIPTION..................................................................... 19 5.1 General Description.................................................................................................... 19 5.1.1 USPORT Transceiver......................................................................................... 19 5.1.2 PLL (Phase Lock Loop) ..................................................................................... 19 5.1.3 FRTIMER ........................................................................................................... 19 5.1.4 ?C ......................................................................................................................... 19 5.1.5 UTMI (USB 2.0 Transceiver Microcell Interface)........................................... 19 5.1.6 USPORT Logic ................................................................................................... 19 5.1.7 SIE (Serial Interface Engine)............................................................................. 19 5.1.8 Control/Status Register ...................................................................................... 20 5.1.9 REPEATER ........................................................................................................ 20 5.1.10 TT (Transaction Translator) ........................................................................... 20 5.1.11 REPEATER/TT Routing Logic....................................................................... 20 5.1.12 DSPORT Logic ................................................................................................. 22 5.1.13 DSPORT Transceiver....................................................................................... 22 5.2 Configuration and I/O Settings ................................................................................. 23 5.2.1 RESET Setting .................................................................................................... 23 5.2.2 PGANG/SUSPND Setting .................................................................................. 24 5.2.3 SELF/BUS Power Setting .................................................................................. 25 5.2.4 LED Connections ................................................................................................ 25 5.2.5 Built-in Power Regulator ................................................................................... 25 5.2.6 EEPROM Setting................................................................................................ 26 5.2.7 Power Switch Enable Polarity (Not Available for QFN/SSOP 28 Package) . 27 5.2.8 Port Number Configuration (Not Available for QFN/SSOP 28 Package) .... 27 5.2.9 Non-removable Port Configuration (Not Available for QFN/SSOP 28 Package)........................................................................................................................ 28 5.2.10 Reference Clock Configuration (Not Available for QFN/SSOP 28 Package)28
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GL850G Datasheet CHAPTER 6 ELECTRICAL CHARACTERISTICS..................................................... 29 6.1 Maximum Ratings ...................................................................................................... 29 6.2 Operating Ranges ....................................................................................................... 29 6.3 DC Characteristics ..................................................................................................... 30 6.4 Power Consumption ................................................................................................... 31 CHAPTER 7 PACKAGE DIMENSION .......................................................................... 32 CHAPTER 8 ORDERING INFORMATION .................................................................. 35

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GL850G Datasheet

List of Figures
Figure 3.1 - GL850G LQFP 48 Pin Pinout Diagram .......................................................... 11 Figure 3.2 - GL850G SSOP 28 Pin Pinout Diagram ........................................................... 12 Figure 3.3 - GL850G QFN 28 Pin Pinout Diagram............................................................. 13 Figure 4.1 - GL850G Block Diagram (Single TT) ............................................................... 18 Figure 5.1 - Operating in USB 1.1 Scheme .......................................................................... 21 Figure 5.2 - Operating in USB 2.0 Scheme .......................................................................... 22 Figure 5.3 - Power on Reset Diagram................................................................................... 23 Figure 5.4 - Power on Sequence of GL850G........................................................................ 23 Figure 5.5 - Timing of PGANG/SUSPEND Strapping........................................................ 24 Figure 5.6 - Individual/GANG Mode Setting....................................................................... 24 Figure 5.7 - SELF/BUS Power Setting ................................................................................. 25 Figure 5.8 - LED Connection ................................................................................................ 25 Figure 5.9 - Schematics between GL850G and 93C46 ........................................................ 27 Figure 7.1 - GL850G 48 Pin LQFP Package........................................................................ 32 Figure 7.2 - GL850G 28 Pin SSOP Package ........................................................................ 33 Figure 7.3 - GL850G 28 Pin QFN Package.......................................................................... 34

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Page 6

GL850G Datasheet

List of Tables
Table 3.1 - GL850G LQFP 48 Pin List................................................................................. 14 Table 3.2 - GL850G SSOP 28 Pin List ................................................................................. 14 Table 3.3 - GL850G QFN 28 Pin List ................................................................................... 14 Table 3.4 - Pin Descriptions................................................................................................... 15 Table 5.1 - 93C46 Configuration........................................................................................... 26 Table 5.2 - Configuration by Power Switch Type ............................................................... 27 Table 5.3 - Port Number Configuration............................................................................... 27 Table 5.4 - Ref. Clock Configuration.................................................................................... 28 Table 6.1 - Maximum Ratings............................................................................................... 29 Table 6.2 - Operating Ranges................................................................................................ 29 Table 6.3 - DC Characteristics except USB Signals ............................................................ 30 Table 6.4 - DC Characteristics of USB Signals under FS/LS Mode .................................. 30 Table 6.5 - DC Characteristics of USB Signals under HS Mode ....................................... 30 Table 6.6 - DC Supply Current ............................................................................................. 31 Table 8.1 - Ordering Information ......................................................................................... 35

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GL850G Datasheet

CHAPTER 1 GENERAL DESCRIPTION
GL850G is Genesys Logic’s advanced version hub solutions which fully comply with Universal Serial Bus Specification Revision 2.0. GL850 inherits Genesys Logic’s cutting edge technology on cost and power efficient serial interface design. GL850G has proven compatibility, lower power consumption figure and better cost structure above all USB2.0 hub solutions worldwide. GL850G provides multiple advantages to simplify board level design that help achieve lowest BOM (Bill of Material) for system integrator. GL850G integrated both 5V to 3.3V and 3.3V to 1.8V voltage drop regulator into single chip, therefore no external LDO required. Also, GL850G’s power enable pin supports both high-enable and low-enable power switch that provides better flexibility on component selection. GL850G embeds an 8-bit RISC processor to manipulate the control/status registers and respond to the requests from USB host. Firmware of GL850G will control its general purpose I/O (GPIO) to access the external EEPROM and then respond to the host the customized PID and VID configured in the external EEPROM. Default settings in the internal mask ROM is responded to the host without having external EEPROM. GL850G is designed for customers with much flexibility. The more complicated settings such as PID, VID, and number of downstream ports settings are easily achieved by programming the external EEPROM (Ref. to Chapter 5). Each downstream port of GL850G supports two-color (green/amber) status LEDs to indicate normal/abnormal status. GL850G also support both Individual and Gang modes (4 ports as a group) for power management. The GL850G is a full function solution which supports both Individual/Gang power management modes and the two-color (green/amber) status LEDs. Please refer the table in the end of this chapter for more detail. Number of downstream ports setting can be configured by IO setting in absence of EEPROM. (Ref. to Chapter 5) To fully meet the cost/performance requirement, GL850G is a single TT hub solution for the cost requirement. Genesys Logic also provides GL852G for multiple TT hub solution to target on systems which require higher performance for full/low-speed devices, like docking station, embedded system … etc.. Please refer to GL852G datasheet for more detailed information. *TT (transaction translator) is the main traffic control engine in an USB 2.0 hub to handle the unbalanced traffic speed between the upstream port and the downstream ports.

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GL850G Datasheet

CHAPTER 2 FEATURES ?
Compliant to USB Specification Revision 2.0 ? Support 4/3/2 downstream ports by I/O pin configuration ? Upstream port supports both high-speed (HS) and full-speed (FS) traffic ? Downstream ports support HS, FS, and low-speed (LS) traffic ? 1 control pipe (endpoint 0, 64-byte data payload) and 1 interrupt pipe (endpoint 1, 1-byte data payload) ? Backward compatible to USB specification Revision 1.1 On-chip 8-bit micro-processor ? RISC-like architecture ? USB optimized instruction set ? Performance: 6 MIPS @ 12MHz ? With 64-byte RAM and 2K mask ROM ? Support customized PID, VID by reading external EEPROM ? Support downstream port configuration by reading external EEPROM Single Transaction Translator (STT) ? Single TT shares the same TT control logics for all downstream port devices. This is the most cost effective solution for TT. Multiple TT provides individual TT control logics for each downstream port. This is a performance better choice for USB 2.0 hub. Please refer to GL852G datasheet for more detailed information. Integrate USB 2.0 transceiver Built-in upstream 1.5K pull-up and downstream 15K pull-down

?

?

? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?

Embed serial resister for USB signals Conform to bus power requirements Automatic switching between self-powered and bus-powered modes Support compound-device (non-removable in downstream ports) by I/O pin configuration Configurable non-removable device support Built-in PLL supports external 12 MHz crystal / Oscillator clock input Built-in 5V to 3.3V regulator Low power consumption Improve output drivers with slew-rate control for EMI reduction Internal power-fail detection for ESD recovery Each downstream port supports two-color status indicator, with automatic and manual modes compliant to USB specification Revision 2.0 (Not available for SSOP 28 package) Support both individual and gang modes of power management and over-current detection for downstream ports (Individual mode is not supported by SSOP 28 package) Power enable pin supports both low/high-enabled power switches. (Power switch is not supported by GL850G-22 SSOP28 package) Optional 27/48 MHz Oscillator clock input (Not available for QFN 28 / SSOP 28 package) Available in 48 pin LQFP and 28 pin SSOP package (Full Function only available in 48 pin) Number of Downstream port can be configured by GPIO without external EEPROM

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Page 9

GL850G Datasheet

?

Applications: ? Stand-alone USB hub ? PC motherboard USB hub, Docking of notebook ? Gaming console ? LCD monitor hub ? Any compound device to support USB hub function

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GL850G Datasheet

CHAPTER 3 PIN ASSIGNMENT
3.1 Pinouts

PSELF DVDD PGANG OVCUR2# PWREN2# OVCUR1# PWREN1# SEL27 PGREEN1
PAMBER1

37 38 39 40 41 42 43 44 45 46 47 48

24 23 22 21 20 19

PAMBER4 PGREEN4 DP4 DM4 AGND AVDD DP3 DM3 AVDD X2 X1 AGND

GL850G
LQFP - 48

18 17 16 15 14 13

V5 V33

Figure 3.1 - GL850G LQFP 48 Pin Pinout Diagram

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Page 11

GL850G Datasheet

Figure 3.2 - GL850G SSOP 28 Pin Pinout Diagram

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Page 12

GL850G Datasheet

OVCUR3#

OVCUR4#

TEST/SCL

RESET#

DVDD

18

17

16 6 DM2

21

20

19

5

1

2

3

4

Figure 3.3 - GL850G QFN 28 Pin Pinout Diagram

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AVDD

DM0

DP0

DM1

DP1

DP2

7

15

DM4

DP4

Page 13

GL850G Datasheet 3.2 Pin List
Table 3.1 - GL850G LQFP 48 Pin List
Pin# 1 2 3 4 5 6 7 8 9 Pin Name AVDD AGND DM0 DP0 DM1 DP1 AVDD AGND DM2 Type Pin# P P B B B B P P B B B P Pin Name Type Pin# P I O P B B P P B B O O Pin Name Type Pin# I Pin Name Type I_5V P B I_5V O I_5V O I O O P P 13 AGND 14 X1 15 X2 16 AVDD 17 DM3 18 DP3 19 AVDD 20 AGND 21 DM4 22 DP4 23 PGREEN4 24 PAMBER4 25 SEL48 26 RESET# 27 TEST 28 OVCUR4# 29 PWREN4# 30 OVCUR3# 31 PWREN3# 32 PGREEN3 33 PAMBER3 34 DVDD 35 PGREEN2 36 PAMBER2 37 PSELF

I_5V 38 DVDD I 39 PGANG

I_5V 40 OVCUR2# O 41 PWREN2#

I_5V 42 OVCUR1# O O O P O O 43 PWREN1# 44 SEL27 45 PGREEN1 46 PAMBER1 47 V5 48 V33

10 DP2 11 RREF 12 AVDD

Table 3.2 - GL850G SSOP 28 Pin List
Pin# 1 2 3 4 5 6 7 Pin Name AVDD DM2 DP2 RREF AVDD X1 X2 Type Pin# P B B B P I O 8 9 Pin Name DM3 DP3 Type Pin# B B P B B Pin Name Type Pin# P P Pin Name Type O P P B B B B 15 GND 16 DVDD 17 PSELF 18 PGANG 19 OVCUR2# 22 PWREN1# 23 V5

10 AVDD 11 DM4 12 DP4 13 RESET# 14 TEST/SCL

I_5V 24 V33 B 25 DM0 27 DM1

I_5V 26 DP0 O

I_5V 20 PWREN2#* I/B

21 OVCUR1#* I_5V 28 DP1

* Power switch is not supported in GL850G-22 version.

Table 3.3 - GL850G QFN 28 Pin List
Pin# 1 2 3 4 5 6 7 Pin Name DM0 DP0 DM1 DP1 AVDD DM2 DP2 Type Pin# B B B B P B B 8 9 Pin Name RREF AVDD Type Pin# B P I I B B P Pin Name Type Pin# B B Pin Name Type I_5V B I_5V I_5V B P P 15 DM4 16 DP4 17 RESET# 18 TEST/SCL 19 OVCUR4# 20 OVCUR3# 21 DVDD 22 PSELF 23 PGANG

10 X1 11 X2 12 DM3 13 DP3 14 AVDD

I_5V 24 OVCUR2# I/B 25 OVCUR1#

I_5V 26 SDA I_5V 27 V5 P 28 V33

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Page 14

GL850G Datasheet 3.3 Pin Descriptions
Table 3.4 - Pin Descriptions
USB Interface GL850G Pin Name DM0,DP0 DM1,DP1 DM2,DP2 DM3,DP3 DM4,DP4 RREF LQFP 48 Pin 3,4 5,6 9,10 17,18 21,22 11 SSOP 28 Pin 25,26 27,28 2,3 8,9 11,12 4 QFN 28 Pin 1,2 3,4 6,7 12,13 15,16 8 I/O Type B B B B B B Description USB signals for USPORT USB signals for DSPORT1 USB signals for DSPORT2 USB signals for DSPORT3 USB signals for DSPORT4 A 680 resister must be connected between RREF and analog ground (AGND)

Note: USB signals must be carefully handled in PCB routing. For detailed information, please refer to GL850G Design Guideline. Hub Interface GL850G Pin Name LQFP 48 Pin 42,40, 30,28 SSOP 28 Pin 21,19 QFN 28 Pin 25,24, 20,19 I/O Type Description

OVCUR1~4#

PWREN1~4#

43,41, 31,29

22,20

--

PGREEN1~4

45,35, 32,23

--

--

PAMBER1~4

46,36, 33,24 37

--

--

PSELF

17

22

PGANG

39

18

23

Active low. Over current indicator for DSPORT1~4 I_5V OVCUR1# is the only over current flag for GANG (pu) mode Active low. Power enable output for DSPORT1~4 PWREN1# is the only power-enable output for GANG O mode * Power switch is not supported in GL850G-22 version. Green LED indicator for DSPORT1~4 1,3,4:O *GREEN[1~2] are also used to access the external 2:B EEPROM (pd) For detailed information, please refer to Chapter 5 Amber LED indicator for DSPORT1~4 O *Amber[1~2] are also used to access the external (pd) EEPROM For detailed information, please refer to Chapter 5 0: GL850G is bus-powered I_5V 1: GL850G is self-powered This pin is default put in input mode after power-on reset. Individual/gang mode is strapped during this period. After the strapping period, this pin will be set to output mode, and then output high for normal mode. B When GL850G is suspended, this pin will output low. *For detailed explanation, please see Chapter 5 Gang input:1, output: 0@normal, 1@suspend Individual input:0, output: 1@normal, 0@suspend

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Page 15

GL850G Datasheet

Clock and Reset Interface GL850G Pin Name X1 X2 RESET# LQFP 48 Pin 14 15 26 SSOP 28 Pin 6 7 13 QFN 28 Pin 10 11 17 I/O Type I O Description 12MHz crystal clock input, or 12/27/48MHz clock input 12MHz crystal clock output

SEL48/SEL27 25,44

--

--

Active low. External reset input, default pull high 10K I_5V When RESET# = low, whole chip is reset to the initial state SEL48/SEL27: 0 1: 48MHz OSC-in I 1 0: 27MHz OSC-in 1 1: 12MHz X’tal/OSC-in

System Interface GL850G Pin Name LQFP 48 Pin 27 -SSOP 28 Pin 14 -QFN 28 Pin 18 26 I/O Type I (pd) B B Description TEST: 0: Normal operation. (Internal pull down) 1: Chip will be put in test mode. I2C:clock output pin (SSOP 28pin/QFN 28pin only) I2C: data pin

TEST/SCL SDA

Power / Ground GL850G Pin Name AVDD AGND DVDD GND V5 LQFP 48 Pin
1,7,12, 16,19 2,8,13, 20 34,38 -47

SSOP 28 Pin
1,5,10 -16 15 23

QFN 28 Pin
5,9,14 -21 -27

I/O Type P P P

Description 3.3V analog power input for analog circuits Analog ground input for analog circuits 3.3V digital power input for digital circuitsLL

P

V33

48

24

28

P

5V Power input. It need be NC if using external regulator 5V-to-3.3V regulator Vout (LQFP48) 5V-to-3.3V regulator Vout & 3.3 input (SSOP28/QFN28) It can be NC or connect to 3.3V power if using external regulator (LQFP48 only)

Note: Analog circuits are quite sensitive to power and ground noise. PCB layout must take care the power routing and the ground plane. For detailed information, please refer to GL850G Design Guideline.

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Page 16

GL850G Datasheet

Notation: Type O I I_5V B B/I B/O P A SO pu pd odpu

Output Input 5V tolerant input Bi-directional Bi-directional, default input Bi-directional, default output Power / Ground Analog Automatic output low when suspend Internal pull up Internal pull down Open drain with internal pull up

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Page 17

GL850G Datasheet

CHAPTER 4 BLOCK DIAGRAM
12/27/48 MHz

D+

D-

USPORT FRTIMER Transceiver

PLL x40, x10

RA M

ROM CPU

GPIO

USPORT UTMI Logic SIE

Control/Status

Register

REPEATER

TT (Transaction Translator)

REPEATER / TT Routing Logic

DSPORT1 Logic

DSPORT2 Logic

DSPORT3 Logic

DSPORT4 Logic

DSPORT
Transceiver

DSPORT
Transceiver

DSPORT
Transceiver

DSPORT
Transceiver

D+

D- LED/ OVCUR/ PWRENB

D+

D- LED/ OVCUR/ PWRENB

D+

D- LED/ OVCUR/ PWRENB

D+

D- LED/ OVCUR/ PWRENB

Figure 4.1 - GL850G Block Diagram (Single TT)

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Page 18

GL850G Datasheet

CHAPTER 5 FUNCTION DESCRIPTION
5.1 General Description 5.1.1 USPORT Transceiver
USPORT (upstream port) transceiver is the analog circuit that supports both full-speed and high-speed electrical characteristics defined in chapter 7 of USB specification Revision 2.0. USPORT transceiver will operate in full-speed electrical signaling when GL850G is plugged into a 1.1 host/hub. USPORT transceiver will operate in high-speed electrical signaling when GL850G is plugged into a 2.0 host/hub.

5.1.2 PLL (Phase Lock Loop)
GL850G contains a 40x PLL. PLL generates the clock sources for the whole chip. The generated clocks are proven quite accurate that help in generating high speed signal without jitter.

5.1.3 FRTIMER
This module implements hub (micro) frame timer. The (micro) frame timer is derived from the hub’s local clock and is synchronized to the host (micro)frame period by the host generated Start of (micro)frame (SOF). FRTIMER keeps tracking the host’s SOF such that GL850G is always safely synchronized to the host. The functionality of FRTIMER is described in section 11.2 of USB Specification Revision 2.0.

5.1.4 ?C
?C is the micro-processor unit of GL850G. It is an 8-bit RISC processor with 2K ROM and 64 bytes RAM. It operates at 6MIPS of 12Mhz clock to decode the USB command issued from host and then prepares the data to respond to the host. In addition, ?C can handle GPIO (general purpose I/O) settings and reading content of EEPROM to support high flexibility for customers of different configurations of hub. These configurations include self/bus power mode setting, individual/gang mode setting, downstream port number setting, device removable/non-removable setting, and PID/VID setting.

5.1.5 UTMI (USB 2.0 Transceiver Microcell Interface)
UTMI handles the low level USB protocol and signaling. It’s designed based on the Intel’s UTMI specification 1.01. The major functions of UTMI logic are to handle the data and clock recovery, NRZI encoding/decoding, Bit stuffing /de-stuffing, supporting USB 2.0 test modes, and serial/parallel conversion.

5.1.6 USPORT Logic
USPORT implements the upstream port logic defined in section 11.6 of USB specification Revision 2.0. It mainly manipulates traffics in the upstream direction. The main functions include the state machines of Receiver and Transmitter, interfaces between UTMI and SIE, and traffic control to/from the REPEATER and TT.

5.1.7 SIE (Serial Interface Engine)
SIE handles the USB protocol defined in chapter 8 of USB specification Revision 2.0. It co-works with Μc to play the role of the hub kernel. The main functions of SIE include the state machine of USB protocol flow, CRC check, PID error check, and timeout check. Unlike USB 1.1, bit stuffing/de-stuffing is implemented in UTMI, not in SIE.

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Page 19

GL850G Datasheet 5.1.8 Control/Status Register
Control/Status register is the interface register between hardware and firmware. This register contains the information necessary to control endpoint0 and endpoint1 pipelines. Through the firmware based architecture, GL850G possesses higher flexibility to control the USB protocol easily and correctly.

5.1.9 REPEATER
Repeater logic implements the control logic defined in section 11.4 and section 11.7 of USB specification Revision 2.0. REPEATER controls the traffic flow when upstream port and downstream port are signaling in the same speed. In addition, REPEATER will generate internal resume signal whenever a wakeup event is issued under the situation that hub is globally suspended.

5.1.10 TT (Transaction Translator)
TT implements the control logic defined in section 11.14 ~ 11.22 of USB specification Revision 2.0. TT basically handles the unbalanced traffic speed between the USPORT (operating in HS) and DSPORTS (operating in FS/LS) of hub. GL850G adopts the single TT architecture to provide the most cost effective solution. Single TT shares the same buffer control module for each downstream port. GL852G adopts multiple TT architecture to provide the most performance effective solution. Multiple TT provides control logics for each downstream port respectively. Please refer to GL852G datasheet for more detailed information.

5.1.11 REPEATER/TT Routing Logic
REPEATER and TT are the major traffic control machines in the USB 2.0 hub. Under situation that USPORT and DSPORT are signaling in the same speed, REPEATER/TT routing logic switches the traffic channel to the REPEATER. Under situation that USPORT is in the high speed signaling and DSPORT is in the full/low speed signaling, REPEATER/TT routing logic switches the traffic channel to the TT.

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Page 20

GL850G Datasheet
5.1.11.1 Connected to USB 1.1 Host/Hub
If an USB 2.0 hub is connected to the downstream port of an USB 1.1 host/hub, it will operate in USB 1.1 mode. For an USB 1.1 hub, both upstream direction traffic and downstream direction traffic are passing through REPEATER. That is, the REPEATER/TT routing logic will route the traffic channel to the REPEATER.

Figure 5.1 - Operating in USB 1.1 Scheme 5.1.11.2 Connected to USB 2.0 Host/Hub
If an USB 2.0 hub is connected to an USB 2.0 host/hub, it will operate in USB 2.0 mode. The upstream port signaling is in high speed with bandwidth of 480 Mbps under this environment. The traffic channel will then be routed to the REPEATER when the device connected to the downstream port is signaling also in high speed. On the other hand, the traffic channel will then be routed to TT when the device connected to the downstream port is signaling in full/low speed.

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Page 21

GL850G Datasheet

Figure 5.2 - Operating in USB 2.0 Scheme

5.1.12 DSPORT Logic
DSPORT (downstream port) logic implements the control logic defined in section 11.5 of USB specification Revision 2.0. It mainly manipulates the state machine, the connection/disconnection detection, over current detection and power enable control, and the status LED control of the downstream port. Besides, it also output the control signals to the DSPORT transceiver.

5.1.13 DSPORT Transceiver
DSPORT transceiver is the analog circuit that supports high-speed, full-speed, and low-speed electrical characteristics defined in chapter 7 of USB specification Revision 2.0. In addition, each DSPORT transceiver accurately controls its own squelch level to detect the detachment and attachment of devices.

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Page 22

GL850G Datasheet 5.2 Configuration and I/O Settings 5.2.1 RESET Setting
GL850G’s power on reset can either be triggered by external reset or internal power good reset circuit. The external reset pin, RESETJ, is connected to upstream port Vbus (5V) to sense the USB plug / unplug or 5V voltage drop. The reset trigger voltage can be set by adjusting the value of resistor R1 and R2 (Suggested value refers to schematics) GL850G’s internal reset is designed to monitor silicon’s internal core power (3.3V) and initiate reset when unstable power event occurs. The power on sequence will start after the power good voltage has been met, and the reset will be released after approximately 2.7 uS after power good.

GL850G internally contains a power on reset circuit as depicted in the picture above

Figure 5.3 - Power on Reset Diagram

DVDD Power good voltage, 2.5~2.8V

Internal reset

External reset

To fully control the reset process of GL850G, we suggest the reset time applied in the external reset circuit should longer than that of the internal reset circuit.

Figure 5.4 - Power on Sequence of GL850G
?2010 Genesys Logic, Inc. - All rights reserved. Page 23

μ ≒
2.7

s

GL850G Datasheet 5.2.2 PGANG/SUSPND Setting
To save pin count, GL850G uses the same pin to decide individual/gang mode as well as to output the suspend flag. The individual/gang mode is decided within 20us after power on reset. Then, about 50ms later, this pin is changed to output mode. GL850G outputs the suspend flag once it is globally suspended. For individual mode, a pull low resister greater than 100K should be placed. For gang mode, a pull high resister greater than 100K should be placed. In figure 5.5, we also depict the suspend LED indicator schematics. It should be noticed that the polarity of LED must be followed, otherwise the suspend current will be over spec limitation (2.5mA).

RESET# 50 ms GANG_CTL Input mode, strapping to decide individual or gang mode Output mode, Indicating GL850G Is In normal mode or suspend mode

Figure 5.5 - Timing of PGANG/SUSPEND Strapping

Figure 5.6 - Individual/GANG Mode Setting

?2010 Genesys Logic, Inc. - All rights reserved.

Page 24

GL850G Datasheet 5.2.3 SELF/BUS Power Setting
GL850G can operate under bus power and conform to the power consumption limitation completely (suspend current < 2.5 mA, normal operation current < 100 mA). By setting PSELF, GL850G can be configured as a bus-power or a self-power hub.

1: Power Self PSELF 0: Power Bus Inside GL850G On PCB

Figure 5.7 - SELF/BUS Power Setting

5.2.4 LED Connections
GL850G controls the LED lighting according to the flow defined in section 11.5.3 of Universal Serial Bus Specification Revision2.0. Both manual mode and Automatic mode are supported in GL850G. When GL850G is globally suspended, GL850G will turn off the LED to save power.

AMBER/GREEN LED

DGND Inside GL850G On PCB

Figure 5.8 - LED Connection

5.2.5 Built-in Power Regulator
The USB data lines are required by the USB specification to have a maximum output voltage between 2.8V and 3.6V. Since the power provided by the USB cable is specified to be between 4.4V and 5.0V, an on-chip regulator is used to drop the voltage to the appropriate level for sourcing the USB transceiver and external pull-up resistor. An output pin driven by the regulator is provided to source the 1.5-k external resistor. Features: 5V to 3.3V PMOS type linear regulator. 200mA output driving capability 28uA maximum quiescent current.

?2010 Genesys Logic, Inc. - All rights reserved.

Page 25

GL850G Datasheet 5.2.6 EEPROM Setting
GL850G replies to host commands by the default settings in the internal ROM. GL850G also offers the ability to reply to the host according to the settings in the external EEPROM (93C46). The following table shows the configuration of 93C46.

Table 5.1 - 93C46 Configuration
Unit: Byte 00 00h 10h 20h 30h 40h 50h 60h 70h
SERIAL NUMBER LENGTH PRODUCT LENGTH

01

02

03

04

05

06

07

08

09
FF

0A
FF

0B 0C 0D 0E 0F
FF FF FF FF FF

VID_L VENDOR LENGTH

PORT DEVICE VID_H PID_L PID_H CHKSUM FF REMOVABLE NUMBER MaxPower

start Vendor string (ASC II code)
end

start Product String(ASC II code)
end

start
end

Serial Number String(ASC II code)

Note: 1. VID_H/VID_L: high/low byte of VID value 2. PID_H/PID_L: high/low byte of PID value 3. CHKSUM: CHKSUM must equal to VID_H + VID_L + PID_H + PID_L + 1,otherwise firmware will ignore the EEPROM settings. 4. PORT_NO: port number, value must be 1~4. 5. MaxPower : Describe the maximum power consumption, range=0Ma~500Ma . Value -> 00H~FAH (unit = 2Ma) 6. DEVICE REMOVALBE: PORT4 PORT3 PORT2 PORT1 REMOVABLE REMOVABLE REMOVABLE REMOVABLE 0: Device attached to this port is removable. 1: Device attached to this port is non-removable.

-

7. VENDOR LENGTH: offset 10h contains the length of the vendor string. Values of vendor string is contained from 11h~3Fh. 8. PRODUCT LENGTH: offset 40h contains the length of product string. Values of product string is contained from 41h~6Fh. 9. SERIAL NUMBER LENGTH: offset 70h contains the value of serial number string. Values of serial number string is contained after offset 71h.

?2010 Genesys Logic, Inc. - All rights reserved.

Page 26

GL850G Datasheet
The schematics between GL850G and 93C46 are depicted in the following figures:

DVDD

EE_CS EE_SK EE_DI EE_DO

CS SK DI DO

VCC NC NC GND

93C46

Figure 5.9 - Schematics between GL850G and 93C46
GL850G firstly verifies the check sum after power on reset. If the check sum is correct, GL850G will take the configuration of 93C46 as part of the descriptor contents. To prevent the content of 93C46 from being over-written, amber LED will be disabled when 93C46 exists.

5.2.7 Power Switch Enable Polarity (Not Available for QFN/SSOP 28 Package)
Both low/high-enabled power switches are supported. It is determined by jumper setting, based on the state of pin AMBER2, as the following table:

Table 5.2 - Configuration by Power Switch Type
AMBER2 0 1 Power Switch Enable Polarity Low-active High-active

Note: When AMBER2=1, the external resistor of PWREN1~4 need pull down.

5.2.8 Port Number Configuration (Not Available for QFN/SSOP 28 Package)
Number of downstream port can be configured as 2/3/4 ports by pin strapping in addition to EEPROM, based on the state of pin AMBER 3, AMBER 4, as the following table:

Table 5.3 - Port Number Configuration
AMBER3 1 0 0 AMBER 4 0 1 0 Port Number 2 3 4

?2010 Genesys Logic, Inc. - All rights reserved.

Page 27

GL850G Datasheet 5.2.9 Non-removable Port Configuration (Not Available for QFN/SSOP 28 Package)
For compound application or embedded system, downstream ports that always connected inside the system can be set as non-removable based on the state of corresponding status LED, pin GREEN 1~4. If the pin is pull high in the initial stage (POR reset), the corresponding port will be set as non-removable.

5.2.10 Reference Clock Configuration (Not Available for QFN/SSOP 28 Package)
GL850G can support optional 27/48MHz clock source, which is selectable through GPIO configurations. For some on-board design that 27/48MHz clock source is available, such as motherboard or Monitor built-in applications, system integrator can leverage this feature to further reduce BOM cost by removing external crystal.

Table 5.4 - Ref. Clock Configuration
SEL48 0 1 1 SEL27 1 0 1 Clock Source 48MHz OSC-in 27MHz OSC-in 12MHz X’tal/OSC-in

?2010 Genesys Logic, Inc. - All rights reserved.

Page 28

GL850G Datasheet

CHAPTER 6 ELECTRICAL CHARACTERISTICS
6.1 Maximum Ratings
Table 6.1 - Maximum Ratings
Symbol V5 VDD VIN VINOD VINUSB TS FOSC 5V Power Supply 3.3V Power Supply Input Voltage for digital I/O pins Open-drain input pins(Ovcur1~4#,Pself,Reset) Input Voltage for USB signal (DP, DM) pins Storage Temperature under bias Frequency Parameter Min. -0.5 -0.5 -0.5 -0.5 -0.5 -55 Max. +6.0 +3.6 +3.6 +5.5 +3.6 +100 12 MHz ± 0.05% Unit V V V V V
o

C

6.2 Operating Ranges
Table 6.2 - Operating Ranges
Symbol V5 VDD VIN VINOD VINUSB TA TJ 5V Power Supply 3.3V Power Supply Input Voltage for digital I/O pins Open-drain input pins(Ovcur1~4#,Pself,Reset) Input Voltage for USB signal (DP, DM) pins Ambient Temperature Absolute maximum junction temperature Thermal Characteristics 48 LQFP Thermal Characteristics 28 SSOP Thermal Characteristics 28 QFN Parameter Min. 4.5 3.15 -0.5 -0.5 0.5 0 0 Typ. 5.0 3.3 83.5 56.3 34.5 Max. 5.5 3.45 3.6 5.0 3.6 70 125 o o o

Unit V V V V V
o o

C C

C/W C/W C/W

?2010 Genesys Logic, Inc. - All rights reserved.

θ

JA

Page 29

GL850G Datasheet 6.3 DC Characteristics
Table 6.3 - DC Characteristics except USB Signals
Symbol PD V33 VIL VIH VTLH VTHL VOL VOH RDN RUP Power Dissipation 5V to 3.3V regulator output with 200mA load LOW level input voltage HIGH level input voltage LOW to HIGH threshold voltage HIGH to LOW threshold voltage LOW level output voltage when IOL=8mA HIGH level output voltage when IOH=8mA Pad internal pull down resister Pad internal pull up resister Parameter Min. 366.5 2.9 2.0 1.4 0.87 2.4 29 80 Typ. 3.3 1.5 0.94 59 108 Max. 426.5 3.52 0.8 1.6 0.99 0.4 135 140 Unit mW V V V V V V V K K

Table 6.4 - DC Characteristics of USB Signals under FS/LS Mode
Symbol VOL VOH VDI VCM VSE CIN ILO ZDRV Parameter DP/DM FS static output LOW(RL of 1.5K to 3.6V ) DP/DM FS static output HIGH (RL of 15K to GND ) Differential input sensitivity Differential common mode range Single-ended receiver threshold Transceiver capacitance Hi-Z state data line leakage Driver output resistance Min. 0 2.8 0.2 0.8 0.2 -10 28 Typ. Max. 0.3 3.6 2.5 20 +10 44 Unit V V V V V Pf ?A

Table 6.5 - DC Characteristics of USB Signals under HS Mode
Symbol VOL CIN ILO ZDRV Parameter DP/DM HS static output LOW(RL of 1.5K to 3.6V ) Transceiver capacitance Hi-Z state data line leakage Driver output resistance for USB 2.0 HS Min. 4 -5 42 Typ. 4.5 0 45 Max. 0.1 5 +5 48 Unit V Pf ?A

?2010 Genesys Logic, Inc. - All rights reserved.

Page 30

GL850G Datasheet

6.4 Power Consumption
Table 6.6 - DC Supply Current
Symbol Active ports ISUSP Condition Host Suspend F* 4 H
*

Typ. Device 753 F H F F H F F H F F H F N/A N/A 85.3 70.3 82.2 83.4 71 80.3 80.9 71.9 78.2 78.3 72.6 75.7 75.6 73.3

Unit uA mA mA mA mA mA mA mA mA mA mA mA mA mA mA

H F 3 H H ICC F 2 H H F 1 H H USPORT Config. *: F: Full-Speed, H: High-Speed F H

?2010 Genesys Logic, Inc. - All rights reserved.

Page 31

GL850G Datasheet

CHAPTER 7 PACKAGE DIMENSION

Internal No.

Green Package + AU Wire

GL850G Version No. AAAAAAAGAA YWWXXXXXXXX
Date Code Lot Code

Figure 7.1 - GL850G 48 Pin LQFP Package

?2010 Genesys Logic, Inc. - All rights reserved.

Page 32

GL850G Datasheet

Figure 7.2 - GL850G 28 Pin SSOP Package
?2010 Genesys Logic, Inc. - All rights reserved. Page 33

GL850G Datasheet

Figure 7.3 - GL850G 28 Pin QFN Package
?2010 Genesys Logic, Inc. - All rights reserved. Page 34

GL850G Datasheet

CHAPTER 8 ORDERING INFORMATION
Table 8.1 - Ordering Information
Part Number GL850G-MNGXX GL850G-HHGXX GL850G-OHG*XX Package LQFP 48 SSOP 28 QFN 28 Green/Wire Material Green Package + AU Wire Green Package + AU Wire Green Package + AU Wire Version XX XX XX Status Available Available Available

*The marking of "OHG" will not be shown on the IC due to QFN 28 package size limitation.

?2010 Genesys Logic, Inc. - All rights reserved.

Page 35


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