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Flash Memory测试简介_图文

Memory 测试原理

Unit 1: Introduction to Flash Technology

Overview of Memory Devices

Course Contents

Two Basic Memory Categories Volatile Memory 易挥发存储器
? Data is lost when power is removed.

Nonvolatile Memory非易挥发存储器 Memory非易挥发存储器
? Data remains even when power is removed.

Volatile Memory RAM – Random Access Memory
? SRAM - Static RAM is commonly used as 640 Kb cache memory in computers. ? DRAM - Dynamic RAM is commonly used for read-write memory in computers. read-

Nonvolatile Memory
ROM – Read Only Memory, ROM, are programmed in a wafer fab and cannot be erased or reprogrammed in the field. PROM – Programmable ROM can be reprogrammed in the field by applying larger voltages with special equipment. EPROM – Erasable PROM can be erased with UV light and reprogrammed with special equipment. EEPROM – Electrically Erasable PROM can be erased with higher voltages and reprogrammed in the field.

Nonvolatile Memory
NVRAM – Nonvolatile RAM (Flash) is (Flash) smaller than PROMs, less expensive, and easier to program and erase. Magnetic – Magnetic disk and tape can be easily programmed and erased by user, but are slower than Flash. Optical – CD ROM can be easily programmed by user but is slower than Flash.

Benefits of Flash Memory Chips
Smaller than EPROMS and EEPROMS Requires only one transistor and a storage capacitor per bit cell. Can be quickly and easily erased and reprogrammed without the need of special equipment. Excellent for use in cell phones, pagers, calculators, portable digital devices, automotive, flight data recorders, and personal computers.

Simple ROM Memory Array
Bit line Word line

Data “0” Cell No gate metal contact

G S D Bit line Word line

Data “1” Cell Gate is connected

G S D

Simple DRAM Memory Array
Sense Amps / Buffers

?Activate Row to read
–If capacitor was charged, no current flows on bit line –If capacitor not charged, current flows on bit line –Buffer on column sense amps

Word line Bit line Bit line Bit line

Capacitor CurrentCurrentsensing line

Capacitor charged, No current, “0”

Capacitor uncharged, Current flow, “1”

Simple EPROM Memory Array
Sense Amps / Buffers

Word line Bit line Bit line Bit line Bit line Bit line Bit line

Floating gate

A second “floating gate” serves as the storage element in an EPROM.

Basic Flash Memory Cell

Source

Gate Floating Gate

Drain

Floating Gate (electrically isolated) is the storage element ? charged = “programmed” ? neutral = “erased”

Flash Cell Structure - Similar to EPROM, except Electrically-erasable ElectricallyPolysilicon (doped)

Dielectric (ONO) Dielectric (oxide) n+ Source p+ Substrate Control Gate Floating Gate

n+ Drain

Flash Cell Operation - Program Mode Channel Hot-Electron Injection HotVG = +9.3V Control Gate Floating Gate E-field
E-field E-field

Electric fields form due to voltages

GND n+ Source

VD = +4.5V Drain n+

p+ Substrate

Flash Cell Operation - Program Mode Channel Hot-electron Injection HotVG = +9.3V Control Gate Floating -Gateee e-e ee e- e- e- e- - ee ee- ep+ Substrate

GND n+ Source

VD = +4.5V Drain n+

Flash Cell Operation - Program Mode IDS Conduction & Floating Gate Charge (Q)
VG = +9.3V Logic state “0” GND Q Control Gate Floating Gate IDS
=0

VD = +4.5V Drain n+

n+ Source

p+ Substrate

Flash Cell Operation - Erase Mode Negative Gate ---F-N Tunneling ---F
VG = -9.3V

ElectricallyElectrically-erasable charge from gate

Logic state “1” Float Q Control Gate e- e- eFloating Gate eeeeeeeVD = Float Drain n+

n+ Source

p+ Substrate

Flash Memory Bit Threshold Voltages

IDS

0

1

2

3

4

5

6

7

VGS

Flash Array Architecture (schematic)

1. Bit cell formation 2. Word lines (gate) 3. GND lines (source) 4. Bit lines (drain)

Core memory (core)

Flash Array Cell Addressing
Selected word line (H)
R o w D e c o d e r

Selected bit line (L)
S o u r c e S w i t c h

Address

GND

Selected cell
Column Decoder

Basic Memory Device Internal Architecture
Memory cell
A4 A0 A1 A2 A3 1 0 0 0 A5 0 1 0 0 A6 0 0 1 0 A7 0 0 0 1

?Memory Cell block: 每个CELL存储 data(1/0) ?Address Decoder Circuitry:地址译码 以(A0~ )来选择不同的memory cell or block 进行读写操作。 ?Input/Output I/O) circuitry:是memory Cell 和外界的输入输出接口, 将data 在 (D0 ~) 与Cell间传输。 ?Control Circuitry: 控制memory Cell 工作状态的电路 CE/ OE/ WE (Chip Enable/ Output Enable / Write Enable)

Unit 2:

Device Testing

? DC parametric test ? AC parametric test ? Functional Test

DC parametric test
DC Parametric Tests:测试 Address Decoder 和 I/O 回路 中Input/Output Buffer 的DC特性。 在DC Test中一般使用 VSIM 及ISVM 的方法。 ISVM:Force current message voltage : VSIM: Force voltage message current

? ? ? ? ?

DC Contact Check Input/Output Leakage Check CMOS Automatic Sleep Standby Current Check Output Drive Voltage & Current

开路/短路测试 OPEN/SHORT 输入/输出漏电流测试 INLEAK/OUTLEAK CMOS自动睡眠模式电流测试 CMOSASM Device不工作时待机电流测试 ICCSB Device 电压及电流驱动能力测试 VOH/VOL

DC Parametric Test
? ? ? ? ?

OPEN / SHOR Test INLEAK/OUTLEAK Test CMOSASM ICCSB Test VOH/VOL Test

Open Test
Purpose:
测量 device pins 是否 correctly to DUT/Tester channel 测量 Device内部 管脚是否有开路。

Test Method
?Ground all pins (including VCC); ?Set Voltage Clamp 3.0 volts; ?Using PMU, force positive or negative current, one pin at a time; ?Measure resultant voltage; ?Fails test (open) if the absolute voltage measured is greater than 1.5V;

Short Test
Purpose: Test Method:
?Ground all pins (including VCC); ?Set Voltage Clamp 3.0 volts; ?Using PMU, force positive or negative Voltage, one pin at a time; ?Measure resultant current; ?Fails test (short) if the absolute voltage measured is less than 0.2V.
Vcc (3.3V) Vcc (3.3V)

测试 the device pins 是否有短路

In (0.3V)

No current through two protect diode

In (0.3V)

No current through two protect diode

I
Vss (0 V)

I
Vss (0 V)

Normal I <100ua

If short I >100ua

Input Leakage Test (INLEAK )
Definition
IIL -- Input leakage low The current in an input when it is forced low voltage. IIH -- Input leakage high The current in an input when it is forced high voltage. Why test? The IIL test measures the resistance from an input pin to VCC, IIH test measures the resistance from an input pin to VSS. The test insures that the input buffers offer a high resistance when apply 0v and VCC.

Input Leakage Low Test---IIL Test---IIL
Test Method
PMU
0V VCCmax Pin Electronics Force Logic 1 on all inputs

IIL
V I
VSS = 0V DUT Input Pin

DUT

Force 0.0v

Measure

? Apply VCCmax.
? Preconditioning all inputs to logic 1 with pin drivers. ? Input disable ? Using PMU, force individual inputs to VSS. ? Measure the current flows from VCC to the pin being tested. ? Repeat the same test on each pin. ? Fails IIL if measured current is outside of the spec.

Input Leakage High Test---IIH Test---IIH
Test Method
PMU
Force VCCmax V
3.5V DUT Input Pin

VCCmax

Pin Electronics Force Logic 0 on all inputs DUT

Measure I

IIH
VSS= 0V

? Apply VCCmax.
? Preconditioning all inputs to logic 0 with pin drivers. ? Input disable ? Using PMU, force individual inputs to VCC. ? Measure the current flows from the pin being tested to VSS. ? Repeat the same test on each pin. ? Fails IIH if measured current is outside of the spec.

Output Leakage Test ---IOL ---IOL
Purpose: To measure the output current leakage (1uA spec) Test Method
? Apply VCCmax. ? Preconditioning all Outputs to logic 1 with pin drivers. ? Output Disable ? Using PMU, force individual inputs to VCC. ? Measure the current flows from the pin being tested to VSS. ? Repeat the same test on each pin. ? Fails IOL if measured current is outside of the spec. OFF ON VCCmax IOL

0.0 v

VSS=0V

Output Leakage Test ---IOH ---IOH
Purpose:
To measure the output current leakage (1uA spec)

Test Method
? Apply VCCmax. ? Preconditioning all Outputs to logic 0 with pin drivers. ? Output Disable ? Using PMU, force individual inputs to VCC. ? Measure the current flows from the pin being tested to VSS. ? Repeat the same test on each pin. ? Fails IOH if measured current is outside of the spec. VSS=0V ON 3.5v
IOH

VCCmax OFF

CMOSASM Test
Purpose:
This test checks the CMOS Automatic Sleep Mode. It is a guardbanded tests using a Vcc which is 15-30% higher than Max. Vcc and tests against a limit of 10% guardband). The input pins are biased at the worst possible condition as well (lowest VIH and highest VIL).

Test Method
? Apply VCCmax.
? chip enabled, but at output disable state. (Automatic Sleep Mode) ? Measure current flowing into VCC pin at VIH &VIL ? Failure CMOSASM when current is out of SPEC
CE=L Chip Enable

Vcc
CMOSASM A

Device On

ICCSB Test
Purpose:
This tests checks the Icc Standby Current(Icc3 in the TTL Table). This test should be done with all inputs high(VIH) and all inputs low(VIL). With the move to eliminate the TTL table(most companies do NOT use TTL logic anymore), this test has decreasing importance.

Test Method
? Apply VCCmax.
?chip disabled, but at output disable state. (Standby Mode) ? Measure current flowing into VCC pin at VIH &VIL ? Failure ICCSB when current is out of SPEC
CE=H Chip Disable

Vcc
ICCSB A

Device (OFF)

Output voltages testing

?VOH/IOH ?VOL/IOL

Output voltages testing---VOH/IOH testing---VOH/IOH
Definition
VOH -- represents the minimum voltage (V) produced by an output (O) when the output is in the logic 1 (High) state. IOH -- represents the current sourcing capabilities (I) of an output (O) when the output is in the logic 1 (High) state.

Why test? VOH/IOH test measures the resistance of an output pin when the output is in the logic 1 state. This test insures that the resistance of the output meets the design parameters and guarantees that the output will provide the specified IOH current while maintaining the proper VOH voltage.

Output voltages testing---VOH/IOH testing---VOH/IOH
DUT

Test Method

VCCmin IOH ON DUT Output Pin

PMU
Force I Measure V

OFF VSS=0V

?Apply VCCmin. ?Precondition output to logic 1 (output high). ?Using PMU, force IOH current per specification. ?Wait 1 to 5 msec (Set PMU delay). ?Measure resultant voltage. ?Fails VOH of measured voltage is less than the limit.

Output voltages testing---VOL/IOL testing---VOL/IOL
Definition
VOL -- represents the maximum voltage (V) produced by an output (O) when the output is in the logic 0 (Low) state. IOL -- represents the current sinking capabilities (I) of an output (O) when the output is in the logic 0 (Low) state.

Why test? VOL/IOL test measures the resistance of an output pin when the output is in the 0 state. This test insures that the resistance of the output meets the design parameters and guarantees that the output will provide the specified IOL current without exceeding the VOL voltage.

Output voltages testing
DUT

Test Method

VCCmin DUT Output Pin IOL VSS=0V

PMU
Force I Measure V

OFF ON

?Apply VCCmin. ?Precondition output to logic 0 (output low). ?Using PMU, force IOL current per specification. ?Wait 1 to 5 msec (Set PMU delay). ?Measure resultant voltage. ?Fails VOL of measured voltage is greater than the limit.

AC Parametric Testing
? Output signal: - the rise & fall times. ? Relationship between input signals: - the setup & hold times. ? Relationship between input and output signals: - the delay times ? Successive relationship between input and output signals: - the speed test.

AC parametric test--- Rise and Fall Time test--?Rise and Fall time - To guarantee that output data rise and fall rate.

AC parametric test---Setup Time TSD test---Setup
?Setup time - TSD to guarantee that input data can be read within a minimum amount of time before a reference signal occurs.

AC parametric test--- Hold Time THD test--?Hold time - THD to guarantee that input data can be read within a minimum amount of time after a reference signal occurs.

AC parametric test--- Program Delay Time test--?Propagation Delay Measurements - TAA to guarantee that an output signal can occur within a specified amount of time after the occurrence of a reference signal.

Functional Test
Functional Test:是为了保证Device的 工作是Match 它的Truth Table 而进行的测试。 由Pattern Generator模拟正常的工作状态,输出Pattern 加入Device, 将输出值与期望值相比较,Match 的为 Pass,不Match 的为Fail。

Hierarchy in Reduced functional Faults

? ? ? ?

Stuck-At Fault Transition Fault Coupling Fault NPSF Neighborhood Pattern Sensitive Fault

StuckStuck-At Fault * The logic value of a stuck-at (SA) cell or
line is always 0 or 1; it is always in state 0 or in state 1 and can not be changed to the opposite state.

Transition Fault
* A cell or line which fails to undergo a 0 -> 1 transition when it is written is said to contain an up transition fault; similarly, a down transition fault is the impossibility of making a 1 -> 0 transition.

Coupling Fault
? A write operation which generates an U or a Y transition in one cell changes the contents of a second cell, where U denotes a write 1 operation to a cell containing a 0 and Y denotes a write 0 operation to a cell containing a 1. The types of coupling faults used for DRAM are based on the following assumptions for read/write operations: 1. A read operation will not cause an error.
2. A non-transition write operation will not cause a fault. 3. A transition write operation may cause a fault.

?

Neighborhood Pattern Sensitive Fault
? A Pattern Sensitive Fault (PSF) is defined as follows: The contents of a cell, or the ability to change the contents, is influenced by the contents of all other cells in the memory. ? The PSF can be considered the most general case of the k-coupling fault. ? The PSF model allows the neighborhood to take on any position in the memory array. ? When the neighborhood is allowed to take on only a single position, one speaks about a Neighborhood Pattern Sensitive Fault (NPSF).

Function Test Item Example
? READ0/READALL+EMBERASE+BLANK ? PRGDIAG ? VERDIAG ? PRGRVCK ? RVCKSP ? PRGSP1 / 2 ? PRGCKBD

READ0/READALL+PREERASE+BLANK
Description:
These test blocks work together to insure the array is blank before testing continues. A portion of the array is read using READ0 or READALL (depending on the flow). Devices which fail this initial blank check are PREERASE, and then the erase is verified with a full Blank Check.

PRGDIAG *
Description:
?PRGDIAG Embedded Programs a reverse DIAG pattern. Each byte/word must program within SPEC ?Hot temperature is worst-case since column leakage is at its highest levels. ?Only the programmed 0’s are verified at this test block.
00 00 01 10 11

0 0 0 0

01

10

11

VERDIAG
Description:
?Reads both 1’s and 0’s of the DIAG pattern. The DIAG pattern is designed to reveal metal shorts (M1-M1, M1-M2, and M2-M2) which cause blank bits to program adjacent to the target programming bit. Programming only one bit per column helps reveal this type of defect. ?In Figure , the array on the right has a metal short between columns (bitlines) 2 and 3. The short accidentally shares the programming drain voltage between the two columns. The programming wordline voltage is common across a row, so programming any bit in column 2 accidentally programs the adjacent bit in column 3.

This is called bit pickup

PRGRVCK --- Programming Reverse CKBD
Description:
?RVCK is a worst-case pattern for speed since outputs switch on every address transition (1-0-1-0…).
00

00

01

10

11

0 0 0 0 0 0

0

01

10

0

11

RVCKSP *--Description:

Reverse CKBD Speed

?RVCKSP tests AC speed by reading the RVCK pattern with tight timing. ?There are usually six speed grades. The program tests units starting with the fastest speed bin, and moving through the six grades until finding a passing bin. ? The actual speed values of the six bins vary from program to program, depending on the speed distribution of the part and Marketing requirements. An example of 3V speed grades is shown below:

PRGSP1 / 2 * --Description:

Program Speed

?The PRGSP1/2 blocks test the AC write parameters ?It Embedded Programs one row and one column using tight timing parameters and address/data formatting. ?A programming failure indicates the write command was not accepted due to the tight write parameters.

PRGCKBD *---

Programming Checkerboard/ Check board verify

Programming Checkerboard Description:
Programs a CKBD pattern, which alternates 1’s and 0’s through the entire array. This checks the programmability of half the array. The surrounding blank bits are NOT read in this test, they are checked in Checkerboard Verify.

PRGCKBD *--- Programming Checkerboard/
Check board verify Checkerboard Verify Description:
Reads both 1’s and 0’s of the CKBD pattern. The CKBD pattern is designed to reveal bit-to-bit shorts, typically caused by poly 1 to poly 1 shorts. Unlike metal shorts which affect entire columns, the poly 1 shorts only affect bits adjacent to the short. So every pair of bits must be checked. By alternating 1’s and 0’s through the whole array, the CKBD pattern accomplishes this task.

Class Test Flow
Parametrics IREF Trim * Opens, Shorts, Icc power tests, Input / Output Lkg trims reference current / VT levels, accounting for temperature difference from wafer sort Embedded Erases the devices if the previous test indicates non-blank verifies the device is blank after the Embedded Erase program DIAG pattern (usually reverse DIAG) to check programmability and prepare for pattern read verify DIAG pattern, checking for failures due to MANDIAG programs a RVCK pattern to check programmability and prepare for pattern read

EMBERASE *

BLANK * PRGDIAG *

VERDIAG PRGRVCK

Class Test Flow (Continues)
RVCKSP * AC speed read of RVCK pattern

VOLVOH *

DC input / output levels

PRGSP1 / 2 *

address / data formatting test to check for AC write parameters program CKBD pattern, bringing array to 0’s pattern

PRGCKBD *

PREPROG *

launches Embedded Erase and stops after pre-programming to bring array to all 0’s and check address sequencer

CHIPSECT *

erases each sector, checking erase and APDE times test ICCDYN, INLEAK, and ICCSSB at end of flow

Outgoing Parametrics *

Basic Test System Components
Pattern Memory for Parallel and Scan Vectors Network Interface Timing Formatting, Masking and Timeset Memory Special Tester Options PMU Precision Measurement Unit Load Board with DUT

System Clocks and Calibration Circuits

CPU with Hard Disk, Tape Drive, Keyboard & Video

Internal Controll er CPU

System Power Supplies

DPS and Reference Supplies (for VCC, VIL, VIH, VOL, VOH)

Test Head Pin Electronics Drivers, Comparators, Current Loads, etc.


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