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DS12CR887-DS12R887


Rev 4; 5/06

RTC DS12R885/DS12CR887/DS12R887
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DS12R885 DS12885 RTC/ RAM AM/PM VCC 12 V BACKUP DS12R885 Intel Motorola DS12R887 DS12R885 31 24 122μs DS12CR887 14 114 0 RAM +5.0V DS12CR887 DS12R887 BGA DIP (EDIP) +3.3V 500ms (RTC) 114

__________________________________
RTC 2100 Intel Motorola

_________________________________

__________________________
CRYSTAL VCC

______________________________
PART DS12R885-5 DS12R885-33 DS12CR887-5
SQW

TEMP RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C

PINPACKAGE 24 SO (300 mils) 24 SO (300 mils) 24 EDIP (700 mils) 24 EDIP (700 mils)

TOP MARK DS12R885-5 DS12R885-33 DS12CR887-5 DS12CR887-33 DS12R887-5 DS12R887-33

X1 AS R/W DS

X2

VCC RESET RCLR

DS83C520

CS AD(0–7) IRQ MOT

DS12R885

DS12CR887-33
SUPER CAP

VBACKUP
±

DS12R887-5 DS12R887-33

-40°C to +85°C 48 BGA -40°C to +85°C 48 BGA

GND

______________________________________________ Maxim Integrated Products

1

Maxim

Maxim Maxim

Maxim

www.maxim-ic.com.cn

RTC DS12R885/DS12CR887/DS12R887
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC Pin Relative to Ground .....-0.3V to +6.0V Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature .......................................See IPC/JEDEC J-STD-020A Specification Soldering Temperature (leads, 10s) ................................+260°C

Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER Supply Voltage (Note 2) VBACKUP Input Voltage (DS12R885 Only) Input Logic 1 Input Logic 0 VCC Power-Supply Current (Note 3) VCC Standby Current (Note 4) Input Leakage I/O Leakage Input Current Output Current at 2.4V Output Current at 0.4V Power-Fail Voltage (Note 2) VRT Trip Point Trickle-Charger Current-Limiting Resistor Trickle-Charger Output Voltage SYMBOL VCC VBACKUP VIH VIL ICC1 ICCS IIL IOL IMOT IOH IOL VPF VRTTRIP R1 VOUT (Note 5) (Note 6) (Note 2) (Note 2) -33 -5 -33 -5 DS12R885 Only DS12R885 Only 2.7 4.05 2.88 4.33 1.3 10 3.05 -33 -5 (Note 2) (Note 2) (Note 2) -33 -5 -5 -33 -1.0 -1.0 -1.0 -1.0 4.0 2.97 4.5 CONDITIONS MIN 2.97 4.5 2.0 2.2 -0.3 0.7 0.8 0.250 0.140 TYP 3.3 5.0 MAX 3.63 5.5 VOUT VCC + 0.3 +0.8 2 2 0.5 0.3 +1.0 +1.0 +500 UNITS V V V V mA mA μA μA μA mA mA V V kΩ V

2

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RTC DS12R885/DS12CR887/DS12R887
DC ELECTRICAL CHARACTERISTICS (DS12R885 Only)
(VCC = 0V, VBACKUP = 3.2V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER VBACKUP Current (OSC On); TA = +25°C, VBACKUP = 3.0V VBACKUP Current (Oscillator Off) SYMBOL IBACKUP2 (Note 7) CONDITIONS MIN TYP 800 MAX 1000 100 UNITS nA nA

IBACKUPDR (Note 7)

AC ELECTRICAL CHARACTERISTICS
(VCC = 4.5V to 5.5V, TA = -40°C to +85°C.) (Note 1)
PARAMETER Cycle Time Pulse Width, DS Low or R/W High Pulse Width, DS High or R/W Low Input Rise and Fall R/W Hold Time R/W Setup Time Before DS/E Chip-Select Setup Time Before DS or R/W Chip-Select Hold Time Read-Data Hold Time Write-Data Hold Time Address Valid Time to AS Fall Address Hold Time to AS Fall Delay Time DS/E to AS Rise Pulse Width AS High Delay Time, AS to DS/E Rise Output Data Delay Time from DS or R/W Data Setup Time Reset Pulse Width IRQ Release from DS IRQ Release from RESET SYMBOL tCYC PWEL PWEH tR, tF tRWH tRWS tCS tCH tDHR tDHW tASL tAHL tASD PWASH tASED tDDR tDSW tRWL tIRDS tIRR (Note 8) 0 10 5 0 5 0 20 5 10 30 35 15 50 5 0 0 2 2 60 35 CONDITIONS MIN 180 80 65 30 TYP MAX DC UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns μs μs μs

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3

RTC DS12R885/DS12CR887/DS12R887
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.97V to 3.63V, TA = -40°C to +85°C.) (Note 1)
PARAMETER Cycle Time Pulse Width, DS Low or R/W High Pulse Width, DS High or R/W Low Input Rise and Fall R/W Hold Time R/W Setup Time Before DS Chip-Select Setup Time Before DS or R/W Chip-Select Hold Time Read-Data Hold Time Write-Data Hold Time Address Valid Time to AS Fall Address Hold Time to AS Fall Delay Time DS to AS Rise Pulse Width AS High Delay Time, AS to DS Rise Output Data Delay Time from DS or R/W Data Setup Time Reset Pulse Width IRQ Release from DS IRQ Release from RESET SYMBOL tCYC PWEL PWEH tR, tF tRWH tRWS tCS tCH tDHR tDHW tASL tAHL tASD PWASH tASED tDDR tDSW tRWL tIRDS tIRR (Note 8) 0 15 8 0 5 0 30 15 15 45 55 20 70 5 0 0 2 2 80 55 CONDITIONS MIN 280 130 90 30 TYP MAX DC UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns μs μs μs

4

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RTC DS12R885/DS12CR887/DS12R887
__________________________________________________________ Motorola /

PWASH AS tASD tCYC DS PWEL tRWS R/ W tCH CS tCS tDSW AD0–AD7 WRITE tASL AD0–AD7 READ tAHL tDHR tDDR tDHW PWEH tRWH tASED

_____________________________________________________________________________ Intel

tCYC AS tASD DS tASD R/W PWEL tCS CS tASL AD0–AD7 WRITE tAHL tDSW tDHW tASED PWEH tCH PWASH

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5

RTC DS12R885/DS12CR887/DS12R887
___________________________________________________________________ Intel
tCYC AS tASD DS tASD R/W tCH tCS CS tASL AD0–AD7 tAHL tDDR tDHR PWASL PWASH tASED PWEH

______________________IRQ
DS RESET tRWL

IRQ tIRDS

tIRR

____________________________________________________________________
VCC VPF(MAX)
VPF(MIN)

/

tF

tR tRPU tDR

INPUTS

RECOGNIZED

DON'T CARE

RECOGNIZED

HIGH-Z OUTPUTS VALID VALID

6

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RTC DS12R885/DS12CR887/DS12R887
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA = -40°C to +85°C) (Note 1)
PARAMETER Recovery at Power-Up VCC Fall Time; VPF(MAX) to VPF(MIN) VCC Rise Time; VPF(MIN) to VPF(MAX) SYMBOL tRPU tF tR CONDITIONS MIN 20 300 0 TYP MAX 200 UNITS ms μs μs

DATA RETENTION (DS12CR887)
PARAMETER Expected Data Retention SYMBOL tDR TA = +25°C CONDITIONS MIN 5 TYP MAX UNITS Years

CAPACITANCE
(TA = +25°C)
PARAMETER Capacitance on All Input Pins Except X1 and X2 Capacitance on IRQ, SQW, and DQ Pins SYMBOL CIN CIO (Note 9) (Note 9) CONDITIONS MIN TYP MAX 10 10 UNITS pF pF

AC TEST CONDITIONS
PARAMETER Input Pulse Levels (-5) Input Pulse Levels (-33) Output Load Including Scope and Jig (-5) Output Load Including Scope and Jig (-33) Input and Output Timing Measurement Reference Levels Input-Pulse Rise and Fall Times 0 to 3.0V 0 to 2.7V 50pF + 1TTL Gate 25pF + 1TTL Gate Input/Output: VIL maximum and VIH minimum 5ns TEST CONDITIONS

WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data.
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Limits at -40°C are guaranteed by design and not production tested. All voltages are referenced to ground. All outputs are open. Specified with CS = DS = R/W = RESET = VCC; MOT, AS, AD0–AD7 = 0; VBACKUP open. Applies to the AD0 to AD7 pins, the IRQ pin, and the SQW pin when each is in a high-impedance state. The MOT pin has an internal 20kΩ pulldown. Measured with a 32.768kHz crystal attached to X1 and X2. Measured with a 50pF capacitance load. Guaranteed by design. Not production tested.

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7

RTC DS12R885/DS12CR887/DS12R887
____________________________________________________________________
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)

IBACKUP vs. VBACKUP (DS12R885)
DS12R885 toc01

VBACKUP vs. VCC vs. IBACKUP (DS12R885)
VCC = 0V 3.0
DS12R885 toc02

625

0μA -15μA -30μA -45μA

2.8

SUPPLY CURRENT (nA)

600 VBACKUP 575 2.2 550 2.0 2.3 2.5 VBACKUP (V) 2.8 3.0 2.6

2.4 -60μA

2.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC

IBACKUP vs. TEMPERATURE (DS12R885)
625 SUPPLY CURRENT (nA) 600 575 550 525 500 475 450 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (°C) FREQUENCY (Hz) VCC = 0V, VBACKUP = 3.0V
DS12R885 toc03

OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE
32768.08 32768.06 32768.04 32768.02 32768.00 32767.98 32767.96 32767.94 32767.92 32767.90 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY (V)
DS12R885 toc04

650

32768.10

8

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RTC DS12R885/DS12CR887/DS12R887
_______________________________________________________________________

X1 OSC X2 DS12R887/ DS12CR887 ONLY VCC VBACKUP POWER CONTROL AND TRICKLE CHARGER DIVIDE BY 8 DIVIDE BY 64 DIVIDE BY 64

16:1 MUX SQUAREWAVE GENERATOR SQW IRQ

GND DS12R887/ DS12CR887 ONLY

DS12R885
CS R/W DS AS MOT RESET AD0–AD7 BUS INTERFACE CLOCK/CALENDAR UPDATE LOGIC

IRQ GENERATOR

REGISTERS A, B, C, D

CLOCK/CALENDAR AND ALARM REGISTERS BUFFERED CLOCK/ CALENDAR AND ALARM REGISTERS USER RAM 114 BYTES

RLCR

_______________________________________________________________________
SO 1 PIN EDIP 1 BGA C5 NAME FUNCTION Motorola or Intel Bus Timing Selector. This pin selects one of two bus types. When Motorola Intel VCC connected to VCC, Motorola bus timing is Intel selected. When connected to GND or left Motorola disconnected, Intel bus timing is selected. The pin has an internal pulldown resistor. Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for32.768kHz with a crystal having a 12.5pF specified load capacitance (CL). Pin operation CL 12.5pF X1 is the input to X1 oscillator and can optionally 32.768kHz the be connected to an external 32.768kHz X1 oscillator. The output X2the internal oscillator, pin X2, is floated if an external oscillator is of connected to pin X1. Multiplexed, Bidirectional Address/Data Bus. The addresses are presented during the first portion of /the bus cycle and latched into the DS12R885 by the falling AS of AS. Write edge data is latched by the falling edge of DS (Motorola timing) or the rising edge of R/W (Intel DS12R885 DS Motorola R/W Intel DS12R885 DS DS R/W timing). In a read cycle, the DS12R885 outputsMotorola data during the latter portion of DS (DS and Intel R/W high for DS Motorola R/W DS low and R/W high for Intel timing). The read cycle is timing, DS the bus returns to a high-impedance state as DS transitions low in the case Intel terminated and Motorola of Motorola timing or as DS transitions high in the case of Intel timing.

MOT

2





X1

3





X2

4–11

4–11

F4, D4, F3, D3, F2, D2, F1, D1

AD0– AD7

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9

RTC DS12R885/DS12CR887/DS12R887
____________________________________________________________________
SO 12, 16 PIN EDIP 12 BGA D5–D8, E1–E8, F5–F8 NAME FUNCTION

(

)

GND

Ground Chip-Select Input. The active-low chip-select signal must be asserted low for a bus cycle in the DS12R885 to be accessed. CS must be DS12R885 active state during DS and AS kept in the DS AS Intel for Motorola timing and during DS and R/W for Intel timing. DS cycles that take place Motorola Bus R/W V CS CS VCC without asserting CS latch addresses, but no access occurs. When VCC is below VPF PF volts, DS12R885 CS RTC the DS12R885 inhibits access by internally disabling the CS input. This action protects the RAM RTC data and the RAM data during power outages. Address Strobe Input. A positive-going address-strobe pulse serves to demultiplex the bus. The falling edge of AS causes the address to be latched within the DS12R885. The AS next rising edge that occurs on CS AS bus clears the address regardless of whether CS is the DS12R885 AS CS asserted. An address strobe must immediately precede each write or read access. If a CS write or read is performed with CS deasserted, another address strobe must be performed prior to a read or write access with CS asserted. Read/Write Input. The R/W pin has two modes of operation. When the MOT pin is connected to VCC for Motorola timing, R/W is at a level that indicates whether the current / R/W MOT cycle is a read or write. A read cycle is indicated with aVCC level on R/W while R/Wis high. high Motorola DS DS R/W R/W A write cycle is indicated when R/W is low during DS. When the MOT pin is connected to MOT Intel R/W R/W GND for Intel timing, the R/W signal is an active-low signal. In this mode, the R/W pin RAM (WE) operates in a similar fashion as the write-enable signal (WE) on generic RAMs. Data are latched on the rising edge of the signal. No Connection. This pin should remain unconnected. On the EDIP, these pins are missing EDIP by design. Data Strobe or Read Input. The DS pin has two modes of operation depending on the level of the MOT pin. When the MOT pin is connected to VCC, Motorola bus timing is selected. In this MOT mode, DS is a positiveDS se during the latter portion of the bus MOT and is VCC data pul cycle called Motorola DS strobe. During read cycles, DS signifies the time that the DS12R885 is to drive the DS DS12R885 DS DS12R885 bidirectional bus. In write cycles, the trailing edge of DS causes the DS12R885 to latch the MOT Intel DS DS12R885 written data. When the MOT pin is connected to GND, Intel bus (OE) is selected. DS timing DS RAM identifies the time period when the DS12R885 drives the bus with read data. In this mode, the DS pin operates in a similar fashion as the output-enable (OE) signal on a generic RAM.

13

13

C1

CS

14

14

C3

AS

15

15

C2

R/W

22

2, 3, 16, 20–22

A3

N.C.

17

17

A1

DS

10

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RTC DS12R885/DS12CR887/DS12R887
____________________________________________________________________
PIN SO EDIP BGA NAME FUNCTION Reset Input. The active-low RESET pin has no effect on the clock, calendar, or RAM. On power-up, the RESET pin can be held low for a timeRAM to allow the power supply to stabilize. RESET RESET The amount of time that RESET is held low is dependent on the application. However, if RESET is used on power-up, the time RESET is low should exceed 200ms to ensure that RESET RESET 200ms the internal timer that controls the DS12R885 on power-up has timedCC When RESET is DS12R885 RESET V out. VPF low and VCC is above VPF, the following occurs: A. (PIE) 0 A. Periodic interrupt-enable (PIE) bit is cleared to 0. B. (AIE) 0 B. Alarm interrupt-enable (AIE) bit is cleared to 0. C. (UIE) 0 C. Update-ended interrupt-enable (UIE) bit is cleared to 0. D. (PF) 0 D. Periodic-interrupt flag (PF) bit is cleared to 0. E. (AF) 0 E. Alarm-interrupt flag(UF) bit is cleared to 0. (AF) F. 0 F. Update-ended interrupt flag (UF) bit is cleared to 0. G. (IRQF) 0 G. Interrupt-request status flag (IRQF) bit is cleared to 0. H. IRQ I. RESET H. IRQ pin is in the high-impedance state. (SQWE) 0 I. J. The device is not accessible until RESET is returned high. RESET V (SQWE) bit is DS12R885 0. J. Square-wave output-enableCC cleared to In a typical application, RESET can be connected to VCC. This connection allows the DS12R885 to go in and out of power fail without affecting any of the control registers. Interrupt Request Output. The IRQ pin is an active-low output of the DS12R885 that can be used as an interrupt input to a processor. The IRQ output remains low as long as the DS12R885 IRQ status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. IRQ The processor program normally reads the C register to clear the IRQ pin. The RESET pin C IRQ RESET also clears pending interrupts. When no interrupt conditions are present, the IRQ level is in IRQ IRQ the high-impedance state. Multiple interrupting devices can be connected CC an IRQ bus, IRQ V to provided that they are all open drain. The IRQ pin is an open-drain output and requires an external pullup resistor to VCC. Connection for Rechargeable Battery or Super Cap. This pin provides trickle charging VCC VBACKUP when VCC is greater than VBACKUP. RAM Clear. The active-low RCLR pin is used to clear (set to logic 1) all 114 bytes of RAM RCLR 1) general-purpose RAM, but does not affect the (RAM associated114 the RTC. ToRAM the with clear RCLR RAM RAM VCC RAM, RCLR RTC be forced to an input logic 0 during battery-backup mode when VCC is must ( ) not applied. 0 RCLR function is designed to be used through a human interface The RCLR (shorting to ground manually or by a switch) and not to be driven with external buffers. This pin is internally pulled up. Do not use an external pullup resistor on this pin. Square-Wave Output. The SQW pin can output a signal from one of 13 taps provided by the 15 internal divider stagesRTC RTC. The frequency of the SQW pin can be changed of the 15 SQW 13 A SQW 1 SQW B SQWE by programming Register A, as shown in Table 1. The SQW signal can be turned on and V Register B. The SQW signal is not available when VCC is less SQW VCC off using the SQWE bit in PF than VPF. DC Power Pin for Primary Power Supply. When VCC is applied within normal limits, the DC VCC device is fully accessible and data can be written and read. When VCC is below VPF reads VPF VCC and writes are inhibited.

(

)

18

18

A2

RESET

19

19

A4

IRQ

20





VBACKUP

21



A5

RCLR

23

23

C4

SQW

24

24

A6–A8, B1–B8, C6–C8

VCC

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11

RTC DS12R885/DS12CR887/DS12R887
______________________________
DS12R885 14 114 DS12885 RTC / / RAM 24

____________________________
DS12R885 32.768kHz 1 1 PCB ESR

DS12R885 AM/PM VCC 12

/ DS12R885 DS12R887 / 114 RAM AM/PM VCC 31 24 12 Intel Motorola 32.768kHz X1 32.768kHz X2 1 DS12R885 DS12R885

1.
PARAMETER Nominal Frequency fO

*
SYMBOL MIN TYP 32.768 50 12.5 MAX UNITS kHz kΩ pF

I/O Motorola DS12CR887 EDIP DS12R885 +25°C DS12R887 BGA V CC ) ) 98 ( 10% 90% 30 (11 VCC 90% DS12R885

I/O

Intel

Series Resistance Load Capacitance

ESR CL

VCC

*

RF 58 Crystal Considerations with Dallas RealTime Clocks (RTCs)

(+25°C 11 ( 10%
COUNTDOWN CHAIN

x 1000

) 1000 30 8 (98

x 30

)
C L1 CL 2 RTC REGISTERS

DS12R885
X1 CRYSTAL X2

1.

12

____________________________________________________________________

RTC DS12R885/DS12CR887/DS12R887
______________________________
LOCAL GROUND PLANE (LAYER 2)

X1

2 58 Dallas Real-Time Clocks (RTCs) DS12R887 DS12CR887 +25°C PCB Crystal Considerations with tDR ±1

CRYSTAL X2

_____________________
VCC V CC VCC ) A) t REC

/
RAM V BACKUP VPF ( (

NOTE: AVOID ROUTING SIGNAL LINES IN THE CROSSHATCHED AREA (UPPER LEFT QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE DEVICE PACKAGE.

GND

2.

( (DM) B SET 0 RTC 10

BCD 10 RTC

) B

10

2A

2B 24-12 1 PM

BCD 12

____________________________

10 BCD 1 1 7 31 B SET 1

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13

RTC DS12R885/DS12CR887/DS12R887

0 ( 1 2A 2B) / 0

0 128 1) C0 1 FF 2) 3) C A D 7 MSB

2A.
ADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH-7F UIP SET IRQF VRT X BIT 7 0 0 0 0 AM/PM 0 AM/PM 0 0 0 0 0 0 0 0 0 DV2 PIE PF 0 X 0 10 Years DV1 AIE AF 0 X DV0 UIE UF 0 X BIT 6 BIT 5 BIT 4 10 Seconds 10 Seconds 10 Minutes 10 Minutes 0 0 0

BCD
BIT 3

(DM = 0)
BIT 2 BIT 1 Seconds Seconds Minutes Minutes Hours Hours 0 Date Month Year RS3 RS2 DM 0 0 X RS1 24/12 0 0 X RS0 DSE 0 0 X Day BIT 0 FUNCTION Seconds Seconds Alarm Minutes Minutes Alarm Hours Hours Alarm Day Date Month Year Control Control Control Control RAM RANGE 00–59 00–59 00–59 00–59 1–12 +AM/PM 00–23 1–12 +AM/PM 00–23 01–07 01–31 01–12 00–99 — — — — —

10 Hours 10 Hours 10 Hours 10 Hours 0 10 Date 10 Months

SQWE 0 0 X

X=

/ 0 0 0 1

14

____________________________________________________________________

RTC DS12R885/DS12CR887/DS12R887
2B.
ADDRESS 00H 01H 02H 03H 04H 0 AM/PM 05H 0 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH-7F 0 0 0 0 UIP SET IRQF VRT X 0 0 0 DV2 PIE PF 0 X 0 0 0 DV1 AIE AF 0 X 0 0 DV0 UIE UF 0 X Year RS3 SQWE 0 0 X 0 0 0 Hours 0 Date Month RS2 DM 0 0 X RS1 24/12 0 0 X RS0 DSE 0 0 X Day Day Date Month Year Control Control Control Control RAM BIT 7 0 0 0 0 AM/PM 0 0 Hours Hours Hours Alarm BIT 6 0 0 0 0 0 BIT 5 BIT 4

(DM = 1)
BIT 3 BIT 2 Seconds Seconds Minutes Minutes Hours Hours BIT 1 BIT 0 FUNCTION Seconds Seconds Alarm Minutes Minutes Alarm RANGE 00–3B 00–3B 00–3B 00–3B 01–0C +AM/PM 00–17 01–0C +AM/PM 00–17 01–07 01–1F 01–0C 00–63 — — — — —

X=

/ 0 0 0 1

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15

RTC DS12R885/DS12CR887/DS12R887
____________________________
DS12R885 4

A
BIT 7 UIP BIT 6 DV2 BIT 5 DV1 BIT 4 DV0 BIT 3 RS3 BIT 2 RS2 BIT 1 RS1 BIT 0 RS0

7 UIP 1 244μs RESET

(UIP) UIP 0 UIP 0 RAM UIP B SET 1 UIP DV0 010 11X 010 DV0 DV1

3

0

(RS3 15

RS2

RS1 13

RS0) (SWQ

) 1) 2) 3)

/ PIE SQWE SQW

6 RTC

5

4

DV2

DV1

DV2

500ms

4) 3 / RS RESET

16

____________________________________________________________________

RTC DS12R885/DS12CR887/DS12R887
B
BIT 7 SET BIT 6 PIE BIT 5 AIE BIT 4 UIE BIT 3 SQWE BIT 2 DM BIT 1 24/12 BIT 0 DSE

7

SET SET 1 SET

0 1 SET

3 SQWE / VPF

(SQWE) A 0 SQW RESET

1

SQW RS3 – RS0 SQWE SQW SQWE

/ 6 C PIE IRQ 0

RESET

DS12R885 (PIE) PIE / (PF) IRQ A RS3– RS0 PIE IRQ DS12R885 0 PF

VCC 0 2

RESET (DM) BCD DM

1

DS12R885 RESET DM 1 0 BCD 1 / / 1

PIE RESET 5 1 IRQ ( ) C (AIE)

AIE

/ (AF)

1 24/12 24/12 24 0 12 DS12R885 RESET 0 (DSE) DSE

11XXXXXX AIE IRQ AIE DS12R885 0 RESET (UIE) C RESET DS12R885 SET UIE (UF)

0

AF

4

/ UIE RESET IRQ UIE

1:59:59 AM 3:00:00 AM 1:59:59 AM 1:00:00 AM / DSE DSE 0 DS12R885 RESET

DSE

0

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17

RTC DS12R885/DS12CR887/DS12R887
C
BIT 7 IRQF BIT 6 PF BIT 5 AF BIT 4 UF BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 0

7 1 PF = PIE = 1 AF = AIE = 1 UF = UIE = 1 IRQF 1 C RESET 6 RS3 RS0 PF PIE

(IRQF)

5 IRQF 4 1

(AF) AIE

AF 1

1 IRQ C RESET UF IRQF 1 C RESET

IRQ (PF) 1 PF 1 PIE IRQF 3

1 IRQ 0

UIE

1

(UF) UF

1

C 0

1 C

IRQ RESET

1

D
BIT 7 VRT BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 0

7 RAM VBACKUP 1 RAM

(VRT) 0 RESET RTC

6

0 0

D

18

____________________________________________________________________

RTC DS12R885/DS12CR887/DS12R887
__________________
DS12R885 114 NV RAM C

RAM (NV RAM)
1 IRQ IRQF C IRQ RTC (IRQF ) 1 C

IRQ

1 7 IRQF

_________________________________
DS12R885 500ms 122μs

DS12R885

__________________________
DS12R887 A 11x DS12CR887 4 6 010 (DV2 = 1, DV1 = 1, DV0 = X) 4

B 1 0 IRQ IRQ

6

__________________________
15 C B 13 A ( 1) SQWE 1 C C 1( ) 0 1 RS3 B B PIE SQWE ( 1) RS0–RS3 SQW 16 1

1

________________________
500ms 122μs A A RS0 – IRQ

C C

1

2

3

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19

RTC DS12R885/DS12CR887/DS12R887
3.
SELECT BITS REGISTER A RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 tPI PERIODIC INTERRUPT RATE None 3.90625ms 7.8125ms 122.070μs 244.141μs 488.281μs 976.5625μs 1.953125ms 3.90625ms 7.8125ms 15.625ms 31.25ms 62.5ms 125ms 250ms 500ms SQW OUTPUT FREQUENCY None 256Hz 128Hz 8.192kHz 4.096kHz 2.048kHz 1.024kHz 512Hz 256Hz 128Hz 64Hz 32Hz 16Hz 8Hz 4Hz 2Hz

RTC 999ms C A UIP 244μs / 244μs C ( PF 3) 1 1 A UIP t BUC IRQF (UIP) UIP UIP 244μs /

______________________________
B SET B SET DS12R885 1

(tP1/2 + tBUC)

1 SECOND UIP tBUC UF

tP1/2
PF t PI tBUC = DELAY TIME BEFORE UPDATE CYCLE = 244μs

tP1/2

3. UIP

20

____________________________________________________________________

RTC DS12R885/DS12CR887/DS12R887
PCB ________________________________
EDIP BGA IPC/ BGA 1. 2. 3. 4. ( 160°C) 90 180 100 60 150°C 170°C 200°C JEDEC J-STD-020B EDIP (DS12CR887) +85°C (MSD) 5. 6. 220°C 30 230°C

________________________________________________________________________

TOP VIEW
MOT 1 X1 2 X2 3 AD0 4 AD1 5 AD2 6 AD3 7 AD4 8 AD5 9 AD6 10 AD7 11 GND 12 24 VCC 23 SQW 22 N.C. 21 RCLR 20 VBACKUP MOT 1 N.C. 2 N.C. 3 AD0 4 AD1 5 AD2 6 AD3 7 AD4 8 AD5 9 AD6 10 AD7 11 GND 12 24 VCC 23 SQW 22 N.C. 21 N.C. 20 N.C.

DS12R885

19 IRQ 18 RESET 17 DS 16 GND 15 R/W 14 AS 13 CS

DS12CR887

19 IRQ 18 RESET 17 DS 16 N.C. 15 R/W 14 AS 13 CS

SO (0.300")

EDIP (0.700")

____________________________________________________________________

21

RTC DS12R885/DS12CR887/DS12R887
__________________________
TOP VIEW (BUMP SIDE DOWN)
A DS 1 RESET VCC R/W 2 N.C. 3 IRQ 4 RCLR VCC MOT 5 VCC 6 VCC 7 VCC 8 VCC VCC GND GND GND VCC VCC GND GND GND VCC VCC GND GND GND GND GND GND VCC SQW AD1 GND AD0 VCC AS AD3 GND AD2 B VCC C CS D E F

(

)

______________________________
PACKAGE SO THETA-JA (°C/W) 105 THETA-JC (°C/W) 22

AD7 GND AD6

______________________________
TRANSISTOR COUNT: 17,061 PROCESS: CMOS SUBSTRATE CONNECTED TO GROUND

DS12R887

AD5

GND AD4

______________________________
www.maxim-ic.com.cn/DallasPackInfo

48 BGA

22 _________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 2006 Maxim Integrated Products Printed USA


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