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ENGINEERING SPECIFICATIONS
TFT COLOR LCD MODULE

TM141XG-02L05
- 36cm (14.1 inch) diagonal - XGA resolution (1024 x 768 pixels) - LVDS (6 bits x RGB) - Side mount - With CFL backlight unit - Nonglare surface type

(TENTATIVE)
Ver. 2 Jan. 31, 2001

Tottori SANYO Electric Co., Ltd. Electric Devices Business Headquarters LCD Division

3-201, Minami-yoshikata, Tottori, 680-8634 Japan TEL: 81-857-21-2941, 1958 FAX: 81-857-21-2162

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NOTICES 1. The contents stated in this document and the product may be subject to change without prior notice. When you kindly study to use this product, please ask our distributor or us for the latest information. 2. This product is developed and produced for usage onto normal electronic products (office automation equipments, communication peripherals, electric appliance products, game machines, etc.) and is not suitable for applications which need extremely high reliability and extreme safety (aero- or space-use machines, control equipments for nuclear power, life keeping equipments, etc.). 3. This document shall not grant or guarantee any right to adapt intellectual property or any other patents of third party. 4. Please use this product correctly according to operating conditions and precautions for use stated in this document. Please install safety proof in your designing to avoid human accident, fire accident and social damage, which may be resulted from malfunction of this product. 5. This product is not designed to withstand against radiant rays. 6. It is strictly prohibited to copy or publish a part or whole of this document without our prior written approval.

REVISION HISTORY
DATE Sep. 13, 00 Jan. 31, 01 REVISION NO. Ver. 1 Ver. 2 PAGE 2/16 DESCRIPTIONS Initial Release MECHANICAL CHARACTERISTICS Weight: TBD 515g TYP. ELECTRICAL ABSOLUTE MAXIMUM RATINGS Define the Maximum value of Lamp supply voltage: VHV=2000Vrms and VLGND=100Vrms. ELECTRICAL CHARACTERISTICS Power Supply current IDD: TBD 380mA TYP. and 700mA MAX. OPTICAL CHARACTERISTICS Contrast ratio CR: (250) TYP. 300 TYP. Response time tR(Rise): (35) ms TYP. 32 ms TYP. BACKLIGHT CHARACTERISTICS CFL voltage VL: TBD TYP. 640 Vrms TYP. Operating frequency fL: TBD TYP. and 60kHz MAX. 60 kHz TYP. and 65kHz MAX. Start up voltage VS: TBD MAX. 1350 Vrms MAX. Add the Note 4 about the type of inverter. OUTER DIMENSIONS Change the definition of side mounting screw penetration. Define the tolerance of side mounting hole position. Define the torque of side mounting screw.

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MECHANICAL CHARACTERISTICS
ITEM Module size Resolution Sub-pixel pitch Pixel pitch Active area Effective viewing area Bezel opening area Weight SPECIFICATION 298.5(W) x 227.0(H) x 6.1 Max.(t) 1024 x R.G.B(W) x 768(H) 0.093(W) x 0.279(H) 0.279(W) x 0.279(H) 285.696(W) x 214.272(H) 288.7(W) x 216.3(H) 289.9(W) x 218.5(H) 515 TYP. Ta=25 degC UNIT mm pixel mm mm mm mm mm g

ELECTRICAL ABSOLUTE MAXIMUM RATINGS
ITEM Power supply voltage Input voltage CFL current Lamp supply voltage SYMBOL VDD-VSS VI IL VHV VLGND MIN -0.3 VSS-0.3 MAX 4.0 VDD+0.3 6.5 2000 100 UNIT V V mA Vrms Vrms Ta=25 degC NOTE

ENVIRONMENTAL ABSOLUTE MAXIMUM RATINGS
ITEM Ambient temperature Humidity Vibration Shock SYMBOL TST TOP CONDITIONS Storage Operation Ta=40 degC max. Storage Storage MIN -20 0 MAX 60 50 85 1.5 50 UNIT degC %RH G G Ta=25 degC NOTE Note 1 No condensation Note 2 Note 3 XYZ 11ms/direction

[Note 1] Care should be taken so that the LCD module may not be subjected to the temperature beyond this specification. [Note 2] Ta>40 degC: Absolute humidity shall be less than that of 85%RH/40 degC. [Note 3] 10-200Hz, 30min/cycle, X/Y/Z each one cycle and except for resonant frequency.

ELECTRICAL CHARACTERISTICS
ITEM Power supply voltage LVDS input Threshold voltage LVDS input Termination resistor Power Supply current VDD=3.3V ,fV=60Hz ,fCLK=65MHz ,Ta=25 degC SYMBOL CONDITIONS MIN TYP MAX UNIT NOTE VDD-VSS 3.0 3.3 3.6 V VTH High level +100 mV VCM=1.2V VTL Low level -100 RT IDD Note 1 100 380 700 ohms mA Internal

[Note 1] Under the following display image : Typical Value: Display pattern is 64 gray scale bar. [Note 2] VCM : Common mode voltage of LVDS input

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OPTICAL CHARACTERISTICS
ITEM SYMBOL CONDITIONS Brightness B φ =0 deg. Brightness uniformity φ =0 deg. δB φ =0 deg. Contrast ratio CR θ= 0 deg. θ= 90 deg. Viewing angle range CR>10 φ θ=180 deg. θ=270 deg. Rise tr Response φ =0 deg. time Fall tf x Red y x Green y Color of CIE φ =0 deg. Coordinate x Blue y x White y MIN 100 150 30 40 10 40 0.283 0.299 Ta=25 degC, VDD=3.3V, fV=60Hz TYP MAX UNIT NOTE 2 150 cd/m Note 5,7,8 1.45 Note 6,7,8 300 Note 2,4,8 Note 1,2, deg. 4,8 32 50 ms. Note 3,4,8 13 30 (0.58) (0.35) (0.31) (0.56) Note 4,8 (0.15) (0.11) 0.313 0.343 0.329 0.359

φ
θ =180

DATA

Black
100%

White

Black

B
θ =270 θ=90

90% 10% 0%

θ θ =0

tr

tf

[Note 1] φ and θ

[Note 3] Response time

[Note 2] The contrast ratio "CR" is defined as : Brightness at White CR = Brightness at Black

[Note 4] This shall be measured at center (point No.3 shown in Note 7).

[Note 5] The brightness shall be the average of five points.

[Note 6] The brightness uniformity " δB" is defined as :

δB =

Maximum brightness of five points Minimum brightness of five points

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[Note 7] Measurement points 1/6H 1/2H

5/6H Active area

1/6V 1/2V 5/6V

1 3 4

2

5

Vp: Total Number of Vertical pixel Hp: Total Number of horizontal pixel

[Note 8] Measurement condition (1) Measurement equipment: BM-5A (TOPCON Corp.), Field=2 degree (2) Ambient temperature Ta: 25 +/- 2 degC (3) LCD: All pixels are WHITE, VDD=3.3V, fV=60Hz (4) Measure after 30 minutes of CFL warm up. (5) IL=6.0 mArms with the CFL inverter CXA-L0612A-VJL (TDK).

BACKLIGHT CHARACTERISTICS
ITEM SYM. CONDITIONS MIN CFL voltage VL CFL current IL 3.0 Operating frequency fL 40 Start up voltage VS CFL life time tOL 10000 TYP 640 60 MAX 6.0 65 1350 UNIT Vrms mArms kHz Vrms hrs Ta=25 degC NOTE at IL=6.0mArms
(Recommended value) (Recommended value)

at Ta=0 degC at IL=6.0 mArms

[Note 1] Backlight driving conditions (operating frequency fL especially) may interfere with horizontal frequency fH, causing the beat or flicker on the display. Therefore the operating frequency fL shall be adjusted in relation to horizontal frequency fH to avoid interference. [Note 2] The inverter open voltage should be large than start up voltage, otherwise backlight may blinking for a moment after turns on or not be turned on. And this voltage should be applied to lamp for more than 1 second to start up, otherwise backlight may not be turned on. [Note 3] If driving current waveform is asymmetrical, mercury deviation inside of CFL will incline to one side and consequently abnormal lighting may occur. To prevent such unfavorable lighting, driving current waveform is asked to have unbalance rate of less than 10% and wave-height rate of less than 2 +/- 10%. And this driving waveform shall be confirmed in your system.
Unbalance rate = | Ip - I-p | / IL x 100 (%) Ip Wave-height rate = Ip (or I-p) / IL Ip I-p IL Current waveform : High peak value : Effective value

I-p : Low peak value

[Note 4] The inverter of ground reference type should be used. The inverter of ground floating type should not be used.

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BLOCK DIAGRAM

ASIC TFT Timing Generator (LVDS-Receiver)

DATA

CN1

Source Driver DE 1024 X (RGB) Gate Driver DC/DC Converter

768

VDD VSS

TFT Panel

Back Light Vcom FLCN1 CFL

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INTERFACE PIN CONNECTIONS LCM : CN1
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SYMBOL VDD VDD VSS VSS Rin0Rin0+ VSS Rin1Rin1+ VSS Rin2Rin2+ VSS RCLKRCLK+ VSS NC NC VSS VSS FUNCTION Power Supply ( 3.3V +/- 0.3V ) Power Supply ( 3.3V +/- 0.3V ) Ground Ground Receiver Signal(-) Receiver Signal(+) Ground Receiver Signal(-) Receiver Signal(+) Ground Receiver Signal(-) Receiver Signal(+) Ground Clock Signal(-) Clock Signal(+) Ground No Connection (Should be open during operation.) No Connection (Should be open during operation.) Ground Ground

CN1 : FI-SEB20P-HF13R (JAE) Suitable mating connector: FI-S20S/FI-SE20M/FI-SE20MR (JAE) [Note 1] Internal termination resistors of LVDS input lines are 100 ohms.

Backlight : FLCN1
PIN NO. 1 2 SYMBOL HV LGND FUNCTION High voltage for CFL Low voltage for CFL

FLCN1 : BHSR-02VS-1 (JST) Suitable mating connector: SM02B-BHSS-1 (JST)

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INTERFACE (LVDS) DATA ASSIGNMENT

Rin0 +/-

Rxout 6 GO(LSB)

Rxout 5 R5(MSB)

Rxout 4 R4

Rxout 3 R3

Rxout 2 R2

Rxout 1 R1

Rxout 0 R0(LSB)

Rin1 +/-

Rxout13 B1

Rxout12 B0(LSB)

Rxout11 G5(MSB)

Rxout10 G4

Rxout 9 G3

Rxout 8 G2

Rxout 7 G1

Rin2 +/-

Rxout20 DE

Rxout19 VSYNC

Rxout18 HSYNC

Rxout17 B5(MSB)

Rxout16 B4

Rxout15 B3

Rxout14 B2

RCLK +/-

INTERFACE SIGNALS
SYMBOL DCLK HSYNC VSYNC DE R0 R1 R2 R3 R4 R5 G0 G1 G2 G3 G4 G5 B0 B1 B2 B3 B4 B5 FUNCTION Data Clock Horizontal Sync. (This signal is invalid.) Vertical Sync. (This signal is invalid.) Data Enable (positive) Red Data (LSB) Red Data Red Data Red Data Red Data Red Data (MSB) Green Data (LSB) Green Data Green Data Green Data Green Data Green Data (MSB) Blue Data (LSB) Blue Data Blue Data Blue Data Blue Data Blue Data (MSB)

[Note 1] "DE mode" only. The valid synchronous signals are DCLK and DE. HSYNC and VSYNC are invalid. [Note 2] INTERFACE SIGNALS are loaded from LVDS-transmitter to TFT Timing generator with LVDS sequence. (See BLOCK DIAGRAM.)

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INTERFACE (LVDS) SIGNAL TIMING PARAMETERS
PARAMETER Data Setup Time Data Hold Time SYMBOL tsu thd MIN 600 600 TYP MAX UNIT ps ps NOTE at Tin=15ns Note 1

[Note 1] In the following timing waveform, the n-th edge of internal imaginary clock tcn, which is sampling position of LVDS input data signal, is given by: tcn = (2n-1) Tin / 14 (n=1,2, ~ 7) where Tin is period of LVDS input clock. For this imaginary clock edge, data setup time is tsu and data hold time is thd, respectively. Tin
tcn

LVDS Input Clock
tsu

LVDS Input Data
thd

n-th edge of internal imaginary clock (data sampling position)

CYCLE JITTER of LVDS CLOCK
PARAMETER P-P of jitter / 100 cycles Jitter rate SYMBOL tcj1 tcj2 MIN TYP MAX 300 20 UNIT ps ps/cycle NOTE Note 1

[Note 1] Please confirm tcj2 (Jitter rate), only if tcj1 (P-P of jitter/100cycles) exceeds 300ps. [Additional explanation] Right diagram shows the example of CYCLE JITTER of LVDS CLOCK. According to this diagram, tCLK MIN. is 15.0ns and tCLK MAX. is 15.42ns between 0nc and 100nc. The tcj1 (P-P of jitter / 100 cycles) in this sphere is tcj1=15.42-15.0=0.42 ns and out of specification (300ps MAX.). So, it is neccesary to measure tcj2 (jitter rate) and to judge whether it conform to above specification. According to the diagram, the sharpest fluctuation of tCLK is 0.4ns per 5nc. So that, the tcj2 in this sphere is
15.6 15.5 Period t CLK (ns) 15.4 15.3 15.2 15.1 15.0 14.9 0 50 100 Cycle 150 200 250

<EXAMPLE> CYCLE JITTER of LVDS CLOCK

nc (n)

tcj2=0.4/5=0.08 ns/cycle and larger than specification (20ps/cycle MAX.). In conclusion, normal function of the LCD module can not be assured in this case.

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INTERNAL SIGNAL TIMING PARAMETERS (DE_MODE)
PARAMETER Frequency DCLK Duty Setup Time Hold Time Horiz. Period DE Horiz. DE Vert. Period Vert. DE Setup Time DATA Hold Time SYMBOL fCLK D tSI tHI tHP tHDE tVP nVDE tSD tHD MIN 60.0 (0.40) (3) (1.5) 1270 1024 780 768 (3) (1.5) TYP 65.0 0.50 1344 1024 806 768 MAX 66.6 (0.60) 1450 tHP-12 900 tVP-5 UNIT MHz ns ns tCLK tCLK tHP n ns ns NOTE tCLK=1/fCLK D=tCLKL/tCLK for DCLK

60Hz typical for DCLK

[Note 1] fH (Horizontal Frequency) = 1/tHP fV (Vertical Frequency) = 1/tVP [Note 2] These signal timing parameters are specified at the digital inputs of LVDS transmitter. With respect to setup time and hold time for DE and DATA signals, please refer to input signal specification of LVDS transmitter. Recommended LVDS transmitter : SN75LVDS84 (TI)

INTERNAL SIGNAL TIMING DIAGRAM ( DE_MODE )
tCLK

DCLK

1/2 VDD

tCLKL

tSD

tHD

(Data: Latched at falling edge of DCLK) Invalid Data

Data

Invalid Data
tSI

DE

VIH VIL tHI

tHP tHDE

DE

Shrink
tVP

DE

1

2

----nVDE

n-1

n

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RELATIONSHIP BETWEEN INPUT DATA AND DISPLAY COLOR
INPUT DATA DISPLAY COLOR BLACK RED(63) GREEN(63) BLUE(63) CYAN MAGENTA YELLOW WHITE BLACK RED(1) RED(2) : : RED(61) RED(62) RED(63) BLACK GREEN(1) GREEN(2) : : GREEN(61) GREEN(62) GREEN(63) BLACK BLUE(1) BLUE(2) : : BLUE(61) BLUE(62) BLUE(63) RED DATA GREEN DATA BLUE DATA MSB LSB MSB LSB MSB LSB
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

BASIC COLOR

L H L L L H H H L L L H H H L L L

L H L L L H H H L L L H H H L L L

L H L L L H H H L L L : : H H H L L L : :

L H L L L H H H L L L H H H L L L

L H L L L H H H L L H L H H L L L

L H L L L H H H L H L H L H L L L

L L H L H L H H L L L L L L L L L

L L H L H L H H L L L L L L L L L

L L H L H L H H L L L : : L L L L L L : :

L L H L H L H H L L L L L L L L L

L L H L H L H H L L L L L L L L H

L L H L H L H H L L L L L L L H L

L L L H H H L H L L L L L L L L L

L L L H H H L H L L L L L L L L L

L L L H H H L H L L L : : L L L L L L : :

L L L H H H L H L L L L L L L L L

L L L H H H L H L L L L L L L L L

L L L H H H L H L L L L L L L L L

RED

GREEN

L L L L L L L L L

L L L L L L L L L

L L L L L L : : L L L

L L L L L L L L L

L L L L L L L L L

L L L L L L

H H H L L L

H H H L L L L L L

H H H L L L : : L L L

H H H L L L L L L

L H H L L L L L L

H L H L L L

L L L L L L

L L L L L L

L L L L L L : :

L L L L L L L L L L L H

L L L L H L

BLUE

L L L L L L

L H H H H L H L H H H H H L L H H H H H H

[Note 1] Color(n) --- 'n' indicates gray scale step.

RELATIONSHIP BETWEEN INPUT DATA AND DISPLAY POSITION
1, 1 2, 1 1, 2 . . . . . . . . . . 1, 1023 1, 1024 2, 1024

. . . .

. .

Vp, Hp

R G B

. .

767, 1 768, 1

768, 2

. . . . . . . . . .

767, 1024 768, 1023 768, 1024

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POWER ON/OFF SEQUENCE REQUIREMENT
Power-on
3.0V

Power-off
3.0V 0.3V 15ms < t3 < 200ms 150ms < t5 0 < t4 < 50ms

VDD
0V

0.3V 0 < t1 < 25ms 0 < t2 < 65ms

LVDS input
0V 100ms < t6 ON

VALID DATA

VTH VTL VCM

0ms < t7

CFL
(Recommend)

OFF

When the power is off, LVDS input must be kept at either low level or high impedance.

Power sequence for CFL (backlight) is not specified especially, however it is recommended to consider some timing difference between LVDS input as shown above. If backlight lights on before LCD starts function, or if backlight is kept on after LCD stopped function, screen may look white for a moment or abnormal image may be displayed. This is caused by variation in output signal from timing generator at LVDS input on or off. It does not cause damage to liquid crystal molecule and driving circuit.

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PRECAUTIONS (INSTRUCTIONS FOR SAFE AND PROPER USE) 1. Instructions for safety
(1) Please do not disassemble or modify LCD module to avoid the possibility of electric shock, damage of electronic components, scratch at display surface and invasion of foreign particles. In addition, such activity may result in fire accident due to burning of electronic component. LCD module disassembled or modified by customer is out of warranty. Please be careful in handling of LCD module with broken glass. When the display glass breaks, please pay attention not to injure your fingers. The display surface has the plastic film attached, which prevents dispersion of glass pieces, however touching broken edge will injure your fingers. Also CFL (Cold Cathode Fluorescent Lamp) is made of glass, therefore please pay attention in the same way. Please do not touch the fluid flown out of broken display glass. If the fluid should stick to hand or clothes, wipe off with soap or alcohol immediately and then wash it with water. If the fluid should get in eyes, wash eyes immediately with washing lotion for more than 15 minutes and then consult the doctor. Please make secure connection of CFL connector. Please make sure that CFL connector from LCD module is connected with output connector on inverter circuit securely. Poor connection may cause smoke or fire accident due to high voltage in circuit. If connection may not be secure, please switch off the power supply for LCD module and CFL and then make secure connection. Please do not make connection with another connector than recommended mating connector. CFL contains mercury inside. Please follow regulations or rules established by local autonomy at its disposal. Please be careful to electric shock. Before handling LCD module, please switch off the power supply. Since high voltage is applied to CFL terminal, cable, connector and inverter circuit in operation mode, touching them will cause electric shock.

(2)

(3)

(4)

(5) (6)

2. Instructions for designing
(1) Mounting of LCD Please fix LCD module at all mounting flanges shown in this specification for installation onto system. The used screws should have proper dimensions. Furthermore, designing of mounting parts should be adequate so that LCD module is not putted stresses (ex. warped, twisted and pressed stress), to achieve good display quality. The stresses may cause non-uniformity even if there is no nonuniformity statically. Polarity of power supply for CFL Please give careful consideration in designing so that each polar of cable should be connected correctly at assembling (i.e. high voltage side is connected to high voltage side and low voltage side is connected to low voltage side). Since longer CFL cable may cause insatiable start-up of CFL and reduction of brightness, please make cable short as much as possible.

(2)

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(3)

Designing of power supply circuit for CFL Please design the circuit so that high voltage output can be kept for more than 1 second. The shorter time may not start up CFL. The driving inverter circuit is recommended to be the type which CFL current can be controlled. The type which voltage is controlled is not recommended, because it may cause big current under high temperature and insatiable start-up of CFL under low temperature. Heat radiation CFL generates heat at lighting and causes temperature rise inside system. Therefore, designing to radiate heat like radiation slits at cabinet is recommended to meet the specified operating temperature range for LCD module. Noise on power line Spike noise contained in power line causes abnormal operation of driving circuit and abnormal display. To avoid it, spike noise should be suppressed below VDD +/- 200mVp-p. (In any case, absolute maximum rating should be kept.) Power sequence Before LCD module is switched on, please make sure that power supply and input signals of system, testing equipment, etc. meet the recommended power sequence. Absolute maximum rating Absolute maximum rating specified in this specification has to be kept in any case. It shows the maximum that cannot be exceeded. Exceeding it may cause burning or non-recoverable break of electronic components in circuit. Please make system design so that absolute maximum rating is not exceeded even if ambient temperature, input signal and components are varied. Protection for power supply Please study to adapt protection for power supply against trouble of LCD module, depending on usage condition of system. Fuse installed on LCD module should be never modified. Any modification to make the function of fuse ineffective may cause burning or break of printed wiring board or other components at circuit trouble. Protection against electric shock High voltage is applied to CFL connector, inverter circuit and CFL at lighting. Please make design not to expose or be accessible to such high voltage parts to avoid electric shock.

(4)

(5)

(6)

(7)

(8)

(9)

(10) Protection cover and cut-off filter for ultraviolet rays When LCD module is used under severe condition like outdoor, it is recommended to use transparent protection cover over display surface to avoid scratches and invasion of dust and water. In addition, when LCD module is exposed to direct sun light for long time, use of cut-off filter for ultraviolet rays is also recommended. Please be careful not to get condensation.

3. Instructions for use and handling
(1) Protection against Static electricity C-MOS LSI and semiconductors are easily damaged by static discharge. LCD module should be handled on conductive mat by person grounded with wrist strap etc. to avoid getting static electricity. Please be careful not to generate static electricity during operation.

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(2)

Protection against dust and stain LCD module should be handled in circumstance as clean as possible. It is recommended to wear fingerstalls or ductless and soft gloves before handling to avoid getting dust or stain on display surface. Protection film for display surface It is recommended to remove protection film at nearly final process of assembling to avoid getting scratch or dust. To remove film, please pick up its edge with dullhead tweezers or cellophane tape at first and then remove film gradually taking more than 3 seconds. If film is removed quickly, static electricity may be generated and may damage semiconductors or electronic components. Contamination of display surface When display surface of LCD module is contaminated, please wipe the surface softly with cotton swab or clean cloth. If it is not enough, please take it away with cellophane tape or wipe the surface with cotton swab or clean cloth containing benzine. In this case, please be careful so that benzine does not get in inside of LCD module, because it may be damaged. Water drop on LCD surface Please do not leave LCD module with water drop. When the display surface gets water drop, please wipe it off with cotton swab or soft cloth immediately, otherwise display surface will be deteriorated. If water gets in inside of LCD module, circuit may be damaged. Please make sure that LCD module is not warped or twisted at installation into system. Even temporary warp or twist may be the cause for failure. Mechanical stress Please be careful not to apply strong mechanical stress like drop or shock to LCD module. Such stress may cause break of display glass and CFL or may be the cause for failure. Pressure to display surface Please be careful not to apply strong pressure to display surface. Such pressure may cause scratches at surface or may be the cause of failure. Protection against scratch Please be careful not to hit, press or rub the display surface with hard material like tools. In addition, please do not put heavy or hard material on display surface, and do not stack LCD modules. Polarizer at front surface can be easily scratched.

(3)

(4)

(5)

(6) (7)

(8)

(9)

(10) Plugging in of connector Please be careful not to apply strong stress to connector part of LCD module at plugging in or out, because strong stress may damage the inside connection. At plugging in connector, place LCD module on the flat surface and hold the backside of connector on LCD module. Please make sure that connector is plugged in correctly. Insecure connection may be the cause for failure during operation. In addition, please be careful not to put the connecting cable between cabinet of system and LCD module at installing LCD module into system. (11) Handling of CFL cable and FPC (Flexible Printed Circuit) Please be careful not to pull or scratch CFL cable, because CFL or soldered part of cable may be damaged consequently. Also FPC should not be pulled or scratched. (12) Switching off before plugging in connector Please make sure that power is switched off before plugging in connector. If power is on at plugging in or out, circuit of LCD module may be damaged. When LCD is switched on for test or inspection, please make sure that power supply and input signals of driving system meet the specified power sequence.

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(13) Temperature dependence of LCD display Response speed (optical response) of LCD display is dependent on temperature. Under low temperature, response speed is slower. Also brightness and chromaticity change slightly depending on temperature. (14) Slow light-up and life time of CFL under low temperature Under low temperature, start-up of CFL gets difficult. (The time from switch-on to stable lighting becomes longer.) As characteristic of CFL, operation under low temperature makes the life time shorter. To avoid this, it is recommended to operate under normal temperature. (15) Condensation LCD module may get condensation on its display surface and inside in the circumstance where temperature changes much in short time. Condensation can cause deterioration or failure. Therefore, please be careful not to get condensation. (16) Remaining of image Displaying the same pattern for long time may cause remaining of image even after changing the pattern. This is not failure but will disappear with time.

4. Instructions for storage and transportation
(1) Storage Please store LCD module in the dark place of room temperature and low humidity in original packing condition, to avoid condensation that may cause failure. Since sudden temperature change may cause condensation, please store in circumstance of stable temperature. Stacking number Since excessive weight causes deformation and damage of carton box, please stack only up to the number stated on carton box for storage and transportation. Handling Since LCD module consists of glass and precise electronic components, it will be damaged by excessive shock and drop. Therefore, please handle the carton box carefully to minimize shock at loading, reloading and transportation.

(2)

(3)

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Outer Dimensions (FRONT SIDE)

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