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High-Efficiency Power Conversion for Renewable Energy and Distribution Generation

November 2, 2009 Presentation at PEDS 2009 Taipei, Taiwan Professor Jih-Sheng (Jason) Lai Future Energy Electronics Center Virginia Polytechnic Institute and State University 106 Plantation Road Blacksburg, VA 24061-0356 WWW.FEEC.ECE.VT.EDU

JSL

1

Outline

Part A – High Efficiency DC-DC Converters

1. High-Efficiency Low-Ripple Isolated DC-DC Converter 2. Energy Management Using Bidirectional DC/DC Converter

3. High Boost Ratio DC-DC Converters

Part B – High Efficiency Inverters

1. Half-Cycle Asymmetrical Unipolar PWM 2. Single-Stage Power Conversion 3. 4. 5. 6. Dual Buck Converters H5 Inverter Isolated Single-Stage Design Soft-Switching Inverters

Part C – Energy Efficiency Standards

JSL

2

Outline – Part A

Part A – High Efficiency DC-DC Converters

1. High-Efficiency Low-Ripple Isolated DC-DC Converter 2. Energy Management Using Bidirectional DC/DC Converter

3. High Boost Ratio DC-DC Converters

Part B – High Efficiency Inverters

1. 2. 3. 4. 5. Half-Cycle Asymmetrical Unipolar PWM Single-Stage Power Conversion Dual Buck Converters H5 Inverter Isolated Single-Stage Design

6. Soft-Switching Inverters

Part C – Energy Efficiency Standards

JSL

3

Outline – Part A-1

Part A – High Efficiency DC-DC Converters

1. High-Efficiency Low-Ripple Isolated DC-DC Converter 2. Energy Management Using Bidirectional DC/DC Converter

3. High Boost Ratio DC-DC Converters

Part B – High Efficiency Inverters

1. 2. 3. 4. Half-Cycle Asymmetrical Unipolar PWM Single-Stage Power Conversion Dual Buck Converters H5 Inverter

5. Isolated Single-Stage Design 6. Soft-Switching Inverters

Part C – Energy Efficiency Standards

JSL

4

Why Single-Switch DC-DC Converters are Inefficient?

? Forward: <50% ? Flyback: <50% ? Half-bridge: 100% ? Push-pull: 100% ? Full-bridge: 100%

iM 0

iM-pk Magnetizing current iM t B NiM-pk H –NiM-pk 0

iM-pk t B NiM-pk H

JSL

Core is half utilized

Core is fully utilized

5

Half-Bridge DC/DC Converter

20V >250A M1 + Vin – M2 ? ? ? ? ? a b C2

D6 D8

10V >500A C1 i1 1 : n

iL L i2 D 5 D 7 vd

C

400V 5 kW

+ R vo –

JSL

Low device count Low voltage device Device sees twice current Unbalance due to split capacitors High leakage due to twice transformer turns ratio

6

Push-Pull DC/DC Converter 400V

20V >250A 40V a 1:1:n i2 D 5 D 7

iL L

5 kW

+

vd

+ M Vin 1 – M2 b

D6 D8

C

R

vo –

+ Simple non-isolated gate drives + Suitable for low-voltage low-power applications – Device sees twice input voltage – need high voltage MOSFET

? High conduction voltage drop, low efficiency

– Center-tapped transformer

? Difficult to make low-voltage high-current terminations ? Prone to volt-second unbalance (saturation)

JSL

7

Full-Bridge DC/DC Converter

20V >250A M1 + Vin – M2 M4 a b

D6 D8

20V >250A M3 i1 1 : n

iL L i2 D 5 D 7 vd

C

400V 5 kW

+ R vo –

? Most popular circuit today for high-power applications

? Soft switching possible ? Reasonable device voltage ratings

JSL

? High component count from the look ? High conduction losses

8

Device Voltage and Current Stresses

? Device voltage stress

? Push-pull: 200% ? Half-bridge: 100% ? Full-bridge: 100%

? Device current stress

? Half-bridge: 200% ? Push-pull: 100% ? Full-bridge: 100%

? Output diode voltage stress

? Center tap: 200% ? Full-bridge: 100%

JSL

9

Ripple Currents with Full-Bridge Converters

15A 5A -5A -15A I(Ld3) 150A 100A 50A SEL>> -50A I(Cin) 60A 40A 20A -I(Vfc) 30V 20V 10V 0s V(Vfc)

JSL

V(Iac)

Filter inductor current AC load current 330% Input capacitor current 33%

Source current Load step Source voltage

2ms 4ms Time 6ms

Load dump

8ms

10ms

10

Switching Waveforms with Full-Bridge Converter

100A 50A 0A -50A -100A I(Cin) 40V 30V 20V 10V 0V -10V

150 A Ripple frequency = 100 kHz

Zero-voltage switching is achieved

V(M1:d)-V(M1:s) V(M1:g)-V(M1:s) 100A 75A 50A 25A SEL>> -25A 4.998ms 5.000ms 5.002ms 5.004ms 5.006ms 5.008ms 5.010ms I(M1:d) I(M3:d) Time

JSL

11

A Three-Phase Bridge Converter

Fuel Cell or other voltage source

20V >167A

S1 + Cf A S3 iA B

n

S5 1 :n –i C

L iL D1 ia b c D4 D6 D2 Co vo – D3 a D5 + Active Load

12

vin –

C S4 S6 S2 HF AC Xformer

3-phase bridge inverter

Rectifier+LC filter

JSL

? Hard switching ? With 4 devices in parallel per switch ? Efficiency ? 95%

Source Voltage and Current with 3-Phase Bridge Converter Case

15A 5A -5A -15A I(Ld3) 150A 100A 50A 0A -50A V(Iac)

Filter inductor current AC load current 80%

A significant reduction in capacitor ripple current Input capacitor current I(Cin) No reduction in low-freq. source ripple current 33%

-I(Vfc)

60A

SEL>> 20A

Source current Load step Source voltage

Load dump

30V 20V 10V 0s

JSL

5ms V(Vfc) Time

10ms

13

Switching Waveforms with 3-Phase Bridge Converter

50A 25A 0A SEL>> -50A I(Cin) 40V 30V 20V 10V 0V -10V

35 A Ripple frequency = 300 kHz

Zero-voltage switching is achieved

V(M1:d)-V(M1:s) V(M1:g)-V(M1:s) 100A 75A 50A 25A 0A -25A 4.998ms 5.000ms 5.002ms 5.004ms 5.006ms 5.008ms 5.010ms I(M1:d) I(M4:d) Time

JSL

14

Further Expansion to Six-Phase Bridge (V6) Converter

20V >83A

HF AC Xformer Six-phase bridge converter

JSL

Rectifier+LC filter

15

Key Feature of V6 DC-DC Converter

? Soft switching with zero-current turn-on and lagging leg zero-voltage turn-on (ZCZVS) ? High efficiency operation over a wide load range with a peak efficiency of 98% ? Double output voltage with transformer connected in open ?-Y connection ? reduce turns ratio and associated leakage inductance ? Interleaved multiple phase operation to eliminate input high-frequency current ripple ? cost and size reduction on input capacitor Cin ? Output DC link inductor Lo current ripple elimination ? cost and size reduction on inductor ? Low-frequency (single-phase inverter load) ripple reduction with active dual-loop control ? better utilization of source energy and size and cost reduction on input capacitor Cin

99% 98% 97% C 96% 95% 94% 93% B 92% 91% A 0

Efficiency

Commercial transformer

Home-made transformer

1

2

3

4

5

6

Input Power (W)

JSL

A. Vin = 25 V using custom-made commercial transformer B. Vin = 50 V using custom-made commercial transformer C. Vin = 50 V using in-house developed transformer

16

Active Load

Source

Waveform Comparison between Full-Bridge and V6 Converters

Full Bridge Converter V6 Converter

vd iL vd iL

? Secondary inductor current is ripple-less; and in principle, no dc link inductor is needed ? Secondary voltage swing is eliminated with <40% voltage overshoot as compared to 250%

JSL

17

Low-Frequency AC Current Ripple Problems

120Hz 120Hz + DC-DC converter Vdc S ap A High-side cap. S an Sbp AC filter LC Cf Lf + 60Hz

Fuel Cell

B

R

Vo

–

Sbn

–

? Inverter AC current ripple propagates back to fuel cell ? Fuel cell requires a higher current handling capability ? Cost penalty to fuel cell stack ? Ripple current can cause hysteresis losses and subsequently more fuel consumption ? Cost penalty to fuel consumption ? State-of-the-art solutions are adding more capacitors or adding an external active filters ? Size and cost penalty ? The solution without cost penalty is to use existing V6 converter with active ripple cancellation technique to eliminate the ripple ? No penalty JSL

18

Active Ripple Cancellation Technique

Adding a current loop to regulate the output current

Gvc vref Rv1 vsense + – Cv1 Rv2 Cv2 isense iref Ri1 Gic + – Ci1 Ri2 Ci2 Hi Hv

vin (10V/div) 20V avg iin (20A/div) 168A avg iL (10A/div) iac (20A/div) 12.7A rms

JSL

Vd = dVin d + – PWM + Vd –

Lf iLf R cf Cf + RL Vo

Vm

?

vin (10V/div) 20V avg iin (20A/div) 162A avg iL (10A/div) iac (20A/div) 12.7A rms (b) With ripple reduction

19

(a) Without ripple reduction

2. Energy Management Using Bidirectional DC/DC Converter

DC Bus Fuel Cell, PV, or HV Battery DC/DC converter

Inverter

Load

Iac Vbatt

Vac

Vdc

feedbacks

Bidirectional dc/dc converter LV battery or super capacitor

JSL

? Low voltage battery or super capacitor controlling DC bus through a bidirectional dc/dc converter. ? The main application is to help start-up and transient conditions for EV, HEV, fuel cell PCS, etc.

20

Circuit Diagram of a 4-Phase Bidirectional DCDC Converter with Coupled Inductors

S1u L12 S2u S3u S4u

i1 ? =0° 1 i2 ?2=180° i3 i4 S1d S2d S3d

L34 Vlow Clow

?3=90°

S4d

Chigh

?4=270°

Vhigh

? ? ?

JSL

Multiphase interleaved to reduce input and output capacitor current ripples Coupled inductors effectively increase the inductance or reduce the core size Hard or soft switching can be configured depending on inductor size and switching frequency

21

Timing Diagram of 4-Phase Bidirectional DC-DC Converter

D complementary complementary S1u S1d S2u S2d S3u S3d S4u S4d Ts/2 Ts Ts/4 180° 180° 90° D’

complementary complementary

JSL

1.5 kW, 24-48V

50 kW 200-400 V

22

Test Setup of a 1.5-kW Bidirectional DC-DC Converter Using Ultra-capacitor and ABC-150

I1

Ultracapacitor + V1 Pack Bidirectional DC/DC Converter

I2 + V2 –

ABC-150 Channel 2 Voltage Mode

–

36 V

48 V

Test Computer (PC)

Screw Terminal Connector Block Data Acquisition Card (NIDAQ) Remote Operating System

JSL

? Both channels alternate between sinking and sourcing current ? The magnitude of the current is based off of the power command given to the converter.

23

Boost Mode : 1.5-kW Output Power

Input Voltage 36-V

Output Voltage

Output Voltage 48-V Phase Current 10.42-A Command 1.5-kW Input Current 41.67-A

Input Voltage

Input Current

JSL

24

Experimental Results of Bidirectional Charging Mode Transition Operation

In/Out Voltages Output Current Output Current In/Out Voltages

Command

Command

Input Current

Input Current

JSL

25

Continuous and Discontinuous Conducting Modes (CCM and DCM)

? CCM operation

iL Iavg

Vhigh ? Vlow Ipk Vlow L L

Vhigh ? Vlow

iL Iavg

? DCM operation

Ipk+

L

Vlow L

DTs

D’Ts

t

D1Ts D2Ts D3Ts

t

L?

Ts 2 T D ' R ? s (1 ? D ) 2 R 2 2

L?

Ts 2 T D2 R ? s (1 ? D1 ) 2 R 2 2

CCM occurs with ? Larger inductance L ? Smaller R (heavy load) ? Higher switching frequency

JSL

DCM occurs with ? Smaller inductance L ? Larger R (heavy load) ? Lower switching frequency

26

CCM-DCM Boundary Mode and Synchronous Conducting Mode (SCM)

? CCM-DCM Boundary operation ? SCM operation

iL Iavg

Vhigh ? Vlow Ipk Vlow L L

Iavg DTs D’Ts t

Vhigh ? Vlow

iL

Ipk+

L

Vlow L

I pk ? pk ?

Vlow ? Vlow ? ?1 ? ? ?Ts L ? V hi ? ?

Ipk–

t

I pk ? ?

P Vlow ? Vlow ? ?1 ? ? ? ?Ts Vlow 2 L ? V hi ? ?

DCM-CCM features ? Device turns on at zero current ? Device turns off at twice the average load current ? Applicable to any dc-dc converters

JSL

SCM features ? Device turns on at zero voltage ? Device turns off at a current higher than twice the average ? Only applicable to bidirectional dc-dc converters

27

Simulated SCM Operated Voltage and Current Waveforms at 50 kHz Switching

vds 400V vgs 40 40V 2 400

30V 30 20V 20 10V 10 0V 0 10V –10 20V –20 300V 300 200V 200 100V 100 0V 0 –100 >> -200V –200 70A 70 60A 50A 50 40A 30A 30 20A 10A

Vgs1-d=15V

ZVS

1 V(M17:g) 2

Vds1-d=280V

V(M17:d)

iL-all=57A average 16A pk-pk

iL3

iL2

iL4

iL1: 40 A pk-pk

10

SEL>> -10A –10 9.95ms 9.96ms 9.97ms 9.98ms 9.99ms 10.00ms 0 10 -I(RLa) 20 -I(RLb) 30 -I(RLc) 40 I(RLa)-I(RLb)-I(RLc)-I(RLd) -I(RLd) 50 Time (?s) Time

JSL

28

Experimental SCM Operated Voltage and Current Waveforms at 50 kHz Switching

vgs-1d vds-1d +15V –5V ZVS D’Ts DTs 16A pk-pk iL4 280V

iL-all=57A average iL1 iL3 iL2

?iL: 40 A pk-pk

Time (5?s/div)

JSL

29

Multiphase Bidirectional DC-DC Converter with Coupled Inductor and SCM Operation

? Similar to DCM operation, SCM has a high peak-to-peak inductor current. ? With multiphase interleaved, the current ripples cancel each other, and the total current can be significantly reduced. ? Device can switch at true zero voltage conduction, thus it is better to use power MOSFET as the switching device. ? Turn-off loss can be reduced with a paralleled capacitor (resonant capacitor) across the device. ? Coupled inductor allows core loss reduction and increases equivalent inductance. ? Overall efficiency can be very high with proper design of inductor and selection of device.

JSL

30

Efficiency of Bidirectional DC-DC Converter Operating in Synchronous Conduction Mode

100.0%

Vlow = 240V, Vhigh = 400V With 20-kHz frequency

Efficiency (%)

99.5% 99.0% 98.5% 98.0% 97.5% 97.0% 0 5

With 22-kHz frequency

10 15 20 25 30 35 40 45 50

Power (kW)

? Use two identical 4-phase converters with regenerative connection to measure losses ? One converter operates in buck mode, and the other operates in boost mode ? The total supply power is the loss of two converters, but the output voltage and current are actual load condition. ? Measured peak efficiency exceeds 99.1% at 20 kHz switching.

JSL

31

Possible Efficiency Improvement with Variable Frequency Control

100

Efficiency (%)

99 98 97 96 95 0

? If high efficiency at light load is desired, it is possible to vary 50kHz 40kHz 30kHz 20kHz 18kHz the switching frequency. ? High frequency at light load allows much reduced peak current, thus increasing the efficiency. ? Experimental results showed that 5 10 15 20 25 30 >99.2% at 50 kHz Power (W) switching was achieved.

32

JSL

3. High Voltage Conversion Ratio Reboost Converters

1:n Vin + ? L g Q1 D1 + V1 ? Vin + ? g + V2 ?

? ? ?

1:n L

D1 C1 D2 C2

Vo 1 ? n ? D ? Vin 1? D

C

+

Flyback

Q1

Vo=VC1+VC2

L Vin + ? g

d Q1 s

Boost

D2 C

?

JSL

Non-isolated output with high boost ratio Suitable for low input voltages such as fuel cells and solar cells Significant reduction on switch voltage stress

33

Reboost Converter Operating Modes

1:n LM + ? g Llk1 Q1 D2 C2 D1 Llk2 + Co Vo ?

LM + ? g Llk1 Q1 1:n D1 Llk2 D2 C2 + C Vin o + Vo ? ?

1:n LM Llk1 Q1 g D2

D1 Llk2 LM Llk1 Q1 g

1:n

D1 Llk2

Vin

Vin

+ CoVin + Vo ? ?

D2 C2

+ Co Vo ?

C2

(a)

(b)

(c)

(d)

(a) Initially, Q1 is off, magnetizing inductor current continues circulating to supply the secondary current. The boost capacitor C2 is discharging to output capacitor Co through diode D1 and Llk2. D2 is off. Vo = VC2+n·VLM. VLk2 = n·VLM = n·Vin. Current in Llk1 reflects the current in Llk2. (b) Switch Q1 turns on. With reverse biasing, current in D1 starts reducing. Lm is charged. Voltage across Llk2 is VLk2 = n·VLM = Vo–VC2. Since VLM = Vin, VLk2 = nVin. (c) Current in D1 drops to 0. For non-ideal diodes, there will be a reverse recovery period. Capacitor Co has been charged by sum of voltage across Llk2 and C2. Vo=VC2+nVin. Device Q1 is fully turned on, and Lm current is increasing. (d) Switch turns off, diode D2 is turned on, and C2 gets charged. After C2 is fully charged, diode D2 will be turned off. Current in Lk2 starts increasing until it reaches steady state.

JSL

34

Derivation of Voltage Conversion Ratio for the Reboost Converter

? Assume capacitors are large enough that their voltage maintains constant during steady-state operation. Also assume the transformer windings are perfectly coupled. ? During off period (Mode-a and Mode-d), V·s of Lk2 is D’·VLk2. With V·s balance, D’·VLk2= n·D·Vin. Thus VLk2 = n·D·Vin/D’, and VC2 = Vin/D’. ? During on period (Mode-c), Vo = VC2 + nVin. With constant VC2,

D ? ? 1 ? nD ? ? 1 Vo ? VC 2 ? VLk 2 ? Vin ? ? n ? ? ? ?Vin D' ? ? D' ? ? D'

The voltage conversion ratio becomes

Vo 1 ? nD ? Vin 1 ? D

Actual voltage conversion ratio will be slightly lower with non-perfectly coupled transformer.

JSL

35

Voltage Conversion Ratio of Reboost DC-DC Converter

40

n=8

Voltage conversion ratio

35 30 25 20 15 10 5 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8

n=4 n=2

Reboost cases

Boost converter case

Duty cycle

JSL

36

Further Derivation – Recharged Boost Converter L1 Vin D2 C2 C1 D2 C2 L2 D 1 + Co

Vo ?

(a) Reboost converter: ? Treat flyback as coupledinductor converter

+ ?

Q1 g

1? n ? D Vin 1? D

1:n L Vin + ? g

D1

+ C1 D2 C2

? L2 D3 D1

Q1

?

L1 Vin

+ ?

Q1 g

Co

(b) Recharged-boost converter: ? Add D3 and C1. ? when Q1 turns on, C1 is + charged through D3 and L2. 2?n Vin Vo ? 1? D

?

37

JSL

Basic Operating Principle of Recharge-Boost Converter

(a) Initially, Q1 is off, magnetizing inductor current charges boost capacitor C2 through diode D2 and output capacitor Co through C1, L2, and D1. D3 is off. Vo = Vin+VLm+VC1+n·VLm. VC2 = Vin+VLm. VL2 = n·VLm. Current in L1 reflects the current in L2. (b) Switch Q1 turns on. D2 is turned off. Lm is charged. Voltage across L2 is VL2 = n·VLm = Vo–VC1. Since VLm = Vin, VL2 = nVin. With reverse biasing, current in D1 starts reducing. (c) Current in D1 drops to 0. For non-ideal diodes, there will be a reverse recovery period. Capacitor C1 is charged by sum of voltage across L2 and C2. VC1=VC2+nVin. Device Q1 is fully turned on, and Lm current is increasing. (d) Switch turns off, diode D2 is turned on, and C2 gets charged with VC2=Vin+VLm. D3 is now reverse-biased, and its current starts reducing. Current in L2 starts reversing until it reaches 0. There will be a reverse recovery period due to non-ideal D3. After that, the mode returns to Mode (a).

Lk 1 Vin + ? Lm L1 ? C1 + Q1 D2 1:n Lk 2 L2 D1 + V in

Lk1 Lm L1 + ? Q1 ? C1+ D2 1:n Lk2 L2 D1 +

Lk1 Vin Lm L1 + ? Q1 ?

1:n Lk2 L2 D3 C2

D1 +V Co Vo ?

Lk1 Lm L1 + ? Q1 ?

1:n Lk2 L2 D3 C2

D1 + Co Vo ?

D 3 C o Vo ? C2

D 3 C o Vo C2 ?

C 1+ D2

in

C 1+

D2

(a)

JSL

(b)

(c)

(d)

38

Derivation of Voltage Conversion Ratio

? Assume capacitors are large enough that their voltage maintains constant during steady-state operation. Also assume the transformer windings are perfectly coupled. ? During off period (Mode-a and Mode-d), V·s of L2 is D’·VL2. With V·s balance, D’·VL2 = n·D·Vin. Thus VL2 = n·D·Vin/D’, and VLm = D·Vin/D’ ? VC2 = Vin + D·Vin/D’ = (1+D/D’)Vin = Vin/D’. ? During on period (Mode-c), VC1 = VC2 + nVin. With constant VC2, VC1 = (1/D’+n)Vin. ? Again with VC1 being constant, under Mode-a condition, we have

D? n ? 1 ? 2 ? 1 Vo ? VC 2 ? VC1 ? VL 2 ? Vin ? ? ( ? n ) ? n ? ? Vin ? ? ? D' ? ? D' D' ? ? D' D'

Lk1 1:n L1 C1 ? + Q1 D2 D3 C2 Lk2 L2 Co D1 + Vo ?

boost

recharge

flyback

Vin + ?

Lm

The voltage conversion ratio becomes

Vo 2 ? n ? Vin 1 ? D

Actual voltage conversion ratio will be slightly lower with non-perfectly JSL coupled transformer.

39

Voltage Conversion of Recharged Boost Converter

50 45 40 35 30 25 20 15 10 5 0 0.2 0.3 0.4 0.5 0.6 Duty cycle 0.7 0.8

Recharge boost case with n=8 Reboost case with n=8 Recharge boost case with n=4 Reboost case with n=4 Recharge boost case with n=2 Reboost case with n=2 Boost converter case

JSL

Voltage conversion ratio

40

Key Voltage and Current Waveforms of RechargedBoost Converter

Lk1 Lm + ? Q1 L1 C1 ? + D2 D3 C2 1:n Lk2 L2 Co D1 + Vo ?

V V V >> V V(TX1:1)-V(TX1:2) A A A A I(D3) V V V

VL2 VL1 ID3

V(TX1:4)-V(TX1:3)

Vin

ID1

I(D1)

Vo Vc1

V(Vc) V c2 V(Vo)

? Slow turn-off of D1 and D3 shows problem of reverse recovery (SiC Schottky diodes may be used). ? With limited duty cycle range, C2 voltage can be limited, and Si Schottky can be used for D2. ? With large enough capacitors, voltages of capacitors are flat during JSL steady-state operation.

V(Vy)-V(Vx) V V V V V(M1:g) A A A A 5.980ms

VQ1

Vgs

V(M1:d)

IL1 IL2

5.984ms

ILm

5.988ms

5.991ms

41

Design Examples with High Boost Ratio DC-DC Converters

Boost converter Inverter

? Boost converter ? Reboost converter ? Recharge boost converter

PV array

L1 D1 Q1

filter

L1 Vin D2 C2

L2 D1 + Co ?

Vin

L1

C1 D2 C2

L2 D3

D1 + Co ?

42

+ ?

Q1 g

+ ?

Q1 g

JSL

Reboost converter

Recharge boost converter

Voltage Conversion Ratio and Duty Cycle Constraint

? ? ? ? At 10V, Gv = 200/10 = 20, at 20V, Gv = 10 At 60V, Gv = 200/60 = 3.33, 70V, Gv = 200/70 = 2.86 Assume duty cycle is limited to between 0.1 and 0.9 For boost converter case, D at 10 V needs to be 0.95 (difficult to implement) ? The reboost converter with n = 8 case has the best suitable duty cycle range for the wide input voltage range case. ? For recharge-boost converter with n = 0.58 case, D at 70V needs to be 0.10, not effective utilization of the switch. Duty cycle at different PV voltages

PV input Boost Reboost (n = 8) Recharge boost (n = 0.58)

JSL

70 V 0.65 0.17 0.10

60 V 0.70 0.22 0.21

20 V 0.90 0.50 0.742

10 V 0.95 0.68 0.87

43

Duty Cycle Comparison Between Boost and Reboost, and Recharge-Boost Converters

20 18 16 14 12 10 8 6 4 2 0 0

Voltage gain

recharge boost with n = 0.58 reboost with n = 8

boost converter

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Duty ? Boost needs to be excluded Duty cycle range due to duty cycle constraint. Boost: 0.65 at 70 V to 0.95 at 10 V ? Recharge boost works in Reboost: 0.17 at 70 V to 0.68 at 10 V theory, but fails in actual Recharge boost: 0.10 at 70 V to 0.87 at 10 V implementation at 10 V.

JSL

44

Switch Q1 Voltage Stresses

L1 Vin D2 C2 L2 D1 + Co

+ ?

Q1 g

Vo

?

Q1 voltage stress is the voltage across C2 and can be calculated as the boost converter output. 1 VC 2 ? Vin 1? D a. For boost case, At 10 V input, D = 0.95, VC2 = 200 V, At 70 V input, D = 0.21, VC2 = 200 V, b. For reboost case with n = 8, At 10 V input, D = 0.68, VC2 = 31 V, At 70 V input, D = 0.17, VC2 = 84 V, c. For recharge boost case with n = 0.6, At 10 V input, D = 0.87, VC2 = 78 V, At 70 V input, D = 0.10, VC2 = 78 V,

L1 Vin

C1 D2 C2

L2 D3

D1 + Co

+ ?

Q1 g

Vo

?

? Both reboost and recharge-boost can be designed to maintain the voltage stress of C2 to below 100 V.

JSL

45

Turns Ratio versus Voltage Stress for the Reboost Case

? Higher turns ratio, less voltage stress on switch, clamping diode, and clamping capacitor, but higher voltage stress on output diode and more transformer leakage inductance. ? Assume Vo = 200 V, Vin_max = 70 V, and Vclamp_max = Vin_max/(1 – D) = 85 V

Vo 1 ? nD ? Vin 1 ? D

Vo ? nD 1 1? D 1 Vin ? Vin ? Vclamp ? n Vin ? n Vin ? Vclamp ? nVin ? nVclamp 1? D 1? D 1? D 1? D Vclamp Vo ? ? 7.66 n? Vclamp ? Vin Vclamp ? Vin

?

JSL

Assume output diode D1 stress is limited to 700 V Vd 1 ? Vo ? Vclamp n? ? 8.36 Vd 1 ? Vo ? Vclamp ? nVin Vin Therefore, n = 8 should allow reasonable device voltage stress (85 V) and clamping diode voltage stress (700 V).

46

Simulation results of Voltage stress

(a) Switch voltage

(b) Output diode voltage

? With turns ratio n = 8, Vin = 70 V, Vo = 200 V, simulation results agree with the calculated voltage stress of active device and output diode. ? Device voltage has small overshoot during turn-off. Additional margin is needed.

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47

Simulated Voltages and Device Current at 70-V Input, 100-kHz Switching

50A 25A 0A I(M1:d) 100V 50V 0V V(M1:d) 200V SEL>> 0V

19 A

Device current

I(M1:d)

44 A

85 V

Device voltage >

V(M1:d)

80 V

Output voltage 200 V

0

1

85 V 2 3 Time (?s) (a) Reboost

C2 voltage 4 5 0

80 V 1 2 3 Time (?s) (b) Recharge boost

4

5

? ?

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Simulation results match the calculated results Device voltage stress is nearly the same, but the current stress in recharge boost is much higher due to smaller duty cycle

48

Diode Current Stresses for Reboost Converter

? Assume capacitors and 35 IQ1 magnetizing inductance are large 25 ID2 enough that capacitor voltages 15 and magnetizing current maintain 5 –5 constant throughout the entire I(M1: ) I(D2) I(Cc) Id C2 steady-state cycle. 4 ? Average output current Io = 2 ID1 Po/Vo = 300/200 = 1.5 A 0 ? At 20-V input, the average input –2 I(D1) current Iin = 300/20 = 15 A ? With duty cycle D = 0.5, the ILM 30 primary switch current is IQ1 = 20 ILk1 Iin/D = 22.5 A. 10 0 ? The output diode current during 0 2 4 6 8 10 switch turn-off period is ID1 = Time (?s) Io/D’ = 3 A. ? Diode D2 conducts when the switch is turned off but only in a very short period to charge the capacitor C2. The peak current of D2 is the peak switch current, or ID2-peak = Isw-peak, but the average ID2 is very small.

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49

Two Phases Interleaved Recharge Boost Converter L11 Vin + Ci ? Q1 C r1 Dc 1 Cc 1 L21 Q2 C r2 Dc 2 Cc 2 L22 D r2 Do 2 L12 D r1 Do 1 + Co Vo ?

JSL

? Multiphase interleaved operation allows ripple reduction ? Current sharing among phases is good for high power applications

50

Two-phase Interleaved Recharge Boost Converter with Cross Coupling

L11 Vin + Ci ? Q1 C r1 Dc 1 Cc 1 L21 C r2 Dc 2 Q2 Cc 2 L22 L13 D r2 Do 2 L12 L23 D r1 Co Do 1 + Vo ?

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? Cross coupling helps balance equal current sharing

51

Summary of State-of-the-Art High Boost Ratio DC-DC Converters

? ? Conventional boost converter simply cannot be considered as a high boost ratio converter. Reboost converter: ? Requires high turns ratio for high boost ratio and low device voltage stress. ? High turns ratio tends to increase output diode voltage stress and lower device utilization. Recharge boost converter: ? Super high boost ratio with low turns ratio ? Relatively low device voltage stress ? Difficulty to operate in a wide range input voltage due to duty cycle constraint at low input voltages ? High peak current stress on switch when operating at high input voltage where duty cycle is low

?

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52

Charge Pump Reboost Converter

L1 Vin C1 D2 C2 L2

? A new improved high boost ratio dc-dc converter is proposed using charge + D3 pump idea Co 2?n Vo ? Vin ? Voltage boost ratio is 1? D reduced to allow a wider input voltage range while ? maintaining reasonable voltage stresses on devices L2 D1 ? Direct charge pump allows L2 current to be regulated + to avoid low-frequency D3 ripple propagation back to Co V o the source

D1

+ ?

Q1 g

L1 Vin

C1 D2

+ ?

Q1 g C2

? Vo ? 2 ? nD Vin

1? D

53

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Basic Operation of the Charge Pump Reboost Converter

(a) Initially, Q1 is off, magnetizing inductor current charges output capacitor Co through C1, L2, and D1. D2 and D3 are off. Vo = Vin+VLm+VC1+n·VLm. VC2 = Vin+VLm. VL2 = n·VLm. Current in L1 reflects the current in L2. (b) Switch Q1 turns on. D2 is turned off. Lm is charged. Voltage across L2 is VL2 = n·VLm = Vo–VC1. Since VLm = Vin, VL2 = nVin. With reverse biasing, current in D1 starts reducing. (c) Current in D1 drops to 0. For non-ideal diodes, there will be a reverse recovery period. Capacitor C1 is charged by C2, so VC1=VC2. Device Q1 is fully turned on, and Lm current is increasing. (d) Switch turns off, diode D2 is turned on, and C2 gets charged with VC2=Vin+VLm. D3 is now reverse-biased, and its current starts reducing. There will be a reverse recovery period due to non-ideal D3. After C2 is fully charged, the mode returns to Mode (a).

Lk1 Vin + ? Lm L1 ? + C1 Q1 D2 1:n Lk2 D1 L2 D3 C2 Co

Lk1 Lm L1 ? + C1 D2 1:n Lk2 D1 L2 Co + Vo ?

Lk1 Vin + ? Lm L1

1:n Lk2 D1 L2 + D3 Co C2 Vo ?

Vin + ?

Lk1 Lm L1

1:n Lk2 D1 L2 + Co V D3 o ? C2

+ Vin + Vo ? ? Q1

D3 C2

? + C1 Q1 D2

? + C1 Q1 D2

(a)

JSL

(b)

(c)

(d)

54

Voltage Conversion Ratio of Charge Pump Reboost Converter

? Assume capacitors are large enough that their voltage maintains constant during steady-state operation. Also assume the transformer windings are perfectly coupled. ? During off period (Mode-a and Mode-d), V·s of L2 is D’·VL2. With V·s balance, D’·VL2 = n·D·Vin. Thus VL2 = n·D·Vin/D’, and VLm = D·Vin/D’ ? VC2 = Vin + D·Vin/D’ = (1+D/D’)Vin = Vin/D’. ? During on period (Mode-c), VC1 = VC2 = Vin/D’. Under Mode-d condition, we have

D? 1 ? 2 nD ? ? 1 Vo ? VC 2 ? VC1 ? VL 2 ? Vin ? ? ? n ? ? Vin ? ? ? D' ? ? D' D' ? ? D' D'

boost charge pump flyback

The voltage conversion ratio becomes

Vo 2 ? nD ? Vin 1? D

Actual voltage conversion ratio will be slightly lower with non-perfectly coupled transformer.

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55

Voltage Conversion Ratio and Duty Cycle Comparison

20 18 16 14 12 10 8 6 4 2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

recharge boost with n = 0.58

Voltage gain

reboost with n = 8

Charge-pump re-boost converter n = 2.7

Duty Duty cycle range Reboost: 0.17 at 70V to 0.68 at 10 V Recharge boost: 0.10 at 70 V to 0.88 at 10 V Charge pump reboost: 0.16 at 70 V to 0.8 at 10 V (most suitable range) JSL

56

Measured and Calculated Voltage Conversion Ratio

12 Measured Gain Voltage Gain (Vo / Vin) 10 Predicted Gain

calculated

8 6 4 2 0 0 20 40 Duty Cycle (% ) 60 80

measured

?

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Measured voltage conversion ratio matches calculated one very well.

57

Measured Charge-Pump Reboost Converter Efficiency at Different Voltages

98.0 97.0 96.0

Efficiency %

95.0 94.0 93.0 92.0 91.0 0 20

15V 25V 40V 60V

20V 30V 50V 70V

VT test results with 100V FET, Vo = 200V, 85kHz, n = 2.7

40 60 80 % of rated load, 100% = 300W

100

120

58

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Recap of Part A

? A multiphase isolated DC-DC converter with peak efficiency of 98% and significant reduction on high-frequency ripples, thus allowing small-size, low-cost passive components to be used. ? Low-frequency ripple is a major issue in maximum energy harness. An active cancellation technique was presented. ? Super high efficiency (>99%) can be achieved with bidirectional dc-dc converter operating in synchronous conducting mode. ? Different high boost ratio dc-dc converter circuits were presented to show how to design low-cost and high-efficiency converters for renewable energy such as solar panel integration applications.

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59

Half-Time Break

?

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60

Outline – Part B

Part A – High Efficiency DC-DC Converters

1. High-Efficiency Low-Ripple Isolated DC-DC Converter 2. Energy Management Using Bidirectional DC/DC Converter

3. High Boost Ratio DC-DC Converters

Part B – High Efficiency Inverters

1. 2. 3. 4. 5. Half-Cycle Asymmetrical Unipolar PWM Single-Stage Power Conversion Dual Buck Converters H5 Inverter Isolated Single-Stage Design

6. Soft-Switching Inverters

Part C – Energy Efficiency Standards

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61

Outline Part B-1

Part A – High Efficiency DC-DC Converters

1. High-Efficiency Low-Ripple Isolated DC-DC Converter 2. Energy Management Using Bidirectional DC/DC Converter

3. High Boost Ratio DC-DC Converters

Part B – High Efficiency Inverters

1. 2. 3. 4. Half-Cycle Asymmetrical Unipolar PWM Single-Stage Power Conversion Dual Buck Converters H5 Inverter

5. Isolated Single-Stage Design 6. Soft-Switching Inverters

Part C – Energy Efficiency Standards

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62

A Full-Bridge Inverter Circuit

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63

Bipolar Sinusoidal PWM Method

Vc: carrier wave vref: reference voltage

S1, S4 S2, S3 vab vo

Algorithm: ? If vref >vc, turn on upper device; otherwise, turn on lower device.

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time

? If upper device is on then va0= vdc,; otherwise, va0= 0. ? van = va0 – vdc/2;

64

Unipolar (Dual) Sinusoidal PWM Method

vc vref-a vref-b

S1 S2 S3 S4 vab

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time

65

Detailed Waveforms of Unipolar PWM

Vref-a 0

Ts

0 Vref-b va0 vb0 vab

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Vdc 0 Vdc 0 Vdc 0

–Vdc

Switching frequency effectively doubled

66

PWM Methods in Multi-Stage and Single-Stage Power Conversions

? For dc voltage higher than the peak of ac output voltage, a simple dcac inverter can be used. However, for dc voltage lower than the peak of ac output voltage, multiple-stage (multiple high-frequency PWM stages) power conversion is needed to obtain the desired ac voltage. ? It is possible to convert low-voltage dc to high-voltage ac with a single PWM stage dc-dc converter to obtain high-voltage dc and a polarity selection stage to obtain high-voltage ac.

Vdc

+ Vin – HF PWM DC/AC HF Xformer AC/DC HF SPWM DC/AC High-frequency switching DC/AC inverter

Vac + Vin –

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Vac

(a) Multi-stage power conversion

High-frequency transformer

HF PWM DC/AC

Xformer AC/DC

LF Distribution DC/AC Low-frequency polarity selection

(b) Single-stage power conversion

67

High-frequency transformer

A Typical Multi-Stage Power Conversion Using Voltage Source Push-Pull DC-DC Converter and Voltage Source Full-Bridge DC-AC Inverter

DC-DC converter PV array dc/ac inverter filter ac output

? Use voltage source type push-pull dc/dc converter to boost voltage ? Entire module can operate independently with one PV array input and one ac output ? Multiple ac module outputs can be parallel-connected to utility line

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68

A Typical Multi-Stage Power Conversion Using Current Source Push-Pull DC-DC Converter and Voltage Source Full-Bridge DC-AC Inverter push-pull boost converter PV array + Vdc –

? Use current source type push-pull dc/dc converter to boost voltage ? Entire module can operate independently with one PV array input and one ac output ? Multiple ac module outputs can be parallel-connected to utility line

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69

dc/ac inverter

filter ac output

Single-Stage Inverter with Isolated Converter and a Matrix Converter for Low-Voltage PV Systems

matrix converter filter + Vin – HF PWM DC/AC Xformer ac output High-frequency transformer ? ? ? Low-voltage converter implements PWM Transformer converts high-frequency low-voltage PWM to high voltage A matrix converter or cycloconverter converts high-frequency ac to low-frequency ac

70

Vac

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2. Basic Single-Stage Design Idea – A DC-DC Buck Converter + AC Selection Bridge

Vac

Vdc

Filter Buck stage Features:

? ? ? ? ?

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LF distribution AC selection network

High input voltage level Buck converter produces rectified SPWM Low frequency selection network produces ac SPWM output Use power MOSFET as the buck switch to reduce switching loss Use IGBT or thyristor as the low-frequency ac selection switch to avoid reverse recovery loss

71

Basic Operating Modes of Buck Switch

S5 S3 S1 S5 S3 S1 S5 S1, S4 S2, S3 S2 S4 S4 vo

S2

(a) Positive cycle S1&S4 on,S5on

S3 S5 S 1

(b) Positive cycle S1&S4 on,S5 off, freewheeling

S5 S3 S1

S2

S4

S2

S4

? S5 is half-wave symmetrical PWM operated ? Positive cycle, S1and S4 are always on ? Negative cycle, S2 and S3 are always on

(c) Negative cycle S2&S3 on, M1 on JSL

(d) Negative cycle S2&S3 on, M1off, freewheeling

72

3. Dual Buck Type Inverter

200V 100V 0V -100V -200V

vo

V(VaL)

i1 i2

vo

io

Load

20A 10A 0A -10A -20A I(RL) 20A 10A 0A SEL>> -20A 50ms

io i1

80ms Time 100ms

i2

60ms I(RLa) I(RLb)

Features:

? ? ? ? Use power MOSFET to reduce turn-off loss Use ultrafast reverse recovery diode to reduce turn-on loss No dead time and shoot-through concerns The only issue is power flow is unidirectional, and the output current must be in phase with the output voltage (reactive power output tends to have distorted current waveform)

73

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Dual Buck Inverter with Dual Outputs

i1 i2

ia

Load1 Load3

i3 i4

Load2

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74

Dual Boost and Dual Buck-Boost Inverters

L1 C Vdc1 R Vdc2 L2 C iL + vo – Vdc2 Vdc1 C L1 R L2 C iL + vo –

(a) Double Boost Inverter ? ? ?

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(b) Double Buck-Boost Inverter

Use power MOSFET to reduce turn-off loss Use ultrafast reverse recovery diode to reduce turn-on loss No dead time and shoot-through concerns

75

Asymmetrical Half-Cycle Unipolar PWM

S1 S3 S1 S3 S1 S4 S3 S2 S4 S2 S4 S2 vo

(a) Positive cycle S1 SPWM, S4 is always on

S1 S3 S1 S3

S2

S4

S2

S4

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(b) Negative cycle S3 SPWM, S2 is always on

? Split previous buck switch S5 into two PWM operated buck switches, S1 and S3 ? Positive cycle, S4 is always on, S1 runs in SPWM ? Negative cycle, S2 is always on, S3 runs in SPWM

76

4. Asymmetrical Half-Cycle Unipolar PWM Inverter with 5 Switches (H5TM Inverter)

SPWM Buck stage LF selection S1 S1 Vdc S6 S5 S3 S3 Vac

S2

S4

Filter

Features:

? ? ? ? ? ?

JSL

Buck switch S5 produces rectified SPWM IGBT’s S1 and S3 serve as low frequency selection network MOSFET S2 operates in SPWM on negative cycle MOSFET S4 operates in SPWM on positive cycle Use fast recovery diode for S1 and S3 to reduce reverse recovery loss S5 and S2 or S4 share half the DC bus voltage, allowing low-voltage switches to be used in high voltage input

77

Operating Modes of H5TM Inverter

S5 S2 S1 S5 S2 S1 S5 S4 S1 S3 S4 S3 S4 S3 S2 vo

(a) Positive cycle S1, S4&S5 on

S2 S5 S 1

(b) Positive cycle S1 on,S4 and S5 off, freewheeling

S5 S2 S1

S3

S4

S3

S4

(c) Negative cycle S3, S2&S5 on

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(d) Negative cycle S2 on, S3 and S5 off, freewheeling

78

Measured Gate Signals and Output Voltage Waveforms

AC voltage (100 V/div) S3 S5

S4

?

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Experimental results verify the basic operation.

79

Measured H5 Inverter Efficiency

0.990 0.985 0.980 0.975 0.970 0.965 0.960 0.955 0.950 0 1 2

Efficiency

Input: 420 V Output: 240 V

3 4 5 6 7 8

Power (kW) ? ?

JSL

Use 2 CoolMOS parallel for S5 and S6. They are resistive element, so efficiency is high in low power region. Use slow IGBT but ultra fast diode, which can be replaced with SiC Schottky diode to further reduce the MOSFET turn-on loss.

80

5. Isolated Single-Stage Design

Vac + Vin – Xformer AC/DC LF Distribution DC/AC Low-frequency switching inverter

HF PWM DC/AC

High-frequency transformer ? ? ? ?

JSL

Low-voltage inverter implements symmetrical sinusoidal PWM Transformer converts high-frequency SPWM to high voltage Rectifier converts symmetrical SPWM to rectified SPWM Low-frequency inverter selects the positive and negative cycles, same as the non-isolated version

81

Enphase Active-Clamp Flyback Inverter

D2 Q1 Q3

Sx2

S2 D1 Q2 Q4

Q5

?

Sx1

S1

?

?

JSL

Interleaved flyback converters serve as single-stage power conversion. MOSFET S1 and S2 are the main switches. Sx1 and Sx2 are auxiliary switches for active clamp. Q1, Q2, Q3, and Q4 thyristors serve as polarity selection switches. Q1 and Q3 turn on during positive cycle. Q2 and Q4 turn on during negative cycle. Q5 helps commutate thyristors under low dc bus voltage condition. 82

Measured Efficiency of Enphase Inverter

0.95 0.94 0.93 0.92 0.91 0.90 0.89 0.88 0.87 0.86 0 20 40 60 80 100 120 140 160 Power (W)

? ? ?

JSL

Use SiC Schottky diode for D1 and D2 to reduce reverse recovery loss Use low voltage drop thyristors as the polarity selection switch and block reverse (high) voltage from utility Use low conduction voltage drop CoolMOS Q5 to help turn off thyristors at low voltage or zero voltage crossing.

83

Features of Single-Stage Power Conversion

? Reduced power conversion stages with only one PWM stage needed, potentially low cost ? High efficiency due to reduced PWM operation ? Low frequency ripple propagates back to source without any buffer ? A large capacitor bank is needed at the source to ensure maximum power tracking

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Efficiency

84

6. Soft-Switching Inverters

? Soft-Switching Basics ? Zero-Voltage Switching Type Soft-Switching Inverters ? Resonant Snubber Inverter ? Coupled-Magnetic Type Zero-Voltage Switching Inverter

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85

Issues with Device Switching

? Problems associated with conventional hard switching

– High switching losses ? Poor efficiency – High dv/dt and di/dt ? Issues with Electromagnetic inference (EMI)

device voltage 0 device current 0 device power loss 0

turn-on

turn-off

? Major switching losses

– Diode reverse recovery induced turnon loss – IGBT turn-off tail current induced turnoff loss

conduction

? Soft switching methods

– Zero voltage switching (during turn-on) – Zero current switching (during turn-off)

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Waveforms Showing Device Switching Behaviors

86

What’s Relationship Between Snubber and SoftSwitching?

Llk ? Ls The traditional snubber uses Ls to limit the turn-on current rise and Cs to limit the turn-off voltage rise. Device losses were reduced, but the snubber losses were significant. Here are some formula for loss estimation. Snubber loss Turn-on loss Cs Ls Turn-off loss ?

( 2 Ls ? Llk ) I o ? 3CsVdc Ps ? fs 2 Pon ? Vdc tr fs 24( 2 Ls ? Llk )

2 2

2

2

Vdc

Cs

Io

2

2

I t Poff ? o f f s 24Cs

Soft-switching is to do the same job that limits the current rise and voltage rise, but at the same time, to avoid the loss incurred in the snubbers.

87

JSL

Categories of Zero-Voltage Soft-Switching Inverters

Resonant DC Link

Ordinary Resonant Dc Link Active-Clamp Resonant dc Link Quasi-Resonant Dc Link DC Rail Zero-Voltage Transition

Resonant Pole

Ordinary Resonant Pole Clamp Mode Resonant Pole (CMRP)

Auxiliary Switched Resonant Snubber

Auxiliary Resonant Commutated Pole (ARCP) Magnetic Coupled ZeroVoltage Transition Y-Configured Resonant Snubber Inverter (Y-RSI) ?-Configured Resonant Snubber Inverter (? -RSI)

Not easy to achieve 99% efficiency cost effectively

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88

Auxiliary Resonant Commutated Pole (ARCP) Inverter

Csp Sa Vs Csn S4 C4 S6 C6 Sc S2 C2

R. DeDoncker, 1991

S1 Lra

C1

S3

C3

S5

C5

Lrb Sb Lrc

ac motor

Features:

? Standard PWM applicable ? Auxiliary switch sees half dc bus voltage ? Small size resonant components

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Disadvantages:

? ? ? Extra bulk energy storage capacitors Unbalanced capacitor voltages Need complicated control for zerovoltage switching

89

Single-Phase Resonant Snubber SoftSwitching Inverter with One Inductor

S1 IS1

D1 C1 a Ro Lr C2 Io Lo Sr1

S3 b

D3 C3 IS2 IS4 D4

Vdc

IS3 D2 S2

ILr1 Dr1

ILr2

Sr2

Dr2

S4

C4

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90

Operation Modes of the Single-Phase Resonant Snubber Soft Switching Inverter

S1 Vdc Lr1 Ro Dr1 Sr1 Io Lo S3 IS3 0

IS1,4 ILr2 Io

S2

Lr2

Sr2

Dr2

S4

0 0

IC1,4

IS2,3 IC2,3 S 2,3 Sr2 t0 t1 t2 t3t4 t5 t6 IC2,3 IC1,4 S1,4

Mode 0: t0 ~ t1 S1 Vdc Lr1 Ro Dr1 Io ILr2 S2

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Sr1 Lo

S3 IS3

0 0

Lr2

Sr2 Dr2

S4

91

Mode 1: t1 ~ t2

Operation Modes of the Single-Phase Resonant Snubber Soft Switching Inverter

S1 Vdc Lr1 Ro Dr1 Sr1 Io ILr2 S2 Lr2 Sr2 Dr2 S4

0 IS2,3 IC1,4 IC2,3 S 2,3 Sr2 t0 t1 t2 t3t4 t5 t6 IC2,3 IC1,4 S1,4

S3 IS3

0 IS1,4 ILr2 Io

Lo

Mode 2: t2 ~ t3 S1 Vdc Lr1 Ro Dr1 Sr1 Io ILr2 S2

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S3 IS3

0 0 0

Lo

Lr2

Sr2 Dr2

S4

92

Mode 3: t3 ~ t4

Operation Modes of the Single-Phase Resonant Snubber Soft Switching Inverter

S1 Vdc Lr1 Ro Dr1 Sr1 Io ILr2 S2 Lr2 Sr2 Dr2 S4

0 0 0 0 IC1,4 IC2,3 S 2,3 Sr2 t0 t1 t2 t3t4 t5 t6 IS2,3 IC2,3 IC1,4 S1,4

S3

Io

ILr2

Lo IS4

0

IS1,4

Mode 4: t4 ~ t5 S1 Vdc Lr1 Ro Dr1 Sr1 Io Lo IS4 S2

JSL

S3

Lr2

Sr2

Dr2

S4

93

Mode 5: t5 ~ t6

Power Circuit of 3-Phase Couple-Magnetic Soft-Switching Inverter

Sx1 Sx3 Sx5 S1 S3 C1 Lra Vs Cs Sx4 Sx6 Sx2 Lrb Lrc S4 S6 C4 S2 C6 C2 S5 C3 C5 ac motor

Distinct design features:

1. Make turns ratio 1:n with n>1 to ensure zero-voltage switching for a wide range operation 2. Fix delay timing control to simplify controller design

94

JSL

Single-Phase Test Circuit and Basic Operation

?

Sx1 Vdc

Dx1 n 1

S1 Lr ILr S2

C1 ?

VCE1

Lo

S1 Sx1 S2 Sx2

tdt

tdt

tdly iLr iLoad iC2 iC1 iD1 vCE1 iS1 vCE2

t0 t1 t2 t3 t4 t5

tdly

Io Load C2

Sx2

Dx2

tdt: dead time from DSP controller (e.g. 2?s) tdly: delay time (e.g. 1.5?s) tx = tdt – tdly= 0.5?s

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?t1 ?

I Load Lr1 Vdc

I L ?t 2 ? Load r 2 Vdc

95

Illustration of Soft-Switching Operation

(a) Sx1 Dx1 Lr2 Vdc Lr1 Sx2 (c) Dx2 S2 C2 Sx2 (d) S1 (b) C1 ILoad Vdc Lr1 Dx2 S2 C2 Sx1 Dx1 S1 Lr2 C1 ILoad

Sx1

Dx1 Lr2 Lr1

S1

C1 ILoad

Sx1

Dx1 S1 Lr2 Lr1

C1 ILoad

Vdc

Vdc

Sx2

JSL

Dx2

S2

C2

Sx2

Dx2

S2

C2

96

Soft-Switching Operation (cont’d)

(e) Sx1 Vdc Lr1 Sx2 Dx2 S2 C2 Sx2 Dx1 S1 Lr2 C1 ILoad Vdc Lr1 Dx2 S2 C2 (f) Sx1 Dx1 S1 Lr2 C1 ILoad

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97

Inverter Photo Showing DC Bus Capacitor and Coupled Magnetic Connections Resonant inductor Saturable inductor DC bus bar

DSP interface

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98

Experimental Verification in One Resonant Cycle

200A 175A 150A 125A 100A 75A 50A 25A 0A -25A

t(.5?s/div) iLr iLr1 iLr2 ILoad

vGE (20V/div) ILoad (100A/div) iLr (100A/div) vCE (200V/div) t (0.5?s/div)

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99

Experimental Results of Inverter Operation at 300-V Bus 69-A Load Current

vGE (20V/div)

iLr (100A/div) ILoad (100A/div)

t(500?s/div)

JSL

vCE (200V/div)

100

Efficiency Test Results with 100-kW Compressor

100% 99% 98% 97% 96% 95% 94% 93% 92% 91% 90% 20

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Efficiency

30

40

50

60

70

80

90

101

Inverter Input Power (kW)

Efficiency Test Results with a 5-kW Adaptive Timing Zero-Voltage Switching Inverter

99% 98% 97% 96% 95% 94% 93% 92% 91% 0

Resonant inductors

Adaptive timing soft switching Hard switching Fixed timing soft switching

DC bus capacitors Resonant capacitors AC output

Efficiency (%)

DC input

DSP board

1

2 3 4 5 Output Power (kW)

6

? ? ?

Fixed timing shows poor light load efficiency, worse than hard-switching case At 20% load (1-kW), the efficiency improvement with variable timing is >3%. High power output (>4.5 kW), the efficiency difference becomes less visible but both soft switching shows better efficiency than hard switching case

102

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Features of the Auxiliary Commutated Resonant Snubber Inverters

? Main switches turn on at zero voltage or under their anti-parallel diodes conducting condition; ? Main switches turn off at a slower dv/dt rate and lossless snubbing condition; ? Main switches do not have over-voltage or over-current stress; ? Auxiliary switches conduct only in a short period as compared to the PWM cycle; ? Auxiliary switches turn on and off under zero current condition; ? Auxiliary switches need to carry high peak current, typically higher than the rated load current; ? Free wheeling diodes across the main switches do not have reverse recovery problems because their currents are diverted by the auxiliary resonant circuitry; ? Auxiliary circuit diodes need to have very fast reverse recovery characteristic to prevent the resonant current from oscillation when it is swinging down across the zero point.

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103

Recap for Part B

? For energy applications, single-stage inverters have been actively studied and extended to different variations of highefficiency inverter. ? High efficiency commercial inverters (SMA and Enphase) are introduced. ? Dual buck, dual boost, and dual buck-boost inverters show potential for high efficiency operation. ? Soft-switching shows efficiency >99% for 3-phase high-power motor drives and >98% for 1-phase 5-kW grid-tie inverter.

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Outline – Part C

Part A – High Efficiency DC-DC Converters

1. High-Efficiency Low-Ripple Isolated DC-DC Converter 2. Energy Management Using Bidirectional DC/DC Converter

3. High Boost Ratio DC-DC Converters

Part B – High Efficiency Inverters

1. 2. 3. 4. Half-Cycle Asymmetrical Unipolar PWM Single-Stage Power Conversion Dual Buck Converters H5 Inverter

5. Isolated Single-Stage Design 6. Soft-Switching Inverters

Part C – Energy Efficiency Standards

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105

Part C. Energy Efficiency Standards

? California Energy Commission (CEC) ? IEC 61683:1999, First Edition, 1999-11, Photovoltaic systems – Power conditioners – Procedures for measuring efficiency.

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Efficiency of Alternative Energy Inverters – California Energy Commission (CEC) ? All inverters must meet the requirements in EMERGING RENEWABLES EMERGING RENEWABLES PROGRAM, Final Guidebook, Eighth Edition, Section C Inverters. ? There are no set minimum requirements, but the conversion efficiency must be tested and reported to CEC - as defined here.

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IEC 61683:1999, Photovoltaic Systems

– Power Conditioners Procedure for Measuring Efficiency

? This standard describes guidelines for measuring the efficiency of power conditioners used in standalone and utility-interactive photovoltaic systems, where the output of the power conditioner is a stable systems, where the output of the power conditioner is a stable ac voltage of constant frequency or a stable dc voltage. ? The efficiency is calculated from a direct measurement of input and output power in the factory. ? An isolation transformer is included where it is applicable. ? China: GB/T 20514-2006 is based on IEC 61683:1999

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CEC and IEC Weighted Efficiency Measurement CEC 5% 10% 20% 30% 50% 75% 100%

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IEC 0.03 0.06 0.13 0.10 0.48 0 0.20

109

0 0.04 0.05 0.12 0.21 0.53 0.05

Example Efficiency Measurement Results

(A High-Boost Ratio DC-DC Converter Example)

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Measured and Weighted Efficiency Plots

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Summary of Power Electronics Design for Energy Efficiency at Different Levels

? System level – Solar MagicTM, single-stage design ? Circuit topology – soft switching converter/inverter, dual buck inverter, multilevel converter ? Modulation scheme – phase-shift modulation, synchronous conduction mode ? Power device – SiC diode, CoolMOS, hybrid switch ? Combination of above – H5 inverters ? Control strategy – maximum T/A and maximum efficiency for motor drives

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Recap

? High-efficiency and high-performance dc-dc converters were discussed in three categories:

? multiphase isolated dc-dc, ? bidirectional dc-dc, and ? high-boost ratio dc-dc converters.

? High-efficiency dc-ac inverters were introduced in three categories:

? Dual buck, dual boost, and dual buck-boost inverters, ? Single-stage inverter for potential high-efficiency and lowcost design ? Soft-switching inverters show promising efficiency for both motor drive and energy applications.

? Efficiency standards in US and Europe are introduced to show how to calculate weighted PCS efficiency.

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?

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