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Current Status and Challenges of SoC Verification for


An Application-Specific Design Methodology for STbus Crossbar Generation

Author: Srinivasan Murali, Giovanni De Micheli Proceedings of the DATE’05,pp.1176-1181,2005

Presenter : Ching-Yuan Lin Date : 2007/1/22 Seminar book :P120

Abstract
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As the communication requirements of current and future Multiprocessor Systems on Chips (MPSoCs) continue to increase, scalable communication architectures are needed to support the heavy communication demands of the system. This is reflected in the recent trend that many of the standard bus products such as STbus, have now introduced the capability of designing a crossbar with multiple buses operating in parallel. The crossbar configuration should be designed to closely match the application traffic characteristics and performance requirements. In this work we address this issue of application-specific design of optimal crossbar (using STbus crossbar architecture), satisfying the performance requirements of the application and optimal binding of cores onto the crossbar resources. We present a simulation based design approach that is based on analysis of actual traffic trace of the application, considering local variations in traffic rates, temporal overlap among traffic streams and criticality of traffic streams. Our methodology is applied to several MPSoC designs and the resulting crossbar platforms are validated for performance by cycle-accurate SystemC simulation of the designs. The experimental case studies show large reduction in packet latencies (up to 7×) and large crossbar component savings (up to 3.5×) compared to traditional design approaches.

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STbus Crossbar Architecture
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Low-latency, high bandwidth infrastructure
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Interface components: arbiters and frequency/data width adapters

※Full crossbar architecture
Initiators Arbiters Buses Targets Initiators Buses Arbiters Targets

I1 I2 I3

A1 A2 A3

Bus 1 Bus 2 Bus 3

T1 T2 T3

I1
I2 I3

Bus 1 Bus 2 Bus 3

A1 A2
A3

T1 T2 T3

Initiator-Target crossbar

Target-Initiator crossbar

※Partial crossbar architecture
Initiators Arbiters Buses Targets

I1

A1

Bus 1

T1 T2

I2
I3

A2

Bus 2

T3

Initiator-Target crossbar
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What’s the Problem
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Full crossbar is expensive
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Lot of wires and gates Partial crossbar is a compromise solution

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Optimum partial crossbar
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Latency close to full crossbar Fewer component and area How to design best partial crossbar for applications?

4

Application Traffic analysis
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Example traffic trace from 3 Targets

※Traffic trace T1: T1: T2
Merge t1&t2

T2:

T3:

overlap

Simulation period:

Simulation period:

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Overlap is increase average and peak latency

5

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Consider criticality of streams
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Targets with overlapping real-time stream should not share the same bus
※Traffic trace T1: T2 T3:
Simulation period:

Real time constraint

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Crossbar design approach
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Simulation time window for analysis
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Split to fixed sized windows
Satisfy bandwidth requirement
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In each simulation window
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The total receives data of every core (place on same bus) must less or equal than window size

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Minimize overlaps among streams Consider criticality of streams
T1: T2 T3:

overlap
Windows 1

Simulation period:

Windows 2
7

Design flow for partial crossbar design

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Phase1
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Full crossbar traffic in perfect communication Data collection hardware add to arbiters
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Traffic collection on each window
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Data rate for each core Overlap among streams Criticality of streams

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Phase 2: Pre-processing
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Core that should be different buses
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Cores with large overlap (above threshold) (1) Cores with overlapping criticality streams (2) Non-satisfy bandwidth requirements (4)
To bound maximum latency (8)
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Maximum number of cores on bus
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Worst case: packets to all the target onto a bus can arrive in the same cycle

T1: T2: T3:
Simulation period:

One packet (burst)
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Phase 3: Crossbar Design Start with a single bus ? Check for feasible solution
?
? ? ?

Satisfy window bandwidth constraints (4) Place forbidden core on different buses (1)(2) Fewer than maximum number of cores on each bus(8)

Repeat step2, incrementing the number of buses by 1 ? Optimal binding:
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Minimize overlap on each bus (11)

11

Experiment result
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Application benchmark
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?
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Matrix suite-1 (25 cores) Matrix suite-2 (21 cores) FFT suite (29 cores) Quick sort suite (15 cores) DES encryption system (19 cores)

※Matrix multiplication benchmark-2 (21 cores)
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Initiator-target full crossbar
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Need 12 bus Need 9 bus

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Target-initiator full crossbar
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FC bus count = 21

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The average and maximum packet latencies
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Latencies of crossbar (avg) are 4x to 7x higher than crossbar designed using our scheme

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Win : optimal partial crossbar Avg: crossbar base communication traffic flow ,by relaxing overlap constraints and using a single window

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Effect of window size variations

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a) Small window size:
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Finer control of the performance parameters and crossbars have lower latencies Disadvantage: over-design of the network component

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b) the acceptable window size for various burst size
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Overlap threshold setting

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From experiments, threshold value can be set:
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30%-40% of window size for conservative design 10% of window size for conservative designs

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Conclusion
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Presented methodology for STbus crossbar design
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local variations in traffic Overlap of streams Criticality of traffic streams

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Large saving in components, good performance Approach can be extended to other bus designs

16


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