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A I-V CMOS Ultralow-Power Receiver Front


A I-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole
Aaron V. Do, Member, IEEE, C. C. Boon, Member, IEEE, Manh Anh Do, Senior Member, IEEE, Kiat Seng Yeo, Member, IEEE, Alper Cabuk, Member, IEEE
TABLE I OVERALL SENSITIVITY VERSUS MIXER TYPE FOR RECENT LOW-POWER FRONT ENDS Reference SenNF(dBm) SenllP3 (dBm) Mixer TypeA Tech. (nm) Power (mW) IF Power (mW)
A

which uses a voltage-mode passive mixer with a tuned output requirements are relaxed by up to 33 dB for the IEEE 802.15.4 pole. Using this technique, it is shown that the IF section's HP3

Abstmct-A novel passive mixer architecture is proposed

[2] -91.3 -110 PC 180 10 5.76c

[3] -92 -68 A 180 1.4 0.5

[4] -91.9 -127 PV 130 0.75 0.75

[5] -91 -118 PV 90 4.05 1.15

[6] -89.7 -126 PC 180 6.3 4.5

[7] -87 -112 A 180 10.8

[8]B -90.7 -88 PC 180 5.4 0.36

standard. This allows for use of an ultralow power IF section without linearity compensation. The overall receiver front end consisting of an LNA, a mixer and a third-order channel-select

1.7-mW total power consumption.

voltage, and post-layout simulations show a 5 dB NF with only

filter is designed in 0.18 11m CMOS technology with a I-V supply

Low Power, System on Chip.

Index Terms-RF Front End, CMOS RF Integrated Circuits,

A: Active, PV: Passive Voltage-mode, PC: Passive Current-mode B Second gain mode c Estimated only.

I.

INTRODUCTION

HE IEEE 802.15.4 standard [1] was designed to cater to the increasing demand for low-power, low data-rate applications such as wireless sensor networks, and wireless personal area networks (WPAN). Such applications often require mobile devices or devices in remote locations without a connection to the power mains. Therefore, low power consumption is a critical requirement for extending the battery life of such devices. This work deals with the upper band of the IEEE 802.15.4 standard which is the 2.4-GHz Industrial Scientific and Medical (ISM) band. The system bandwidth is 83.5 MHz from 2.4 GHz to 2.4835 GHz. The standard offers 16 channels with 5-MHz spacing, and an IEEE 802.15.4 signal occupies a 2-MHz bandwidth and provides a data rate of 250 kb/s. The standard features relaxed requirements in terms of adjacent and alternate channel interference (+0 dBc and +30 dBc respectively) and a sensitivity requirement of -85 dBm. This work focuses on receiver architecture design for low? power operation. In section II we make the case for the use of passive mixing over active mixing. In section III, we discuss the proposed passive mixer topology and show that it can offer a 33 dB improvement in IF section IIP3. In section IV we
Manuscript received April 4th 2010. The authors are with Nanyang Technological University, Singapore 639798 (email: eccboon@ntu.edu.sg; doaaron@ntu.edu.sg; emado@ntu.edu.sg; eksyeo@ntu.edu.sg)

T

discuss the overall system design, and in section V we present simulation results of the proposed design. The design has been sent for fabrication in a 0.18 11m RFCMOS process and will be subsequently characterized. II. THE CASE FOR PASSIVE MIXERS Among recent low-power research works, architectures using passive mixers have generally out-performed those using active mixers in terms of overall sensitivity (for the IEEE 802.15.4 standard) [2]-[8]. This is mainly attributable to the fact that passive mixers minimally distort the input signal (due to the passive operation), and do not add flicker noise to the system. However, a standard Gilbert-Cell mixer does both. Given the IEEE 802.15.4 standard receiver blocking profile [7], we can calculate the sensitivity based on IIP3 as, (1) where Pb1k is the interfering power, SNRreq is the required output signal to noise ratio (SNR), and I/P3 is the receiver input-referred third order intercept power. From [9], we estimate the SNRreq to be approximately 14 dB while Pb1k is -52 dBm in the worst case when the input power is 3-dB higher than the required sensitivity (-85 dBm [1]). The sensitivity based on noise figure (NF) can be easily calculated as,

SenNF

=

NF + 1OIog(kT4f)+ SNRreq

(2)

978-1-4244-6471-5/10/$26.00 ?2010 IEEE

381

PSD 30 dBc

RFin

>----L---I=::>

IF out
-20 -15 -10 -5 (a) PSD 5 10 15 20 f(MHz)

(a)

1---,--r--l::J IF out
-20 -15 -10 -5 (b) 5 10 15 20 f(MHz)

(b)
Fig. I A simplified illustration of connection between (a) a current-mode passive mixer and an op-amp based filter, and (b) a voltage-mode passive mixer and a gm-C based passive mixer.

Fig. 2 U1ustration of the effect of a single pole low-pass filter on IEEE 802.15.4 standard interference. The striped signals are interferers while the shaded signal is the desired signal.

where kTI':!.j is -Ill for a 2 MHz signal bandwidth. Table I shows the sensitivity of designs [2]-[8] and the mixer type used. We have included the overall power consumption as was published, but it is important to note that different works presented more or less complete systems. Furthermore, certain designs [3], [4] were not specifically designed for the IEEE 802.15.4 standard. Table I clearly shows the advantage of using passive mixers in IEEE 802.15.4 systems. Of the two designs using active mixers, [3] fails to meet sensitivity requirements based on IIP3, and [7] requires more power consumption than other works. Two different types of passive mixers have emerged in recent literature, namely, current-mode and voltage-mode passive mixers. Current-mode passive mixers use a passive switching stage followed by a transimpedance amplifier (TIA) [6] in order to convert the switching stage's output current into a voltage. Voltage-mode passive mixers require that the following stage have high input impedance so that the output of the switching stage is in voltage form. Therefore, current? mode passive mixers connect naturally with op-amp based channel-select filters (CSF), while voltage-mode passive mixers connect naturally with Gm-C type CSFs. This is illustrated in Fig. I. The switching stages are represented by variable resistors controlled by a local oscillator (LO) voltage, Vw. The required filter should be of high enough order to remove the unwanted adjacent and alternate channel interference. III. THE PROPOSED PASSIVE MIXER ARCHITECTURE As the RF circuitry (LNA, Mixer) must pass the entire system bandwidth (83.5 MHz for the IEEE 802.15.4 standard),

the IIP3 requirements are based on worst-case interference. Blocks following the CSF such as limiting amplifiers, variable? gain amplifiers (VGA), etc, do not need to meet such stringent linearity requirements since all of the interference is presumed to have been filtered off by the CSF. However, the CSF itself must still meet IIP3 requirements which are tightened by the high gain of the RF front end required for good noise performance. The high IIP3 requirements of the IF section has led most designers to chose one of two options. The first option is to use a comparatively low RF section gain [4] (only 17 dB) and boost the noise performance of the IF section, which requires more power consumption in the IF section. The second option is to use highly linear CSFs such as op-amp based filters [10] as was done in [2], [4] and [5]. Op-amp based filters are able to achieve excellent linearity, but require a high loop-gain [11] possibly over the entire system bandwidth to reliably do so. In this work, we propose an alternate method for relaxing the IIP3 requirements of the IF section without requiring high power consumption. Going back to Fig. 1b, we note that the voltage-mode passive mixer is effectively an RC low-pass filter at the IF in cascade with a Gm-C type filter. In general, the real pole formed by the switch resistance and the output capacitance is not used for filtering because of the considerable variation in the switch resistance. The switch resistance can vary due to variations in the LO voltage (V LO), the switch threshold voltage, the switch size, and even the output impedance of the previous stage (the LNA output resistance affects the passive mixer output resistance [8]). As the passive switching stage is highly linear, using the passive mixer's output pole provides filtering at no cost in noise, linearity or power consumption; it is essentially "free". As this pole is created by a first-order low-pass filter, it works best when coupled with a direct-conversion system. Fig. 2 shows the effect of the free pole on IEEE 802.15.4 interference.

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SB-IQ-Mixer

Gm-C Biquads

LO Signals C?-"'t---::J

RFin

IFQout

Tuner LO Differential

IQ Signals
VCM

Fig. 3 Block diagram of the receiver front end. Differential LO IQ signals are externally derived and injected into the system. Replica mixers are used as part of the tuning circuitry for the passive mixer output pole. Single? balanced passive mixers convert the single-ended RF signal to a differential IF signal.

Fig. 4 Schematic of the LNA and single-balanced mixers including replica mixers used for tuning.

together with the Gm-C biquads form third-order butterworth type filters. The individual circuit blocks are described in more detail next.
A. The LNA and Mixers

The most stringent HP3 requirement is based on the intermodulation of two tones at 10 MHz and 20 MHz offset from the desired signal. Before filtering, their HP3 requirement for -85 dBm sensitivity and 14 dB SNR is approximately -30 + GRF dBm (using (1) where once again we take the signal strength to be 3 dB above the sensitivity level). Here GRF is the gain in dB of the LNA plus the mixer. A first order filter provides 20 dB/decade or 6 dB/octave attenuation above the corner frequency. Given a I-MHz signal bandwidth [2] at zero-IF, the corner frequency is set at 1 MHz. Therefore, after filtering, the 10 MHz tone is reduced by 20 dB and the 20 MHz tone is reduced by 26 dB. The new HP3 requirement of the filter is therefore -63 + GRF dBm. This is a 33 dB improvement in the HP3 requirements over the standard case. Likewise, considering interfering tones at 5 MHz and 10 MHz offset from the desired tone, the improvement is 24 dB. This 33 dB improvement can potentially be used to either improve the noise performance of the overall design by increasing the RF gain, or to reduce the current consumption of the IF section by using Gm-C filters with relaxed linearity requirements. The latter approach was adopted here. To give an idea of the importance of reducing IF section power consumption, we have included the IF section power consumption of recent works in Table I. The average IF section required 48% of the total receiver front end power consumption. The next section will describe the system design. IV.
RECEIVER DESIGN

A schematic of the LNA and mixers is shown in Fig. 4. Input matching is achieved using a series resonant network with a resistor in series. Under matched conditions, the noise figure of the matching network is 3 dB [12], and the voltage gain of the matching network is equal to the quality factor (Q) of the network. In this work, an 11.5 nH inductor was used resulting in a Q of 3.54 and a voltage gain of 11 dB. An LC tank was used to tune the output node of the LNA. The load inductor was 6.5 nH with a Q of 8.6 resulting in an effective output resistance for the LNA of 860 n. The LNA includes three gain control steps of 6 dB to ease the gain compression requirements of the IF section, and to allow for reduced power consumption at high input signal levels [8]. Single-balanced passive mixers were used to convert the single-ended RF signal into a differential IF signal. This allowed the use of a single-ended LNA thereby saving half of the LNA power consumption. The justification for this strategy is the relaxed IIP2 requirements of the IEEE 802.15.4 standard. The main concern is unwanted DC-offset related to the self? mixing of either LO signals or strong interfering signals. Self mixing of LO signals results in a static DC offset which must be filtered before introducing any high gain stages to the signal. We can estimate the require IIP2 based on self mixing of interfering signals as,

IIP2,req (dBm) ? 2Pb1k - Sen + SNRreq

(3)

A block diagram of the receiver is shown in Fig. 3. The entire system uses a I-V supply. The tuning circuitry is only operational in the tuning mode and therefore doesn't contribute to the overall power consumption. Differential IQ LO signals are derived externally to the system. The RF section consists of a single-ended LNA connected to voltage? mode passive mixers. The output pole of the passive mixers

where Sen is the required sensitivity. Given alternate channel interferers equal to -52 dBm, the required HP2 is 2(-52) - (-82) + 14 -8 dBm. The achieved I1P2 of the down-converter can be estimated as PW/Gleak where G1eak is the ratio of the differential RF signal at the gates of the switching stages to the single-ended RF signal at the source of the switching stages (note that G1eak does not include common-mode leakage) and
=

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383

I--.-CJ f3dB,in

\'- -:?,? ---------'1
1 1 1

RFin

LNA ,,>-_....I....J\

:C>-j
1 I,

1n+

f-a:
1

1n-

1 1 1

Fig. 6 D1ustration of the passive mixer output pole tuning loop. The mixer is represented by variable resistors and the digital amplitude comparator provides peak detection, filtering, and analog to digital conversion.

OutOuH ) -----------------

Fig. 5 Configuration of the Gm-C biquad and a transconductor.

Pw is the LO power. G'eak is effectively a single-ended to

differential leakage gain. In [13], it is shown that the IIP2 of active mixers has similar dependency, while IIP2 on the order of +40 dB is typical.
B.
The Channel-Select Filter

A third-order low-pass Butterworth filter has two complex poles and a single real pole. As previously mentioned, the real pole is formed at the output node of the passive mixer. Therefore, each Gm-C filter needs only provide a pair of complex conjugate poles. A diagram of the Gm-C biquad is shown in Fig. 5. The DC gain of the filter is equal to gm/gm2 while the comer frequency is equal to CI-V(gm2gm3) and the Q is equal to -V(gm3/gm2)' With four variables and three equations, we have one degree of freedom. This is used to select gml to provide the desired overall noise performance of the receiver system. The individual transconductors are configured as simple differential pairs. Using the passive mixer pole tuning method described in Section III, linearization of the transconductors [13] was not required. This allowed for the design of ultralow power biquads without sacrificing either noise or linearity performance. As flicker noise is an important consideration in the design, PMOS devices were used as the inputs of the differential pairs. Although PMOS devices are generally slower than NMOS devices, the operation frequency of the biquads is low. With only a I-V supply voltage, selection of the common-mode voltage of the IF section is important [14] as it will determine the maximum output swing of the filter. The common-mode voltage, VCM was set at 0.3 V which allows approximately 0.5 Vpk-pk of differential output swing. Gain compression requirements were further relaxed by the gain control in the LNA.
C. The Passive Mixer Tuning Loop

of the passive mixers without the output capacitors is also implemented. At the desired pole frequency, the real passive mixer will have a 3-dB lower output impedance than its replica. A signal at the desired pole frequency (1 MHz in this case) is fed into the passive mixers' outputs via high output impedance transconductors which do not affect the passive mixers' output impedances. The transconductors are implemented as simple differential amplifiers. The 3-dB lower output impedance of the real passive mixer is imitated on the replica side by a 3-dB attenuation of the I MHz tuning signal. The digital amplitude comparator consists of multipliers, filters, a clocked comparator, and a counter. The two outputs to be compared are first squared, and filtered to extract a DC voltage related to the amplitude of the signals. They are then fed into the clocked comparator which drives a 6-bit counter connected back to the passive mixers output capacitor to close the loop. If the transconductor output on the real side is lower than that on the replica side, then the counter counts down in order to lower the capacitance, and vice-versa. The tuning scheme implemented in this work is rather primitive and is only designed to illustrate the potential of tuning the output pole of the passive mixer. In a more advanced implementation, a successive approximation architecture [15] for the loop would reduce the required tuning time significantly. The 1 MHz signal required for tuning is generated externally to the chip, but in practice would be available from the crystal oscillator used in the frequency synthesizer.
V.
SIMULATION RESULTS

The principle of the tuning loop is illustrated in Fig. 6. The passive mixers are represented by variable resistors controlled by the LO signal. The output pole of the passive mixer consists of the resistance of the passive mixers and a bank of digitally controllable metal-insulator-metal (MIM) capacitors. A replica

The design has been implemented in a 0.18 11m RFCMOS process and sent for fabrication. The process features a 6 metal layers including a 2.5 11m thick top metal for inductor design, and both 2-metal and 3-metal MIM capacitors for high density capacitance. The overall performance of the receiver front end is shown in Table II and compared with recent literature. At this phase of the design, the proposed design compares favorably to recent literature, although the raw performance attained by [4] is still superior. It should be noted that in [4], several techniques were used which may or may not be

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2010 18th IEEEIIFIP International Conference on VLSI and System-on-Chip (VLSI-SoC 2010)

r--------------------------------------------r Router

Network Interface

:

FIFO_core_l

I

Core

I I I I L ____________________________________________ t

Figure 7.

Detailed structure of the Network Interface.

handshake protocol between NI and router. The Unpacking block can only receive flits when the packet is not completely

The data_ok signal also is responsible to control the

is sufficient to reach the rate required for the application. For this reason, the syntheses results were obtained for data width of the NI equal to 16. Two experiments were performed to evaluate the costs of the NI design. In the first one, it was verified the NI scalability with the variation in the number of cores that need to be synchronized. The second one consisted in the analysis about the impact of the buffer depth in the results. The H.264 decoder bitstream was considered to define those configurations. The Intra and IT
+

unpacked or when the FSM of the Unpacking block is in idle mode, and in this case, the NI is ready to receive a new packet (in all these cases data_ok is equal to 0). Each one of the N buffers has a signal empty that indicates

when the buffer has no data word. If there is at least one data word in each buffer and the core can receive a new data word and still if the buffer that stored the output data of the core is not full, the signal rd is enabled simultaneously for all the reading signals of the FIFOs. As the correct order of the packets are delivered for the NI due to the deterministic routing algorithm used, the data received of different nodes and stored in its respective buffers present the same sequence for a same position of the FIFO. Besides, the appropriate buffer depth should be verified according to the rates of the cores that will have its packets associated, i.e., the buffer depth should be large enough ensuring that no FIFO is full while another synchronization FIFO is empty. This solution can be used even when a large number of packets from many different cores need to be synchronized simultaneously. For that reason, the synchronization problem for the decoder of Fig. 3 can be solved with the proposed network interface as well as the partitioned decoder of Fig. 4. In the first case, one need to associate packets from 2 cores and, for this, 2 FIFOs are used. In the second case, packets from 3 cores need to be associated, using 3 FIFOs. After the synchronization of the packet received of each source core, the data can be sent to the destination core to start the computation of these input data. V.

IQ blocks need to send samples to the Adder

block. Each data word contains 32 bits (4 samples of 8 bits). The Adder block is able to perform 4 operations in parallel. Then the packets were configured to transport 4 samples at a time. For this reason, the widths of the FIFOs were defined as 32 bits. Based on the variation in the decoder traffic behavior, the FIFOs were defined to store up to 8 words, deep enough to tolerate discrepancies between traffic rates. To simulate a variation in the number of synchronized cores, we varied the number of 8-word-FIFOs in the synchronizer block. Table I presents the synthesis results of the network interfaces. For this analysis, we considered 3 possible cases of need to associate packets: we verify the synthesis results when packets from 2 up to 4 cores need to be synchronized. The results present a linear growth in terms of area and power consumption, directly related to the increase in the number of buffers. The maximum operational frequency decreases a little with the increased of the buffer depth, it occurs because the circuit critical path is in the buffer writing mechanism, which depends on the source identification signal source from the Unpacking block, as seen in Fig. 7. To have a complete evaluation of the network interface, the

RESULTS

FIFO depth was varied. In this second experiment, the constant parameter was the number of cores. As in the H.264 decoder, the number of cores to be synchronized was defined as 2. The graphs with the results of area, maximum frequency and power dissipation at 200MHz and at maximum frequency for the network interfaces are presented respectively in Fig. 8, 9, 10 and II.

The proposed network interface was described in VHDL, and we used the ModelSim tool to simulate the code. We analyzed the results to a CMOS 180nm process technology using the Cadence RTL Compiler tool. The network interfaces have been successfully integrated in the NoC. For the H.264 decoder, we verified that, using the channel width equal to 16

2010 18th IEEEIIFIP International Conference on VLSI and System-on-Chip (VLSI-SoC 2010)

385

100 .------. 50 '" :s
(; "

o

?

::: -100 "
.9" o

-60

-40

-20

o

20

Input Voltage (dB)
Fig. 10 IIP3 of the CSF with and without the mixer output pole. The input tones are at 5 MHz and 10 MHz offset from the desired signal.

allows for use of a low-noise IF section with relaxed linearity requirements. The proposed idea was implemented in a 0.18f.lm RFCMOS process and has been sent for fabrication. The proposed system compares favorably to recent literature while consuming the lowest power in the IF section among the designs.
REFERENCES [ I ] IEEE 802.15.4 Standard For Local and Metropolitan Area Networks, 2003. [2] W. Kluge, F. Poegel, H. Roller, M. Lange, T. Ferchland, L. Dathe, D. Eggert, "A Fully Integrated 2.4-GHz IEEE 802.15.4-Compliant Transceiver for ZigBeeTM Applications", IEEE Journal of Solid-State Circuits, vol. 41, issue 12, pp. 2767-2775, Dec, 2006. [3] B. G. Perumana, R. Mukhopadhyay, S. Chakraborty, C.-H. Lee, and J. Laskar, "A low-power fully monolithic subthreshold CMOS receiver with integrated LO generation for 2.4 GHz wireless PAN applications," IEEE J. Solid-State Circuits, vol. 43, no. 10, pp. 2229-2238, Oct. 2008. [4] B. W. Cook, A. Bemy, A. Molnar, S. Lanzisera, K. S. J. Pister, "Low? Power 2.4-GHz Transceiver With Passive RX Front-End and 400-mV Supply", IEEE Journal of Solid-State Circuits, vol. 41, no. 12, Dec. 2006, pp. 2757-2766. [5] M. Camus, B. Butaye, L. Garcia, M. Sie, B. PeDat, T. Parra, "A 5.4 mW/O.07 mm2 2.4 GHz Front end Receiver in 90 nm CMOS for IEEE 802.15.4 WPAN Standard", IEEE Journal of Solid-State Circuits, vol. 43, no. 6, pp. 1372-1383, June 2008. [6] T -K. Nguyen, N -J. Oh, V.-H. Hoang, S. -G. Lee, "A Low-Power CMOS Direct Conversion Receiver With 3-dB NF and 30-kHz Ricker Noise Comer for 915-MHz Band IEEE 802.15.4 ZigBee standard", IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 2, pp. 735-741, Feb, 2006. [7] I. Nam, K. Choi, J. Lee, H. -K. Cha, B. -I. Seo, K. Kwon, K. Lee, "A 2.4-GHz Low-Power Low-IF Receiver and Direct-Conversion Transmitter in 0.18-llm CMOS for IEEE 802.15.4 WPAN Applications", IEEE Transactions on Microwave Theory and Techniques, Yo. 55, No. 4, pp. 682- 689, April, 2007 [8] A. V. DO, C. C. Boon, M. A. Do, K. S. Yeo, A. Cabuk, "An Energy? Aware CMOS Receiver Front End for Low Power 2.4-GHz Applications", Accepted for Publication in IEEE Transactions on Circuits and Systems - I: Regular Papers, 20 I O. [9] P. Gorday, "802.15.4 Multipath", Internet: https:llmentor.ieee.org/802.15/file/04/15-04-0337-00-004b-802-15-4multipath.ppt, July 2004 [Oct. 2009]. [10] J. Crols, M. S. J. Steyaert, "Low-IF Topologies for High-Performance Analog Front Ends of Fully Integrated Receivers", IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Processing, vol. 45, no. 3, March 1998, pp. 269-282.

" [ I I ] A. A. Abidi, General Relations Between IP2, IP3, and Offsets in Differential Circuits and the Effects of Feedback", IEEE Transactions on Microwave Theory and Techniques, vol. 5 I, no. 5, May 2003, pp. 1610-1612. [12] A. V. Do, C. C. Boon, M. A. Do, K. S. Yeo, A. Cabuk, "A Subthreshold Low-Noise Amplifier Optimized for Ultra-Low-Power Applications in the ISM Band", IEEE Trans. on Microwave Theory and Tech., Vol. 56, No. 2, pp. 286-292, February 2008. [13] D. A. Johns, K. Martin, "Continuous-Time Filters", Analog Integrated Circuit Design, I I I River Street, Hoboken, NJ 07030, John Wiley and Sons, Inc, 1997, Chapter 15, pp. 574-647. [14] S. Chatterjee, Y. Tsividis, P. Kinget, "0.5-V Circuit Techniques and Their Application in OTA and Filter Design", IEEE Journal of Solid? State Circuits, vol. 40, no. 12, Dec 2005, pp. 2373-2387. [15] J. Sauerbrey, D. S. -Landsiedel, R. Thewes, "A O.5-V 1-IlW Successive Approximation ADC", IEEE Journal of Solid-State Circuits: Brief Papers, vol. 38, no. 7, July 2003, pp. 1261-1265. [16] B. W. Cook, "Low Energy RF Transceiver Design", PhD Thesis, University of California at Berkeley, May 161h, 2007. [17] c. C. McAndrew, "Validation of MOSFET Model Source-Drain Symmetry", IEEE Transactions on Electron Devices, vol. 53, no. 9, Sept. 2006, pp. 2202-2206. [18] H. Khatri, P. S. Gudem, L. E. Larson, "Distortion in Current? Commutating Passive CMOS Downconversion Mixers", IEEE Transactions on Microwave Theory and Techniques, vol. 57, no. I I , Nov. 2009, pp. 2671-2681.

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