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S6B3306X11 Data Sheet


Rev. 0.00

Data Sheet S6B3306X11

Preliminary

MOBILE DISPLAY DRIVER IC

Property of Samsung Electronics Co., Ltd Copyright ? 2007 Samsung Electronics, Inc. All Rights Reserved

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TRADEMARK & COPYRIGHT INFORMATION
Copyright ? 2007-2008 Samsung Electronics Co., Ltd. All Rights Reserved. This is proprietary information of Samsung Electronics Co., Ltd. No part of the information contained in this document maybe reproduced or used without the prior consent of Samsung Electronics Co., Ltd. Samsung Electronics Co., Ltd. San #24 Nongseo-Dong, Giheung-Gu, Yongin-City, Gyeonggi-Do, Korea Suwon 446-711 http://www.samsung.com/Products/Semiconductor/DisplayDriverIC

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REVISION HISTORY
Rev.# 0.00 Date 2008.09.19 Initial release for review History

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LIST OF CONTENTS
1. OVERVIEW ....................................................................................................................12
1.1. INTRODUCTION ................................................................................................................................ 12 1.2. PRODUCT OPTIONS ........................................................................................................................ 12 1.3. FEATURES ........................................................................................................................................ 13 1.4. BLOCK DIAGRAM ............................................................................................................................ 14 1.5. PAD INFORMATION ......................................................................................................................... 15 1.5.1. Configuration of Signal Pads ................................................................................................... 15 1.5.2. Bump ........................................................................................................................................ 16 1.5.3. Align Key .................................................................................................................................. 17 1.6. DESCRIPTION OF SIGNAL PADS ................................................................................................... 18 1.6.1. Power Supply Pins ................................................................................................................... 18 1.6.2. MPU Interface Pins .................................................................................................................. 19 1.6.3. Display Pins ............................................................................................................................. 20 1.6.4. Miscellaneous Control Pins...................................................................................................... 21

2. ELECTRICAL SPECIFICATION ....................................................................................23
2.1. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 23 2.2. DC CHARACTERISTICS................................................................................................................... 24 2.2.1. DC Characteristics (1).............................................................................................................. 24 2.2.2. DC Characteristics (2).............................................................................................................. 27 2.2.3. DC Characteristics (3).............................................................................................................. 28 2.2.4. DC Characteristics (4).............................................................................................................. 29 2.2.5. DC Characteristics (5).............................................................................................................. 30 2.3. AC CHARACTERISTICS................................................................................................................... 31 2.3.1. Read / Write Characteristics (8080-series MPU)..................................................................... 31 2.3.2. Read / Write Characteristics (6800-series MPU)..................................................................... 32 2.3.3. Serial Data Interface (4 Pin) Timing......................................................................................... 33 2.3.4. Serial Data Interface (3 Pin) Timing......................................................................................... 34 2.3.5. Reset Input Timing ................................................................................................................... 35

3. INTERFACE ...................................................................................................................37
3.1. MPU INTERFACE.............................................................................................................................. 37 3.1.1. Chip Select Input...................................................................................................................... 37 3.1.2. Parallel/Serial Interface ............................................................................................................ 37 3.2. PARALLEL INTERFACE (PS=”H”) .................................................................................................. 38 3.3. SERIAL INTERFACE (PS=”L”) ........................................................................................................ 40 3.3.1. 3-Pin SPI Interface (PS = "L" & MPU = "L")............................................................................. 41 3.3.2. 4-Pin Serial Interface (PS=”L” & MPU=”H”) ............................................................................. 41

4. FUNCTIONAL DESCRIPTION .......................................................................................43
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4.1. DISPLAY DATA RAM........................................................................................................................ 43 4.1.1. DDRAM Address Area Selection ............................................................................................. 43 4.1.2. RAM Addressing Count up....................................................................................................... 44 4.1.3. X address count mode (X address = 00h to 83h, Y address = 00h to 83h)............................. 44 4.1.4. Y address count mode (X address =00h to 83h, Y address = 00h to 83h).............................. 44 4.2. DISPLAY DIRECTION ....................................................................................................................... 46 4.2.1. COM Group Scan Mode........................................................................................................... 46 4.2.2. The relationship between COM outputs and display line of panel (CDIR=0) .......................... 47 4.2.3. Display Direction ...................................................................................................................... 48 4.3. POWER ON/OFF SEQUENCE .......................................................................................................... 51 4.3.1. Power On Sequence ................................................................................................................ 51 4.3.2. External Power Input Sequence .............................................................................................. 52 4.3.3. Power Off Sequence ................................................................................................................ 53 4.3.4. External Power Off Sequence.................................................................................................. 54 4.3.5. Wake up Sequence.................................................................................................................. 55 4.4. MTP CALIBRATION MODE .............................................................................................................. 56 4.4.1. Sequence for Setting the Modified Electronic Volume............................................................. 56 4.4.2. EEPROM Cell Structure........................................................................................................... 57 4.4.3. V1OUT Calibration flow............................................................................................................ 58 4.4.4. MTP Erase Sequence .............................................................................................................. 59 4.4.5. MTP Write Sequence ............................................................................................................... 60 4.4.6. Voltages and waveforms for MTP programming ..................................................................... 61

5. COMMAND.....................................................................................................................63
5.1. INSTRUCTIONS ................................................................................................................................ 63 5.2. INSTRUCTION DESCRIPTIONS....................................................................................................... 64 5.2.1. Non Operation (00H)................................................................................................................ 64 5.2.2. Oscillation Mode Set (02H) ...................................................................................................... 64 5.2.3. Driver Output Mode Set (10H) ................................................................................................. 65 5.2.4. Monitor Signal Control (18H) ................................................................................................... 66 5.2.5. Temperature Compensation Set (28H).................................................................................... 67 5.2.6. Contrast Control (2AH)............................................................................................................. 68 5.2.7. Standby Mode OFF (2CH) ....................................................................................................... 69 5.2.8. Standby Mode ON (2DH) ......................................................................................................... 70 5.2.9. Addressing Mode Set (30H)..................................................................................................... 71 5.2.10. Row Vector Mode Set (32H) .................................................................................................. 72 5.2.11. N-block Inversion Set (34H)................................................................................................... 73 5.2.12. Driving Mode Set (36H).......................................................................................................... 74 5.2.13. Entry Mode Set (40H) ............................................................................................................ 75 5.2.14. Row Address Area Set (42H)................................................................................................. 77 5.2.15. Column Address Area Set (43H) ........................................................................................... 78
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5.2.16. RAM Skip Area Set (45H) ...................................................................................................... 79 5.2.17. Display OFF (50H) ................................................................................................................. 80 5.2.18. Display ON (51H) ................................................................................................................... 81 5.2.19. Specified Display Pattern Set (53H) ...................................................................................... 82 5.2.20. Partial Display Mode Set (55H).............................................................................................. 83 5.2.21. Partial Display Start Line Set (56H), Partial Display End Line Set (57H) .............................. 84 5.2.22. Display Data Write/Read........................................................................................................ 86 5.2.23. Booster Boosting Set (70H) ................................................................................................... 87 5.2.24. Frame Frequency Set (7FH) .................................................................................................. 88 5.2.25. Status Read ........................................................................................................................... 89 5.2.26. Preliminary Instruction (8CH)................................................................................................. 90 5.2.27. CID Read Mode On (DAH) .................................................................................................... 90 5.2.28. CID Read Mode Off (DBH) .................................................................................................... 90 5.2.29. MTP Load (E5H) .................................................................................................................... 90 5.2.30. MTP Read Mode (E6H).......................................................................................................... 91 5.2.31. MTP Initial Disable (E8H)....................................................................................................... 91 5.2.32. MTP Initial Enable (E9H)........................................................................................................ 91 5.2.33. MTP Select Mode Off (EAH).................................................................................................. 91 5.2.34. MTP Select Mode On (EBH).................................................................................................. 91 5.2.35. Offset Volume Set (EDH) ....................................................................................................... 92 5.2.36. MTP Write Disable (EEH) ...................................................................................................... 92 5.2.37. MTP Write Enable (EFH) ....................................................................................................... 92 5.3. INSTRUCTION PARAMETERS......................................................................................................... 93 5.4. RESET OPERATION ......................................................................................................................... 94

6. APPENDIX .....................................................................................................................96
6.1. DISPLAY APPLICATIONS ................................................................................................................ 96 6.1.1. 132 Duty Display (ZIGZAG_MODE=0) .................................................................................... 96 6.1.2. 104 Duty Display (ZIGZAG_MODE=0) .................................................................................... 97 6.1.3. 96 Duty Display (ZIGZAG_MODE=0) ...................................................................................... 98 6.1.4. 80 Duty Display (ZIGZAG_MODE=0) ...................................................................................... 99 6.2. APPLICATION CIRCUIT ................................................................................................................. 100 6.2.1. Internal Power Mode .............................................................................................................. 100 6.2.2. External Power Mode............................................................................................................. 101 6.3. PAD CENTER COORDINATES ...................................................................................................... 102 6.4. EXTERNAL COMPONENT.............................................................................................................. 107 6.5. ABOUT THE POWER ON SEQUENCE .......................................................................................... 108 6.6. ABOUT THE WAKE UP SEQUENCE ............................................................................................. 109

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LIST OF FIGURES
FIGURE 1. FIGURE 2. FIGURE 3. FIGURE 4. FIGURE 5. FIGURE 6. FIGURE 7. FIGURE 8. FIGURE 9. FIGURE 10. FIGURE 11. FIGURE 12. FIGURE 13. FIGURE 14. FIGURE 15. FIGURE 16. FIGURE 17. FIGURE 18. FIGURE 19. FIGURE 20. FIGURE 21. FIGURE 22. FIGURE 23. FIGURE 24. FIGURE 25. FIGURE 26. FIGURE 27. FIGURE 28. FIGURE 29. FIGURE 30. FIGURE 31. FIGURE 32. FIGURE 33. FIGURE 34. FIGURE 35. FIGURE 36. FIGURE 37. FIGURE 38. FIGURE 39. FIGURE 40. FIGURE 41. FIGURE 42. FIGURE 43. FIGURE 44. FIGURE 45. FIGURE 46. FIGURE 47. FIGURE 48. FIGURE 49. FIGURE 50. FIGURE 51. FIGURE 52. BLOCK DIAGRAM.................................................................................................................... 14 S6B3306 CHIP PIN CONFIGURATION ................................................................................... 15 S6B3306 CHIP PAD CONFIGURATION.................................................................................. 16 COG ALIGN KEY COORDINATE............................................................................................. 17 V1 < VIN1*2-1.05 (@ILOAD=250UA, V1 MAXIMUM VOLTAGE=4V)..................................... 25 VCC < VIN1*M2-1.0 (@ILOAD=20UA, VCC MAXIMUM VOLTAGE=12V) ............................. 26 VEE > VIN1*(M3) + 1.0 (@ILOAD=20UA, VEE MINIMUM VOLTAGE=-8V) ........................... 26 VOLTAGE SHIFT...................................................................................................................... 28 OFFSET VOLTAGE .................................................................................................................. 29 DC CHARACTERISTICS FOR VOLTAGE LEVEL .................................................................. 30 PARALLEL INTERFACE (8080-SERIES MPU) TIMING DIAGRAM....................................... 31 PARALLEL INTERFACE (6800-SERIES MPU) TIMING DIAGRAM....................................... 32 SERIAL INTERFACE (4 PIN) TIMING DIAGRAM ................................................................... 33 SERIAL INTERFACE (3 PIN) TIMING DIAGRAM ................................................................... 34 RESET INPUT TIMING DIAGRAM ........................................................................................... 35 6800-SERIES MPU INTERFACE PROTOCOL (MPU=”H”) .................................................... 39 8080-SERIES MPU INTERFACE PROTOCOL (MPU=”L”)..................................................... 39 3-PIN SPI TIMING (RS IS NOT USED) .................................................................................... 41 4-PIN SERIAL INTERFACE TIMING........................................................................................ 41 DDRAM ADDRESS AREA ....................................................................................................... 43 X ADDRESS COUNT MODE .................................................................................................... 44 Y ADDRESS COUNT MODE .................................................................................................... 44 DISPLAY DATA RAM MAP...................................................................................................... 45 THE RELATIONSHIP BETWEEN COM OUTPUTS AND PANEL........................................... 46 DIRECTION OF COM OUTPUTS (ZIGZAG_MODE = 0) ......................................................... 48 DIRECTION OF COM OUTPUTS (ZIGZAG_MODE = 1) ......................................................... 49 THE RELATIONSHIP BETWEEN SEG OUTPUTS AND RGB COLOR.................................. 50 POWER ON SEQUENCE ......................................................................................................... 51 EXTERNAL POWER INPUT SEQUENCE ............................................................................... 52 POWER OFF SEQUENCE........................................................................................................ 53 EXTERNAL POWER OFF SEQUENCE ................................................................................... 54 WAKE UP SEQUENCE ............................................................................................................ 55 SEQUENCE FOR SETTING THE MODIFIED ELECTRONIC VOLUME ................................. 56 EEPROM BLOCK ..................................................................................................................... 57 MTP ERASE SEQUENCE ........................................................................................................ 59 MTP WRITE SEQUENCE ......................................................................................................... 60 VOLTAGES AND WAVEFORMS FOR MTP PROGRAMMING .............................................. 61 TEMPERATURE COMPENSATION......................................................................................... 67 MDI FUNCTION ........................................................................................................................ 75 RAM SKIP AREA...................................................................................................................... 79 PARTIAL DISPLAY MODE....................................................................................................... 83 PARTIAL DISPLAY START LINE SET .................................................................................... 84 PARTIAL DISPLAY END LINE SET ........................................................................................ 85 4,096 COLOR MODE DATA FORMAT .................................................................................... 86 DISPLAY APPLICATION (132 DUTY, ZIGZAG_MODE=0)..................................................... 96 DISPLAY APPLICATION (104 DUTY, ZIGZAG_MODE=0)..................................................... 97 DISPLAY APPLICATION (96 DUTY, ZIGZAG_MODE=0)....................................................... 98 DISPLAY APPLICATION (80 DUTY, ZIGZAG_MODE=0)....................................................... 99 APPLICATION CIRCUIT (80 SERIES MPU, INTERNAL POWER MODE) ........................... 100 APPLICATION CIRCUIT (80 SERIES MPU, EXTERNAL POWER MODE).......................... 101 ABOUT POWER ON SEQUENCE ......................................................................................... 108 ABOUT WAKE UP SEQUENCE............................................................................................. 109

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LIST OF TABLES
TABLE 1. TABLE 2. TABLE 3. TABLE 4. TABLE 5. TABLE 6. TABLE 7. TABLE 8. TABLE 9. TABLE 10. TABLE 11. TABLE 12. TABLE 13. TABLE 14. TABLE 15. TABLE 16. TABLE 17. TABLE 18. TABLE 19. TABLE 20. TABLE 21. TABLE 22. TABLE 23. TABLE 24. TABLE 25. TABLE 26. TABLE 27. TABLE 28. TABLE 29. TABLE 30. TABLE 31. TABLE 32. TABLE 33. TABLE 34. TABLE 35. TABLE 36. TABLE 37. TABLE 38. TABLE 39. TABLE 40. TABLE 41. TABLE 42. TABLE 43. TABLE 44. TABLE 45. TABLE 46. TABLE 47. TABLE 48. TABLE 49. TABLE 50. TABLE 51. TABLE 52. TABLE 53. TABLE 54. TABLE 55. TABLE 56. TABLE 57. TABLE 58. TABLE 59. TABLE 60. TABLE 61. TABLE 62. TABLE 63. TABLE 64. TABLE 65. TABLE 66. LIST OF S6B3306 OPTIONS.................................................................................................... 12 S6B3306 PAD DIMENSIONS ................................................................................................... 16 POWER SUPPLY PINS ............................................................................................................ 18 MPU INTERFACE PINS............................................................................................................ 19 TIMING SIGNAL PINS FOR MONITORING............................................................................. 20 LCD DRIVER OUTPUT PINS ................................................................................................... 20 OSCILLATOR AND POWER REGULATOR PINS .................................................................. 21 MTP PINS.................................................................................................................................. 21 TEST PINS ................................................................................................................................ 21 ABSOLUTE MAXIMUM RATING ............................................................................................. 23 DC CHARACTERISTICS .......................................................................................................... 24 DC CHARACTERISTICS FOR LCD DRIVER OUTPUTS........................................................ 27 DC CHARACTERISTICS FOR VOLTAGE SHIFT RANGE ..................................................... 28 DC CHARACTERISTICS FOR BIAS RATIO ........................................................................... 28 DC CHARACTERISTICS FOR VOLTAGE TOLERANCE AND OFFSET ............................... 29 DC CHARACTERISTICS FOR VOLTAGE LEVEL .................................................................. 30 AC CHARACTERISTICS (8080-SERIES PARALLEL MODE)................................................ 31 AC CHARACTERISTICS (6800-SERIES PARALLEL MODE)................................................ 32 SERIAL DATA INTERFACE TIMING ....................................................................................... 33 SERIAL DATA INTERFACE TIMING ....................................................................................... 34 AC CHARACTERISTICS (RESET MODE)............................................................................... 35 PARALLEL/SERIAL INTERFACE-MODE. .............................................................................. 37 MPU SELECTION FOR PARALLEL INTERFACE .................................................................. 38 PARALLEL DATA TRANSFER................................................................................................ 38 MPU SELECTION FOR SERIAL INTERFACE ........................................................................ 40 Y ADDRESS CONTROL........................................................................................................... 43 X ADDRESS CONTROL........................................................................................................... 43 THE RELATIONSHIP BETWEEN COM OUTPUTS AND DISPLAY LINE OF PANEL........... 47 MTP CALIBRATION FLOW...................................................................................................... 58 SPECIFICATION OF MTP PROGRAMMING TIMINGS........................................................... 61 SPECIFICATION OF MTP PROGRAMMING VOLTAGE ........................................................ 61 INSTRUCTION TABLE ............................................................................................................. 63 NON OPERATION .................................................................................................................... 64 OSCILLATION MODE SET ...................................................................................................... 64 DRIVER OUTPUT MODE SET ................................................................................................. 65 DLN REGISTER SET................................................................................................................ 65 MONITOR SIGNAL CONTROL ................................................................................................ 66 TEMPERATURE COMPENSATION SET................................................................................. 67 TCS REGISTER SET ................................................................................................................ 67 CONTRAST CONTROL............................................................................................................ 68 V1 VOLTAGE LEVEL BY CONTRAST SETTING ................................................................... 68 STANDBY MODE OFF ............................................................................................................. 69 FUNCTION AND PIN CONDITION AT STANDBY OFF .......................................................... 69 STANDBY MODE ON ............................................................................................................... 70 FUNCTION AND PIN CONDITION AT STANDBY ON ............................................................ 70 LCD DRIVING POWER OUTPUT CONDITION AT STANDBY ON......................................... 70 ADDRESSING MODE SET....................................................................................................... 71 ROW VECTOR MODE SET ...................................................................................................... 72 VEC REGISTER SET................................................................................................................ 72 N-BLOCK INVERSION SET ..................................................................................................... 73 POLARITY INVERSION SET.................................................................................................... 73 DRIVING MODE SET................................................................................................................ 74 ENTRY MODE SET................................................................................................................... 75 ENTRY MODE SET TABLE...................................................................................................... 76 ROW ADDRESS AREA SET .................................................................................................... 77 COLUMN ADDRESS AREA SET ............................................................................................. 78 RAM SKIP AREA SET.............................................................................................................. 79 DISPLAY OFF ........................................................................................................................... 80 BOOSTER AND DRIVERS OPERATION IN DISPLAY OFF................................................... 80 DISPLAY ON............................................................................................................................. 81 BOOSTER AND DRIVERS OPERATION IN DISPLAY ON..................................................... 81 SEPECIFIED DISPLAY PATTERN SET .................................................................................. 82 PARTIAL DISPLAY MODE SET............................................................................................... 83 PARTIAL DISPLAY START LINE SET .................................................................................... 84 PARTIAL DISPLAY END LINE SET ........................................................................................ 85 DISPLAY DATA WRITE/READ ................................................................................................ 86
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TABLE 67. TABLE 68. TABLE 69. TABLE 70. TABLE 71. TABLE 72. TABLE 73. TABLE 74. TABLE 75. TABLE 76. TABLE 77. TABLE 78. TABLE 79. TABLE 80. TABLE 81. TABLE 82. TABLE 83. TABLE 84. TABLE 85. TABLE 86. TABLE 87. TABLE 88. TABLE 89. TABLE 90. TABLE 91. TABLE 92. TABLE 93. TABLE 94. TABLE 95. TABLE 96. TABLE 97. TABLE 98.

16BIT ACCESS MODE ............................................................................................................. 86 8BIT ACCESS MODE ............................................................................................................... 86 16BIT ACCESS MODE ............................................................................................................. 86 8BIT ACCESS MODE ............................................................................................................... 86 BOOSTER BOOSTING SET..................................................................................................... 87 3RD BOOSTER BOOSTING RATIO ........................................................................................ 87 2ND BOOSTER BOOSTING RATIO ........................................................................................ 87 FRAME FREQUENCY SET ...................................................................................................... 88 FRAME FREQUENCY CONTROL ........................................................................................... 88 STATUS READ (MTP_RD=0, ST_RD_MODE=0).................................................................... 89 STATUS READ (MTP_RD=1, ST_RD_MODE=0).................................................................... 89 STATUS READ (MTP_RD=0, ST_RD_MODE=1).................................................................... 89 PRELIMINARY INSTRUCTION ................................................................................................ 90 CID READ MODE ON ............................................................................................................... 90 CID READ MODE OFF ............................................................................................................. 90 MTP LOAD ................................................................................................................................ 90 MTP READ MODE .................................................................................................................... 91 MTP INITIAL DISABLE............................................................................................................. 91 MTP INITIAL ENABLE.............................................................................................................. 91 MTP SELECT MODE ................................................................................................................ 91 MTP SELECT MODE ON.......................................................................................................... 91 OFFSET VOLUME SET ............................................................................................................ 92 OFFSET VOLUME CONTROL ................................................................................................. 92 MTP WRITE DISABLE.............................................................................................................. 92 MTP WRITE ENABLE............................................................................................................... 92 INSTRUCTION PARAMETER .................................................................................................. 93 PAD CENTER COORDINATES(–X11)................................................................................... 102 PAD CENTER COORDINATES (–X11, CONTINUED) .......................................................... 103 PAD CENTER COORDINATES (–X11, CONTINUED) .......................................................... 104 PAD CENTER COORDINATES (–X11, CONTINUED) .......................................................... 105 PAD CENTER COORDINATES (–X11, CONTINUED) .......................................................... 106 EXTERNAL COMPONENT..................................................................................................... 107

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Preface

About This Data Sheet
This document is to provide a complete Data Sheet of S6B3306 IC design. It also provides useful information to those who works on a panel module or a set.

IMPORTANT NOTICE
Precautions against Light
The conductivity of a semiconductor is strongly influenced by electro-magnetic radiation such as visible light, infrared light, ultraviolet light, or gamma radiation. When light is absorbed, electron-hole pairs are generated raising the conductivity of the material, eventually altering the electrical characteristics of the IC. Therefore, if the packages that expose IC’s to external light sources, such as COB, COG, TCP, and COF, are used, effective means to shield the IC from the light coming in all directions – top, bottom, and the sides – must be devised. Full observation of the following precautions is strongly recommended. 1. Make sure that the IC and substrate (board or glass) are protected from a stray light. 2. Always test and inspect products under the environment with no light penetration.

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CHAPTER 1

OVERVIEW
1.1 Introduction 1.2 Product Options 1.3 Features 1.4 Blcok Diagram 1.5 Pad Information 1.6 Description of Signal Pins

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1.

OVERVIEW

1.1. INTRODUCTION
S6B3306 is a mid-display-size-compatible driver for liquid crystal dot matrix gray-scale graphic systems. With on-chip RC oscillator circuit, the display-timing signal is generated without being sent from MPU. Also, it is capable of using 8bit/16bit data bus alternatively and operating with 68/80-series MPU in asynchronous. Due to the LCD driving signal (132 RGB X 132 output) corresponding to the display data and the internal bitmap display RAM of 132 ×132 ×16-bit, S6B3306 is capable of operating maximum 132 RGB x 132 dot LCD panels in low-power consumption. Being the segment RGB 3-output, one pixel is 16-bit data and S6B3306 can max display 65,536 color.

1.2. PRODUCT OPTIONS
S6B3306 offers more than one option in order to meet customer-specific functions from the customers. Table 1 describes its functions.

Table 1.

List of S6B3306 options Remarks Reference design of S6B3306X11

Options -X11

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S6B3306X11 Data Sheet_ Rev. 0.00

Preliminary

Mobile Display Driver IC

1.3. FEATURES
S6B3306 offers the following key features: z z Driver Output - 132 RGB x 132 Gray Scale Function - 65,536 color display of R: 32 gray scale, G: 64 gray scale, B: 32 gray scale - 4,096 color display of R: 16 gray scale, G: 16 gray scale, B: 16 gray scale z z On-chip Display Data RAM - Capacity: 132 x 16 x 132 = 278,784 bits Display Mode - Normal display mode: Entire duty displaying - Partial display mode: Partial duty displaying - Standby mode: Internal display clocks off z MPU (Microprocessor) Interface - 8-bit/16 bit parallel bi-directional interface with 6800-series or 8080-series - 3/4 Pin SPI (only write operation) z On-chip Low Power Analog Circuit - On-chip RC oscillator (Internal capacitor & resistor), external clock available - Voltage converter / Voltage regulator / Voltage follower - On-chip electronic contrast control z Operating Voltage Range - VDD3 = 1.65 to 3.0 [V] - VIN1: 2.4 to 3.0 [V], VIN1R: 2.4 to 3.0 [V] - Display operating voltage (V1): 2.8 to 4.0 [V] z z Low Power Consumption - 900 μA Typ. (Refer to DC CHARACTERISTICS (2)) Package Type - COG (Output Pad Pitch Min. 20 μm)

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S6B3306X11 Data Sheet_ Rev. 0.00

Preliminary

Mobile Display Driver IC

1.4. BLOCK DIAGRAM

Figure 1. Block Diagram

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S6B3306X11 Data Sheet_ Rev. 0.00

Preliminary

Mobile Display Driver IC

1.5. PAD INFORMATION
1.5.1. Configuration of Signal Pads

Figure 2. S6B3306 Chip pin configuration Page 15/109
2008-09-19

S6B3306X11 Data Sheet_ Rev. 0.00 1.5.2. Bump

Preliminary

Mobile Display Driver IC

Figure 3. S6B3306 Chip Pad Configuration

Table 2. S6B3306 Pad Dimensions Item Chip size Input Pad pitch Output Input Bumped Pad top size Output Pad No. (1~52,69~165) (53~68) (166~171,710~715) (172~709) (1~165) (166~171,710~715) (172~709) Height In Wafer Bumped pad height Tolerance In Chip Dimple Height Chip Thickness Note1: Scribe lane 80um included in this die size Note2: Wafer Thickness can be varies based on the Customer’s need.
- S6B3306●●●-●●●C : 300um

Size X 10970 60 85 30 20 40 ±2 120 ±2 10 ±2 15±3 Under 2 1.5 Note2 56 ±2 10 ±2 120 ±2 Y 670

Unit

μm

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S6B3306X11 Data Sheet_ Rev. 0.00

Preliminary

Mobile Display Driver IC

1.5.3. Align Key

Figure 4. COG Align Key Coordinate
Note: When designing COG pattern, ITO pattern must be prohibited on BUMP, COG Align Keys, DUMMY pads, TEST pads. If ITO pattern is used for routing over these areas, it can be happened pattern-short through bumped pattern on these areas.

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S6B3306X11 Data Sheet_ Rev. 0.00

Preliminary

Mobile Display Driver IC

1.6. DESCRIPTION OF SIGNAL PADS
1.6.1. Power Supply Pins

Table 3. Power Supply Pins
Name I/O Description

VDD3 VIN1R VDD VDDO VSS, VSSO VSSA, VSSB VSS3 V1IN V1OUT VMIN VMOUT V0IN VCC VRP VEE VRN VIN1, VIN1A VOUT45 VIN45

Supply Supply Supply Supply GND GND I O I O I I O I O I O I

I/O power supply. Internal regulator power supply This pin is connected to VIN1. Regulated power supply input pin for internal digital and DDRAM block. This pin is connected to REG_OUT outside the chip with stabilization capacitor. Oscillator Power Supply. Connect to VDD Ground I/O Ground (This pin is connected to VSS inside the chip and is the assistance pin for adjacent pins.) LCD segment high selected driving voltage input pin LCD segment high selected driving voltage output pin LCD common non-selected driving voltage input pin LCD common non-selected driving voltage output pin LCD segment low selected driving voltage input pin LCD common high selected driving voltage input pin LCD common high selected driving voltage output pin LCD common low selected driving voltage input pin The relationship between VCC, V1, VM, V0 and VEE: VCC > V1 > VM > V0(=VSS) > VEE (V1 - VM = VM – V0, VCC –VM = VM VEE) LCD common low selected driving voltage output pin Power supply for 1’st booster circuit and VM amp 1’st booster output pin Power supply for V1 amp. Recommend to connect this pin to VOUT45
V1 voltage adjustment pin. It is valid only when the external temperature compensation circuit is used. Otherwise, the ITO pattern is recommended not to be made for this pin. Note : V1T is recommended to connect the external Cap. with GND if much noise is injected into this pin.

V1T

I

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S6B3306X11 Data Sheet_ Rev. 0.00 1.6.2. MPU Interface Pins

Preliminary

Mobile Display Driver IC

Table 4. MPU Interface Pins
Name RSTB I/O I Description Reset input pin. When RSTB is “L”, initialization is executed. MPU interface select pin PS MPU PS MPU Description H L 8080-parallel interface H H 6800-parallel interface L L 3 pin SPI (Write only) L H 4 pin SPI (Write only) NOTE: In serial mode, WRB and RDB must be fixed to either VDD3 or VSS3. Chip select input pin. Data / instruction I/O is enabled only when CS1B is “L” and CS2 is “H”. When chip select is non-active, DB0 to DB15 are high impedance. Display Data / Instruction select input pin ? RS = “H”: DB0 to DB15 are display data ? RS = “L”: DB0 to DB7 are instruction data * When this pin is not used according to mode, these pins must be tied to VSS3. (In the case of 3Pin Serial I/F mode) Read / Write execution control pin PS WRB (R/W) I H MPU H MPU Type 6800-series WRB R/W Description Read / Write control input pin ? R/W = “H”: read ? R/W = “L”: write Write enable clock input pin The data on DB0 to DB15 are latched at the rising edge of the WRB signal.

I

CS1B CS2

I

RS

I

H

L

8080-series

WRB

Read / Write execution control pin PS MPU MPU Type RDB Description Read / Write control input pin ? R/W = “H”: When E is “H”, DB0 to DB15 are in an output status. ? R/W = “L”: The data on DB0 to DB15 are latched at the falling edge of the E signal. Read enable clock input pin When RDB is “L”, DB0 to DB15 are in an output status.

RDB (E)

I

H

H

6800-series

E

H

L

8080-series

RDB

DB[15:8] DB[7]/SDI DB[6]/SCL DB[5:0]

I/O

-DB[15:0]: 16-bit bi-directional data bus. -SDI: Serial data input pin. The data is latched at the rising edge of SCL. -SCL: Serial clock input pin. * When these pins are not used according to mode, these pins must be connected to VSS3.

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S6B3306X11 Data Sheet_ Rev. 0.00 1.6.3. Display Pins

Preliminary

Mobile Display Driver IC

Table 5. Timing signal Pins for monitoring Name CL PM FR I/O O O O Shift clock output pin Field delimiter output pin Liquid crystal alternating current output pin Description

Table 6.

LCD driver output pins Name I/O O O O O Description LCD driving segment outputs (Red or Blue) LCD driving segment outputs (Green) LCD driving segment outputs (Blue or Red) LCD common outputs

SEGA0 to 131 SEGB0 to 131 SEGC0 to131 COM0 to 131

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S6B3306X11 Data Sheet_ Rev. 0.00 1.6.4. Miscellaneous Control Pins

Preliminary

Mobile Display Driver IC

Table 7. Oscillator and Power Regulator Pins
Name I/O External clock input pin EXCLK I When an external input is used, it is input to this pin. But the internal oscillator is used, this pin is connected to VDD3 or VSS3. Internal voltage regulator output pin REG_OUT O This pin is connected to VDD, VDDO, VDDM outside the chip with stabilization capacitor. CID[1:0] I These pins assign ID[1:0] of status-read. This pin must be tied to VDD3 or VSS3. Description

Table 8. MTP pins
Name MTPV I/O I Description Power of writing MTP cell (When this pin is not used, this pin must be floating)

Table 9. Test pins
Name TEST[2] FUSE_EN MODE[1:0] I/O I I I Description Don’t use these pins. IC maker’s test pins These pins must be tied to VDD3. Don’t use this pin. IC maker’s test pin This pin must be tied to VDD3. Don’t use these pins. IC maker’s test pins These pins must be tied to VDD3. COM group scan mode select pin. - ZIGZAG_MODE = H : COM group scanning operates in zigzag. ZIGZAG_MODE I In this mode, ZIGZAG_MODE pin is tied to VDD3. - ZIGZAG_MODE = L : COM group scanning operates in sequence. In this mode, ZIGZAG_MODE pin is tied to VSS3. RTEST DUMMY I Don’t use this pin. IC maker’s test pin This pin must be tied to VSS3. This pin must be floating.

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CHAPTER 2

ELECTRICAL SPECIFICATION
2.1 Absolute Maximum Ratings 2.2 DC Characteristics 2.3 AC Characteristics

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2.

ELECTRICAL SPECIFICATION

2.1. ABSOLUTE MAXIMUM RATINGS

Table 10. Absolute maximum rating Item Supply Voltage range LCD Supply Voltage range Input Voltage range Operating Temperature range Storage Temperature range Symbol VDD3 VIN1  |VCC – VEE| Vin TOPR TSTR Rating -0.3 to +5.0 -0.3 to +5.0 25 - 0.3 to VDD3 +0.3 -30 to +70 Unit V V V V °C °C

-55 to +150

Note1: Absolute maximum rating is the limit value beyond which the IC may be broken. They do not assure operations. Note2: Operating temperature is the range of device-operating temperature. They do not guarantee chip performance. Note3: Absolute maximum rating is guaranteed when our company’s package used.

Caution
Stresses above these absolute maximum ratings may cause permanent damage. These are stress ratings only and functional operation at these conditions is not implied. Exposure to maximum rating conditions for extended periods may reduce device reliability.

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2.2. DC CHARACTERISTICS
2.2.1. DC Characteristics (1)

Table 11. DC characteristics (VSS = 0V, VDD3 = 1.65 to 3.0V, Ta = -30 to 70 °C)
Item Operating voltage Operating voltage Operating voltage Operating voltage Output voltage Symbol VDD3 VIN1 VIN45 2Vr REG_O UT VM Driving voltage input range (*1) VCC VEE Input voltage Output voltage High Low High Low VIH VIL VOH VOL IIL IOZ IOH = 0.5mA IOL = -0.5mA VIN = VDD or VSS VIN = VDD or VSS ( fFR=120Hz target ), Normal or Partial FOSC1 DSG=0, 132 display lines VDDO=1.5V, Temp=25°C 1534.5 1705 1875.5 kHz External power supply mode 2Vr = |VRP- VRN| REG_OUT voltage 1.4 7.0 -8.0 0.8VDD3 VSS 0.8VDD3 VSS -1.0 -3.0 Condition Min 1.65 2.4 2.4 14 2.8 1.5 ± 0.05 2.0 12.0 -4.5 VDD3 0.2VDD3 VDD3 0.2VDD3 +1.0 +3.0 Typ. Max 3.0 3.0 6.0 20 Uni t V V V V V V V V V V V V μA μA Remarks VDD3 VIN1, VIN1A VIN45 VRP, VRN REG_OUT VM VCC VEE

Input leakage current Output leakage current

Oscillator Frequency Tolerance

Driving voltage input range (*2)

V1 VM

2.8 1.4

-

4.0 2.0

V

(*1) The Driving voltage range depend on the operating voltage (VIN1). V1 < VIN1*2-1.05 VCC < VIN1*M2-1.0 VEE > VIN1*(M3) + 1.0 (@Iload=250uA, V1 maximum voltage=4V) (@Iload=20uA, VCC maximum voltage=12V) (@Iload=20uA, VEE minimum voltage=-8V)

? M2 and M3 is Booster Boosting Ratio. (See Booster Boosting Set (70H))

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V1 range (Iload=250uA)

4

3.5

V1
3 2.5 2 2.3 2.5 2.7 2.9 3.1

VIN1

Figure 5. V1 < VIN1*2-1.05 (@Iload=250uA, V1 maximum voltage=4V)

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Figure 6. VCC < VIN1*M2-1.0 (@Iload=20uA, VCC maximum voltage=12V)

Figure 7. VEE > VIN1*(M3) + 1.0 (@Iload=20uA, VEE minimum voltage=-8V)

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2.2.2. DC Characteristics (2)

Table 12. DC characteristics for LCD driver outputs (VSS = 0V, VDD3 = 1.65 to 3.0V, VIN1=2.4 to 3.0V, Ta = -30 to 70 °C) Item Symbo l SEG RON-Seg RON-Com Condition V1=3.0 V, V0=0V, Ta = 25°C, Iload=50uA VCC=9 V, VEE=-6.0V, Ta = 25°C, Iload=100uA VDD3=VIN1=3.0V, V1=3.0V, Bias=1/5, DC=x2, Current consumption Normal Mode Ta=25°C, Display line=132 IDD DSG=0 (1dummy) fOSC=1705kHz (fFR=120Hz) No load, No access, All white pattern 900 1100 μΑ VDD3 VIN1 Min Typ Max Unit kΩ kΩ
Remarks

Driver output resistance

-

1.5

2.0

SEGn

COM

-

1.5

2.0

COMn

* : “IDD” is determined from lowest power consumption for dc-dc converter.

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2.2.3. DC Characteristics (3)

Table 13. DC characteristics for voltage shift range (VSS = 0V, VDD3 = 1.65 to 3.0V, VIN1=2.4 to 3.0V, Ta = -30 to 70 °C) Item Symbo l Δ VRP Δ V1 Voltage shift range(*1) Δ VM Δ?VRN Condition Low current mode Isource = 20uA Low current mode Isource = 250uA Low current mode Isource,sink = 250uA Low current mode Isink = 20uA Min Typ Max Unit Remarks

-

-

200

mV

VRP

-

-

50

mV

V1

-

-

50

mV

VM

-

-

200

mV

VRN

(*1) Voltage shift means output voltage deference between output current = Iload and no-load. Refer to the following figure. (In case of source current mode)

Figure 8. Voltage shift

Table 14. DC characteristics for bias ratio Item Tolerance of Bias ratio Symbol Δ VRP_0 Δ VRN_0(*1) Condition No load Min -200 Typ Max +200 Unit mV Remarks VRP VRN

(*1) Tolerance of bias ratio definition Δ VRP_0 = (VRP - VM) – VM *Bias Δ VRN_0 = (VM - VRN) – VM *Bias

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2.2.4. DC Characteristics (4)

Table 15. DC characteristics for voltage tolerance and offset (VSS = 0V, VDD3 = 1.65 to 3.0V, VIN1=2.4 to 3.0V, Ta = 25°C) Item Temperature compensation Tolerance of Contrast step of V1 Symbo l ΔVt ΔVstep Contrast set = Voltage range ΔV1 ΔVM 7Fh Contrast set = 00h Item ||VRP-VM| -|VM Offset Voltage VRN|| ||V1-VM| |VM-V0|| A B V1 VM V1 VM Condition VDD3=VIN1=3.0V, 25°C to 70 °C Min Typ Max Unit %/°C mV V V V V Max Uni t mV Remarks

-0.02

-

+0.02

V1

3.13 3.95 1.95 2.75 1.35

6.27 4.0 2.00 2.80 1.40

9.41 4.05 2.05 2.85 1.45

V1 V1 VM V1 VM Ref

Condition Load current I Load = +20uA (VRP) I Load = -20uA (VRN) I Load = +100uA ( V1, VM ) I Load = +100uA (VRP) I Load = -100uA (VRN) Voltage range VRP=7.0~12 V V1=2.8~4.0V VM=1.4~2.0V VRN=-4.5~-8.0 V

100

Fig.1

50

mV

Fig.2

Figure 9. Offset Voltage

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2.2.5. DC Characteristics (5)

Table 16. DC characteristics for voltage level (VSS = 0V, VDD3 = 1.65 to 3.0V, VIN1=2.4 to 3.0V, Ta = -30 to 70 °C) Item V1OUT VMOUT Range Min 2.8 V 1.4 V Max (DC = X2.0) 4.0 V(*1) 2.0 V(*2)

Voltage Level

Figure 10. DC characteristics for voltage level

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2.3. AC CHARACTERISTICS
2.3.1. Read / Write Characteristics (8080-series MPU)

RS tAS80 CS1B (CS2) tPW L80(R), RDB, WRB 0.9V DD tf tDS80 DB0 to DB7 (Write) tACC80 DB0 to DB7 (Read) ** tPWL80(W) and tPWL80(R) is specified in the overlapped period when CS1B is low (CS2 is high) and WRB(RDB) is low. tOD80 0.1V DD tr tDH80 tPW L80(W ) tCY80 tPW H80(R), tPW H80(W ) tAH80

Figure 11. Parallel Interface (8080-series MPU) Timing Diagram

Table 17. AC Characteristics (8080-series Parallel Mode) (VSS=0V, VDD3 = 1.8V, Ta = -30 to +70°C) Item Address setup time Address hold time System cycle time(Write) Pulse width low for write Pulse width High for write Pulse width low for read Pulse width high for read Data setup time Data hold time Read access time Output disable time Signal RS Symbol tAS80 tAH80 tCY80 tPWL80(W) tPWH80(W) tPWL80(R) tPWH80(R) tDS80 tDH80 tACC80 tOD80 Condition Min 0 0 100 40 40 200 100 10 10 CL = 50 pF no load 20 150 Max Unit ns Ns Ns Ns Ns Ns Ns

WRB RDB

DB0 to DB15

NOTE : (tr + tf) < (tCY80 – tPWL80(W) – tPWH80(W) ) for write, (tr + tf) < (tCY80 – tPWLR80 – tPWHR80 ) for read

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2.3.2. Read / Write Characteristics (6800-series MPU)

RS,WRB
tAS68 tAH68

CS1B (CS2)
tEWHR68(R), tEWH68(W) tCY68 tEWL68(R), tEWL68(W)

RDB

0.1VDD tr

0.9VDD tf tDS68 tDH68

DB0 to DB7 (Write) DB0 to DB7 (Read)
tACC68 tOD68

** tEWH68(W) and tEWH68(R) is specified in the overlapped period when CS1B is low (CS2 is high) and RDB is high.

Figure 12. Parallel Interface (6800-series MPU) Timing Diagram

Table 18. AC Characteristics (6800-series Parallel Mode) (VSS=0V, VDD3 = 1.8V, Ta = -30 to +70°C) Item
Address setup time Address hold time System cycle time(Write) Enable width high for write Enable width low for write Enable width high for read Enable width low for read Data setup time Data hold time Read access time Output disable time DB0 to DB15 RDB RDB

Signa l
RS WRB

Symbol
tAS68 tAH68 tCY68 tEWH68(W) tEWL68(W) tEWH68(R) tEWL68(R) tDS68 tDH68 TACC68 tOD68

Condition

Min
0 0 100 40 40 200 100 10 10

Max

Unit
Ns Ns Ns Ns Ns

CL = 50 pF no load 20

150

Ns Ns

NOTE: (tr + tf) < (tCY68 – tEWH68(W) – tEWL68(W) ) for write, (tr + tf) < (tCY68 – tEWH68(R) – tEWL68(R) ) for read

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2.3.3. Serial Data Interface (4 Pin) Timing

CS1B (CS2) 0.1VDD

tCSS

tSCYC

tCSH 0.1VDD

tr

tSHW

tSLW
tSAS

SCL
tf

tSAH

RS
tSDS tSDH 0.9VDD 0.1VDD

SDI

0.9VDD 0.1VDD

Figure 13. Serial Interface (4 Pin) Timing Diagram

Table 19. Serial Data Interface Timing (VSS=0V, VDD3 = 1.8V, Ta = -30 to +70°C) Item
SCL Cycle Time SCL High Pulse Width SCL Low Pulse Width SDI Setup time SDI Hold time RS Setup time RS Hold time Chip Select Setup time

Signal
SCL SCL SCL SDI SDI RS RS CS1B (CS2) CS1B (CS2)

Symbol
tSCYC tSHW tSLW tSDS tSDH tSAS tSAH tCSS

Condition

Min
75 20 20 10 10 10 10 10

Unit
ns ns ns ns ns ns ns ns

Chip Select Hold time

tCSH

0

ns

NOTE: (tr + tf) < (tSCYC – tSHW – tSLW) for write,

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2.3.4. Serial Data Interface (3 Pin) Timing

CS1B (CS2) 0.1VDD

tCSS

tSCYC

tCSH 0.1VDD

tr

tSHW

tSLW
tSAS

SCL
tf tSDS tSDH 0.9VDD 0.1VDD

SDI

0.9VDD 0.1VDD

Figure 14. Serial Interface (3 Pin) Timing Diagram

Table 20. Serial Data Interface Timing (VSS=0V, VDD3 = 1.8V, Ta = -30 to +70°C) Item SCL Cycle Time SCL High Pulse Width SCL Low Pulse Width SDI Setup time SDI Hold time Chip Select Setup time Signal SCL SCL SCL SDI SDI CS1B (CS2) CS1B (CS2) Symbol tSCYC tSHW tSLW tSDS tSDH tCSS Condition Min 75 20 20 10 10 10 Unit ns ns ns ns ns ns

Chip Select Hold time

tCSH

0

ns

NOTE: (tr + tf) < (tSCYC – tsHW – tSLW) for write,

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2.3.5. Reset Input Timing
tRW RSTB tR Internal status During reset Reset complete

Figure 15. Reset Input Timing Diagram

Table 21. AC Characteristics (Reset mode) (VSS=0V, VDD3 = 1.8V, Ta = -30 to +70°C) Item Reset low pulse width Reset time Signal RSTB Symbol TRW tR Condition Min. 1000 Max. 1000 Unit ns ns

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CHAPTER 3

INTERFACE
3.1 MPU Interface 3.1 Parallel Interface 3.2 Serial Interface

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3.

INTERFACE

3.1. MPU INTERFACE

3.1.1. Chip Select Input There are CS1B and CS2 pins for chip selection. The S6B3306 can interface with an MPU only when CS1B is “L” and CS2 is “H”. When these pins are set to any other combination, RS, RDB, and WRB inputs are disabled and DB0 to DB15 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset.

3.1.2. Parallel/Serial Interface The S6B3306 has four types of interface with an MPU, which are two serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in Table 22. Table 22. Parallel/Serial Interface-Mode.
PS H H L L H CS1B CS2 MPU L CS1B CS2 6800-Series MPU 3–Pin SPI 4-Pin SPI CS1B CS2 MPU bus type 8080-Series MPU

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3.2. PARALLEL INTERFACE (PS=”H”)
The 8-bit/16-bit bi-directional data bus is used in parallel interface. The type of MPU is selected by MPU and the mode of data-bus is controlled by 16B register as shown in below. In accessing internal registers (RS = “L”), only DB[7:0] are valid. When 16B is high, DB[15:8] are high impedance. Table 23. MPU Selection for Parallel Interface
MPU L 16B L H L H CS1B CS1B CS2 CS2 RDB RDB WRB WRB Data Bus DB[15:0] DB[7:0] DB[15:0] DB[7:0] MPU bus type 8080-series MPU

H

CS1B

CS2

E

R/W

6800-series MPU

Table 24. Parallel Data Transfer RS H H L L 6800-series E H H H H R/W H L H L 8080-series RDB L H L H WRB H L H L Description Read display data Write display data Read out internal status register Write instruction data

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CS1B CS2 RS WRB RDB DB Command Write Data Write Status Read Data Read

Figure 16. 6800-Series MPU Interface protocol (MPU=”H”)

CS1B CS2 RS WRB RDB DB Command Write Data Write Status Read Data Read

Figure 17. 8080-Series MPU Interface Protocol (MPU=”L”)

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3.3. SERIAL INTERFACE (PS=”L”)
Communication with the MPU occurs via a clock-synchronized serial peripheral interface when PS is low. When using the serial interface, read operations are not allowed. When the chip select inputs are valid (CS1B = “L” & CS2 = “H”), the serial data is sent most significant bit first on the rising edge of a serial clock going into DB6 and processed as 8 bit parallel data on the eighth clock. Since the clock signal is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended. And Invalid, the internal shift register and the counter are reset. The serial interface type is selected by setting PS as shown in Table25.

Table 25. MPU Selection for Serial Interface PS L MPU L H CS1B CS1B CS1B CS2 CS2 CS2 RS By S/W D/I Serial Data DB[7] Serial Clock DB[6] SPI Mode 3-Pin 4-Pin

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3.3.1. 3-Pin SPI Interface (PS = "L" & MPU = "L") In 3-Pin SPI Interface mode, the first bit of serial 9 bits is used to indicate whether serial data input is display or instruction data instead of D/I pin. The serial data format consists of D/I (1bit) and DATA (8bits). For details, refer the Figure 18.

Chip Select
1 2 3 8

CS1B =L, CS2 = H
9 1 2 3 8 9

SCL(DB6) SDI(DB7)

0

DB7

DB6

DB1

DB0

1

DB7

DB0

DB1

DB0

RS

Instruction data

RS

Display data

Internal RS

Figure 18. 3-Pin SPI Timing (RS is not used)

3.3.2. 4-Pin Serial Interface (PS=”L” & MPU=”H”) In 4-pin SPI interface mode, RS pin is used for indicating whether serial data input is display or instruction data. Data is display data when RS is high and instruction data when RS is low. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. For details, refer the Figure 19.

Chip Select

l

CS1B=”L”, CS2=”H” DB2

SDI(DB7) SCL(DB6) RS

DB7

DB6

DB5

DB4

DB3

DB1

DB0

DB7

DB6

Figure 19. 4-Pin Serial Interface Timing

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CHAPTER 4

FUNCTIONAL DESCRIPTION
4.1 Display Data RAM 4.2 Display Direction 4.3 Power On/Off Sequence 4.4 MTP Calibration Mode

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4.

FUNCTIONAL DESCRIPTION

4.1. DISPLAY DATA RAM
The on-chip display data RAM of S6B3306 is a static RAM that is stored the data for the display. It is a 2,112 x 132 structure. It is controlled by 2 addresses, X and Y. And, RAM area selection and automatic address count up functions are accomplished by the internal instructions. 4.1.1. DDRAM Address Area Selection A part of DDRAM address area of S6B3306 can be accessed by X and Y address area settings. After setting RAM area, the addresses become the start address.

X-address

Y-address

Figure 20. DDRAM Address Area

Table 26. Y address Control DB7 Code P1 P2 0 DB6 1 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 0

Y start address set(Initial Status = 00H) Y end address set(Initial Status = 83H)

Table 27. X address Control DB7 Code P1 P2 0 DB6 1 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 1

X start address set (Initial status = 00H) X end address set (Initial status = 83H)

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4.1.2. RAM Addressing Count up By selecting the X address and Y address area by the internal instructions, the address counts up from its start address to end address after data access operation. When one address is equal to the end address, it returns to the start address. At this time, the other address is increased by 1.

4.1.3. X address count mode (X address = 00h to 83h, Y address = 00h to 83h)

X-address 00h 01h 02h 03h 00h 1 133 265 397 01h 02h 03h 04h 05h 06h 07h 08h 2 3 4 5 6 7 8 9 83h 132 264 396 528

Y-address

83h

17293
Figure 21. X address count mode

17424

4.1.4. Y address count mode (X address =00h to 83h, Y address = 00h to 83h)

X-address 00h 01h 02h 03h 04h 05h 06h 07h 08h 00h 1 133 265 397 529 661 793 925 1057 01h 2 02h 3 03h 4 83h 17293

Y-address

83h

132 264 396 528 660 792 924 1056 1188
Figure 22. Y address count mode

17424

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XA Address YA Address 00H 01H 02H 03H 04H 05H 06H 07H 08H - - - - - - 00H ------01H ------02H ------03H ------04H ------05H ------06H ------07H ------08H ------09H ------0AH ------0BH ------0CH ------0DH ------0EH ------0FH ----------74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 80H 81H 82H 83H -----------------------------------------------------------------------------------------------------

7DH 7EH 7FH 80H 81H 82H 83H

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Red Green Blue

Figure 23. Display Data RAM Map

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4.2. DISPLAY DIRECTION
4.2.1. COM Group Scan Mode There is ZIGZAG_MODE pin for COM group scan mode selection. ZIGZAG_MODE=0 COM group scanning operates in sequence.

ZIGZAG_MODE=1 COM group scanning operates in zigzag.

Figure 24. The relationship between COM outputs and Panel

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4.2.2. The relationship between COM outputs and display line of panel (CDIR=0) Table 28. The relationship between COM outputs and display line of panel
Display Line Number Line Number0 Line Number1 Line Number2 Line Number3 Line Number4 Line Number5 Line Number6 Line Number7 Line Number8 Line Number9 Line Number10 Line Number11 Line Number12 Line Number13 Line Number14 Line Number15 Line Number16 Line Number17 Line Number18 Line Number19 Line Number20 Line Number21 Line Number22 Line Number23 Line Number24 Line Number25 Line Number26 Line Number27 Line Number28 Line Number29 Line Number30 Line Number31 Line Number32 Line Number33 Line Number34 Line Number35 Line Number36 Line Number37 Line Number38 Line Number39 Line Number40 Line Number41 Line Number42 Line Number43 Line Number44
Common Number ZIGZAG_ MODE=0 Common Number ZIGZAG_ MODE=1

Display Line Number Line Number45 Line Number46 Line Number47 Line Number48 Line Number49 Line Number50 Line Number51 Line Number52 Line Number53 Line Number54 Line Number55 Line Number56 Line Number57 Line Number58 Line Number59 Line Number60 Line Number61 Line Number62 Line Number63 Line Number64 Line Number65 Line Number66 Line Number67 Line Number68 Line Number69 Line Number70 Line Number71 Line Number72 Line Number73 Line Number74 Line Number75 Line Number76 Line Number77 Line Number78 Line Number79 Line Number80 Line Number81 Line Number82 Line Number83 Line Number84 Line Number85 Line Number86 Line Number87 Line Number88 Line Number89

Common Number ZIGZAG_ MODE=0

Common Number ZIGZAG_ MODE=1

Display Line Number Line Number90 Line Number91 Line Number92 Line Number93 Line Number94 Line Number95 Line Number96 Line Number97 Line Number98 Line Number99 Line Number100 Line Number101 Line Number102 Line Number103 Line Number104 Line Number105 Line Number106 Line Number107 Line Number108 Line Number109 Line Number110 Line Number111 Line Number112 Line Number113 Line Number114 Line Number115 Line Number116 Line Number117 Line Number118 Line Number119 Line Number120 Line Number121 Line Number122 Line Number123 Line Number124 Line Number125 Line Number126 Line Number127 Line Number128 Line Number129 Line Number130 Line Number131

Common Number ZIGZAG_ MODE=0

Common Number ZIGZAG_ MODE=1

COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44

COM0 COM1 COM2 COM66 COM67 COM68 COM3 COM4 COM5 COM69 COM70 COM71 COM6 COM7 COM8 COM72 COM73 COM74 COM9 COM10 COM11 COM75 COM76 COM77 COM12 COM13 COM14 COM78 COM79 COM80 COM15 COM16 COM17 COM81 COM82 COM83 COM18 COM19 COM20 COM84 COM85 COM86 COM21 COM22 COM23

COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM80 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 COM89

COM87 COM88 COM89 COM24 COM25 COM26 COM90 COM91 COM92 COM27 COM28 COM29 COM93 COM94 COM95 COM30 COM31 COM32 COM96 COM97 COM98 COM33 COM34 COM35 COM99 COM100 COM101 COM36 COM37 COM38 COM102 COM103 COM104 COM39 COM40 COM41 COM105 COM106 COM107 COM42 COM43 COM44 COM108 COM109 COM110

COM90 COM91 COM92 COM93 COM94 COM95 COM96 COM97 COM98 COM99 COM100 COM101 COM102 COM103 COM104 COM105 COM106 COM107 COM108 COM109 COM110 COM111 COM112 COM113 COM114 COM115 COM116 COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 COM128 COM129 COM130 COM131

COM45 COM46 COM47 COM111 COM112 COM113 COM48 COM49 COM50 COM114 COM115 COM116 COM51 COM52 COM53 COM117 COM118 COM119 COM54 COM55 COM56 COM120 COM121 COM122 COM57 COM58 COM59 COM123 COM124 COM125 COM60 COM61 COM62 COM126 COM127 COM128 COM63 COM64 COM65 COM129 COM130 COM131

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4.2.3. Display Direction 4.2.3.1. CDIR (ZIGZAG_MODE=0) The CDIR flag of driver output mode set instruction selects the direction of common driver scanning. COM group scanning operates in sequence.

80 D isplay Lines (D LN =10) <C D IR =0>
COM 0 Line num ber 0

<C D IR = 1>
COM 0 COM 1 Line num ber 79

D isplay Area
C O M 38 Line num ber 38

D isplay A rea
C O M 41 C O M 66 Line num ber 39 Line num ber 38

C O M 66

Line num ber 39

D isplay Area
C O M 106 C O M 131 Line num ber 79 C O M 104 C O M 131

D isplay A rea
Line num ber 0

96 D isplay Lines (D LN =11) <C D IR =0>
COM 0 Line num ber 0 COM 0

<C D IR = 1>
Line num ber 95

D isplay Area
C O M 47 C O M 66 Line num ber 47 Line num ber 48 C O M 47 C O M 66

D isplay A rea
Line num ber 48 Line num ber 47

D isplay Area
C O M 113 C O M 131 Line num ber 95 C O M 113 C O M 131

D isplay A rea
Line num ber 0

104 D isplay Lines (D LN= 01) <C D IR =0>
COM 0 Line num ber 0 COM 0 COM 1

<C D IR = 1>
Line num ber 103

D isplay Area
C O M 50 C O M 66 Line num ber 50 C O M 53 C O M 66

D isplay A rea
Line num ber 51 Line num ber 50

Line num ber 51

D isplay Area
C O M 118 C O M 131 Line num ber 103 C O M 116 C O M 131

D isplay A rea
Line num ber 0

132 D isplay Lines (D LN= 00) <C D IR =0>
COM 0 Line num ber 0 COM 0

<C D IR = 1>
Line num ber 131

D isplay Area

D isplay A rea

C O M 131

Line num ber 131

C O M 131

Line num ber 0

Figure 25. Direction of COM outputs (ZIGZAG_MODE = 0)

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4.2.3.2. CDIR (ZIGZAG_MODE=1) The CDIR flag of driver output mode set instruction selects the direction of common driver scanning. COM group scanning operates in zigzag

80 D isplay Lines (D LN =10) <C D IR =0>
COM 0 Line num ber 0

<C D IR = 1>
COM 0 COM 1 Line num ber 79

D isplay Area
C O M 20 Line num ber 38

D isplay A rea
C O M 86 C O M 33 Line num ber 39 Line num ber 38

C O M 33

Line num ber 39

D isplay Area
C O M 118 C O M 131 Line num ber 79 C O M 53 C O M 131

D isplay A rea
Line num ber 0

96 D isplay Lines (D LN =11) <C D IR =0>
COM 0 Line num ber 0 COM 0

<C D IR = 1>
Line num ber 95

D isplay Area
C O M 89 C O M 33 Line num ber 47 Line num ber 48 C O M 89 C O M 33

D isplay A rea
Line num ber 48 Line num ber 47

D isplay Area
C O M 122 C O M 131 Line num ber 95 C O M 122 C O M 131

D isplay A rea
Line num ber 0

104 D isplay Lines (D LN= 01) <C D IR =0>
COM 0 Line num ber 0 COM 0 COM 1

<C D IR = 1>
Line num ber 103

D isplay Area
C O M 26 C O M 33 Line num ber 50 C O M 92 C O M 33

D isplay A rea
Line num ber 51 Line num ber 50

Line num ber 51

D isplay Area
C O M 124 C O M 131 Line num ber 103 C O M 59 C O M 131

D isplay A rea
Line num ber 0

132 D isplay Lines (D LN= 00) <C D IR =0>
COM 0 Line num ber 0 COM 0

<C D IR = 1>
Line num ber 131

D isplay Area

D isplay A rea

C O M 131

Line num ber 131

C O M 131

Line num ber 0

Figure 26. Direction of COM outputs (ZIGZAG_MODE = 1)

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4.2.3.3. SWP Function The SWP flag of Driver Output Mode Set instruction selects the swapping of segment display.

Figure 27. The relationship between SEG outputs and RGB color

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4.3. POWER ON/OFF SEQUENCE
4.3.1. Power On Sequence

Power On

Reset

Waiting for Releasing Reset

Standby mode OFF (OSC/DCDC1/AMP/ DCDC2/DCDC3 On automatically)
200ms

Set various registers and RAM data if needed ( MX,MY,Y/X, MDI,EXT,DIV,DLN, DC,FIM,FIP,N-block, PT,DSG,SGF, SGP,SGM, INC,VEC, Display Data )
100ms Display ON

Figure 28. Power on sequence

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4.3.2. External Power Input Sequence

Figure 29. External power input sequence

VDD3 must be applied earlier than VIN1/VIN1R/VIN1A or at least applied simultaneously with these signals. When C1 of table24. External component is 1μF, RSTB must be applied after VIN1/VIN1R/VIN1A have been applied. The applied time gap between VIN1/VIN1R/VIN1A and RSTB is minimum 2ms. As C1 becomes larger, this time gap must be increased. Otherwise function is not guaranteed.

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4.3.3. Power Off Sequence

Normal Case

Emergency Case

Standby ON ( Display Off, DCDC3 Off, DCDC2 Off, AMP Off, DCDC1 Off, OSC Off)

Turn off the power voltage

RSTB = L

Discharge

300ms

Trun off the power voltage

Stanby ON ( Display Off, DCDC3 Off, DCDC2 Off, AMP Off, DCDC1 Off, OSC Off)

Discharge

Turn off the power voltage suddenly Power voltage

GND

RSTB

The RSTB signal should be applied as soon as possible in the emergency case.

GND

COM/SEG Driver Output (VRP) GND

Note: When the signal of the hardware reset comes during the power-off period, COM/SEG output is forcibly lowered to the GND levels.

Figure 30. Power off sequence

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4.3.4. External Power Off Sequence

Figure 31. External power off sequence

VDD3 must be powered down later than VIN1/VIN1R/VIN1A or at least powered down simultaneously with these signals. VIN1/VIN1R/VIN1A must be powered down after RSTB have been powered down. The time gap of powered down between RSTB and VIN1/VIN1R/VIN1A is minimum 1ms. Otherwise function is not guaranteed.

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4.3.5. Wake up Sequence

Operation

Display OFF

Standby Mode On
(DCDC1/AMP/DCDC2/DCDC3 OFF, OSC OFF)

Standby Mode Off (Wake up)
(OSC/DCDC1/AMP/DCDC2/DCDC3 On automatically)

300ms Display ON

Figure 32. Wake up sequence

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4.4. MTP CALIBRATION MODE
4.4.1. Sequence for Setting the Modified Electronic Volume Next figure is a Block Diagram of Sequence for Setting the Modified Electronic Volume.

Electronic volume 7bit level (EV) ADDER 0 MUX Modified EV 7bit level (MEV)

MTP Writing Process

INST calibration 6bit offset (INST_OV) MTP calibration 6bit offset (MTP_OV)

1

MTP Select Mode ON/OFF

Figure 33. Sequence for Setting the Modified Electronic Volume Initially, MTP cell is not programmed and has 6'b000000 value. When the external reset is applied, MTP select mode is On. MEV is EV + MTP_OV. Since MTP_OV is 6'b00000, MEV is EV. For V1OUT calibration, the instruction "MTP select mode off" is executed, and then MEV is EV + OV and user can adjust MEV value using the instruction "Set offset volume register". When MEV overflows or underflows, MEV will be saturated. Repeat this step until end of the calibration. If V1OUT calibration is suitable, MTP writing process is executed, and then MTP cell is programmed and MTP_OV is programmed with OV. Finally, V1OUT calibration process is finished. Again, when the external reset is applied, MTP select mode is ON. MEV is EV + MTP_OV. Accordingly MEV is the EV that has always the offset with MTP_OV value. However, if programmed MTP_OV is unlike, the instruction "MTP select mode off" can be executed and then MEV will be EV + OV. Accordingly OV can be adjusted with instructions although MTP cell is programmed.

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4.4.2. EEPROM Cell Structure
MTP (Multi Time Programmable) has been implemented on the S6B3306. The EEPROM stores the offset volume for V1OUT calibration after the device has been assembled and calibrated on a LCD module. For MTP programming, MTPV pin is used. These pin should be available to on the module glass by ITO. The MTP block of the S6B3306 consists of 7 bits. 1 bit is used for MTP mode protection bit (MPRT), and 6 bits are used for V1OUT calibration (MOV5~MOV0). MPRT can be read or written automatically in this LSI.

4.4.2.1. EEPROM block

Figure 34. EEPROM block

4.4.2.2. Description
MPRT: The Offset Volume(OV) can be written to EEPROM cells only when MPRT bit = ‘0’ MOV5~MOV0: The MOV is used for calibrating the V1OUT voltage as an offset to the EV register value.

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4.4.3. V1OUT Calibration flow V1OUT may be calibrated with MTP in the following order.(ex : EV = 32, OV=-3) Table 29. MTP calibration flow
STEP 1. 2. 3. 4. 5. 0 0 0 0 0 6. 7. 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 0 0 0 0 1 1 RS RW DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0

Description
Execute MTP erase sequence. Apply external reset. (MTP data load) Set contrast control using instruction. (EV = 32) MTP select mode off by using the instruction. Set offset volume by using the instruction. (OV = -3) Repeat STEP 4. Until the end of the calibration. Standby on by using the instruction. Apply programming voltages for MTP

8.

programming. (MTPV=17V±500mV) Wait 1ms or more. 0 0 0 0 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 0 Preliminary Command.(8Ch) Preliminary parameter. (0Fh) Set MTP write enable. (Only available when MPRT= 0). Wait 100ms ~ 200ms. Set MTP write disable. Wait 1ms or more. Cut off programming voltages for MTP programming (MTPV) Apply external reset.

9. 0 10. 11. 12. 13. 0 0

After the external reset, the calibrated data are automatically transferred to the 6-bit reference voltage control register.
*MTP_WRITING PROCESS is available when MPRT is zero (if MPRT = 1, MTP cell could not be programmed).

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4.4.4. MTP Erase Sequence

Start

RESET

Set Standby Mode On (2Dh)

Supply MTPV(15V)

Set Preliminary Command (8Ch) Preliminary Parameter (0Fh)

Set MTP Initial Enable (E9h)

Wait 10us or more

Set MTP Write Enable (EFh)

Wait 100ms ~ 200ms

Set MTP Write Disable (EEh)

Wait 1ms or more

Cut Off MTPV

RESET

End

Figure 35. MTP erase sequence

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4.4.5. MTP Write Sequence

Start
Execute MTP Erase Sequence

RESET

Display On Flow

Bad
Set MTP Select Mode Off (EAh) Find Desired MTP Value (EDh)

Good
Set Standby Mode On (2Dh)

Supply MTPV(17V)

Wait 1ms or more
Set Preliminary Command (8Ch) Preliminary Parameter (0Fh)

Set MTP Write Enable (EFh)

Wait 100ms ~ 200ms

Set MTP Write Disable (EEh)

Wait 1ms or more

Cut Off MTPV(17V)

RESET

End

Figure 36. MTP write sequence

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4.4.6. Voltages and waveforms for MTP programming

Figure 37. Voltages and waveforms for MTP programming
* Note: MTP_OV is offset volume.

4.4.6.1. Specific timings Table 30. Specification of MTP programming timings Timing Tvs Tvh Tdws Tdwh Tpgm Min 1ms 1ms 10us 10us 100ms Max 200ms

4.4.6.2. MTPV Voltage Tolerance Table 31. Specification of MTP programming voltage Item Tolerance of MTPV Pgm Erase Write Min Typ 15 17 Max Unit V Remarks ± 500 mV

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CHAPTER 5

COMMAND
5.1 Instructions 5.2 Instruction Descriptions 5.3 Instruction Parameters 5.4 Reset function

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5.

COMMAND

5.1. INSTRUCTIONS
Table 32. Instruction Table
Instruction Name Non Operation Oscillation Mode Set Driver Output Mode Set Monitor Signal Control Temperature Compensation Set Contrast Control Standby Mode OFF Standby Mode ON Addressing Mode Set ROW Vector Mode Set N-block Inversion Set Driving Mode Set Entry Mode Set Row address Area Set Column address Area Set RAM skip Area Set Display OFF Display ON Specified Display Pattern Set Partial Display Mode Set Partial Display Start Line Set Partial Display End Line Set Booster Boosting Ratio Set Frame Frequency Set Preliminary Instruction CID Read Mode On CID Read Mode Off MTP Load MTP Read Mode MTP Initial Disable MTP Initial Enable MTP Select Mode Off MTP Select Mode On Offset Volume Set MTP Write Disable MTP Write Enable Display Data Write Display Data Read Status Read *: Don’t care RS WRB RDB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 DB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Hex. Parameter 15~8 * 0 0 0 0 0 0 0 0 00 * 0 0 0 0 0 0 1 0 02 1Byte * 0 0 0 1 0 0 0 0 10 1Byte * 0 0 0 1 1 0 0 0 18 1Byte * 0 0 1 0 1 0 0 0 28 1Byte * 0 0 1 0 1 0 1 0 2A 1Byte * 0 0 1 0 1 1 0 0 2C * 0 0 1 0 1 1 0 1 2D * 0 0 1 1 0 0 0 0 30 1Byte * 0 0 1 1 0 0 1 0 32 1Byte * 0 0 1 1 0 1 0 0 34 1Byte * 0 0 1 1 0 1 1 0 36 1Byte * 0 1 0 0 0 0 0 0 40 1Byte * 0 1 0 0 0 0 1 0 42 2Byte * 0 1 0 0 0 0 1 1 43 2Byte * 0 1 0 0 0 1 0 1 45 1Byte * 0 1 0 1 0 0 0 0 50 * 0 1 0 1 0 0 0 1 51 * 0 1 0 1 0 0 1 1 53 1Byte * 0 1 0 1 0 1 0 1 55 1Byte * 0 1 0 1 0 1 1 0 56 1Byte * 0 1 0 1 0 1 1 1 57 1Byte * 0 1 1 1 0 0 0 0 70 1Byte * 0 1 1 1 1 1 1 1 7F 1Byte * 1 0 0 0 1 1 0 0 8C 1Byte * 1 1 0 1 1 0 1 0 DA * 1 1 0 1 1 0 1 1 DB * 1 1 1 0 0 1 0 1 E5 * 1 1 1 0 0 1 1 0 E6 1Byte * 1 1 1 0 1 0 0 0 E8 * 1 1 1 0 1 0 0 1 E9 * 1 1 1 0 1 0 1 0 EA * 1 1 1 0 1 0 1 1 EB * 1 1 1 0 1 1 0 1 ED 1Byte * 1 1 1 0 1 1 1 0 EE * 1 1 1 0 1 1 1 1 EF Display Data Write Display Data Read 0 Status Data Read -

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Parameter: The number of parameter bytes that follows instruction data.

5.2. INSTRUCTION DESCRIPTIONS
5.2.1. Non Operation (00H) This instruction is non operation.

Table 33. Non operation
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0

0

0

0

0

0

0

0

5.2.2. Oscillation Mode Set (02H) Setting of internal function mode

Table 34. Oscillation mode set
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0 0

0 0

0 0

0 0

0 0

0 0

1 EXT

0 0

EXT: External clock selecting EXT = 0: Internal clock mode (Initial status) EXT = 1: External clock mode

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5.2.3. Driver Output Mode Set (10H) This instruction sets the display duty and direction.

Table 35. Driver output mode set
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0 0

0 0

0 DLN

1

0 MY

0 MX

0 SWP

0 CDIR

DLN: Display Line Number selecting (DLN = 00 initial status) Table 36. DLN register set
DB5 DB4 Display Duty

0 0 1 1

0 1 0 1

1/132 1/104 1/80 1/96

MY: Selection Row Address Count. MY = 0 : Row address increment (Initial status) MY = 1 : Row address decrement MX: Selection Column Address Count. MX = 0 : Column address increment (Initial status) MX = 1 : Column address decrement SWP: Swap segment output SEGAi and SEGCi This bit is for swapping the output of segment driver. SWP = 0 (Initial status) CDIR: Common Direction This bit is for controlling the direction of common driver. CDIR = 0 (Initial status)

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5.2.4. Monitor Signal Control (18H) This instruction configures the output enable and timing of monitor signal Table 37. Monitor signal control
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0 0

0 0

0 0

1 0

1 0

0 PM

0 CL

0 FR

PM: Enable to transfer field delimiter signal to output pin by active high PM = 0 (Initial status) CL: Enable to transfer shift signal to output pin by active high CL = 0 (Initial status) FR: Enable to transfer liquid crystal alternating signal to output pin by active high FR = 0 (Initial status)

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5.2.5. Temperature Compensation Set (28H) This Instruction sets up the driving voltage slope for temperature compensation. Table 38. Temperature compensation set
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0 0

0 0

1 0

0 0

1 0

0 0

0 TCS

0

TCS: Temperature compensation slope set (TCS = 00 initial status) Table 39. TCS register set
TCS[1:0] Temp. Coefficient Note

00 01 10 11

0.00%/°C -0.05%/°C -0.10%/°C -0.15%/°C

(Initial status)

Figure 38. Temperature compensation

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5.2.6. Contrast Control (2AH) This instruction updates the contrast control value in normal display mode and partial display mode.

Table 40. Contrast control
RS /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0

0

1

0

1

0

1

0

Contrast control value (0 to 127)

The relation between V1 voltage (typ.) and Contrast set value (00h initial status)

Table 41. V1 voltage level by contrast setting Contrast(HEX) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh V1 [V] 2.800 2.809 2.819 2.828 2.838 2.847 2.857 2.866 2.876 2.885 2.894 2.904 2.913 2.923 2.932 2.942 2.951 2.961 2.970 2.980 2.989 2.998 3.008 3.017 3.027 3.036 3.046 3.055 3.065 3.074 3.083 3.093 Contrast(HEX) 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh V1 [V] 3.102 3.112 3.121 3.131 3.140 3.150 3.159 3.169 3.178 3.187 3.197 3.206 3.216 3.225 3.235 3.244 3.254 3.263 3.272 3.282 3.291 3.301 3.310 3.320 3.329 3.339 3.348 3.357 3.367 3.376 3.386 3.395 Contrast(HEX) 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh V1 [V] 3.405 3.414 3.424 3.433 3.443 3.452 3.461 3.471 3.480 3.490 3.499 3.509 3.518 3.528 3.537 3.546 3.556 3.565 3.575 3.584 3.594 3.603 3.613 3.622 3.631 3.641 3.650 3.660 3.669 3.679 3.688 3.698 Contrast(HEX) 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh V1 [V] 3.707 3.717 3.726 3.735 3.745 3.754 3.764 3.773 3.783 3.792 3.802 3.811 3.820 3.830 3.839 3.849 3.858 3.868 3.877 3.887 3.896 3.906 3.915 3.924 3.934 3.943 3.953 3.962 3.972 3.981 3.991 4.000

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5.2.7. Standby Mode OFF (2CH) This instruction releases the standby mode.

Table 42. Standby mode off
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0

0

1

0

1

1

0

0

The internal statuses during standby off are as following: All commons output: VRP or –VR or VM All segments output: VSS or V1 All Analog power is generated automatically. (OSC. , Amp. , Booster(1’st, 2’nd, 3’rd)) Displaying clocks (FR, PM, CL): In operation

Table 43. Function and Pin condition at standby OFF
Function/Pin Condition

DC/DC booster(1’st,2’nd,3’rd) COM outputs SEG outputs

ON (Operate) VRP or VM or VRN V1 or VSS

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5.2.8. Standby Mode ON (2DH) This instruction enters the standby mode to reduce the power consumption to the static power consumption value (Initial status). The following instructions, standby off and display on, cause returning to the normal operation status.

Table 44. Standby mode on
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0

0

1

0

1

1

0

1

The internal statuses during standby on are as following: All common and segment output: VSS All analog power circuit : OFF (OSC. , Amp. , Booster(1’st,2’nd,3’rd)) Displaying clocks (FR, PM, CL) are held.

Table 45. Function and Pin condition at standby ON
Function/Pin Condition

DC/DC booster(1’st,2’nd,3’rd) COM outputs SEG outputs

OFF VSS Floating (discharged)

Table 46. LCD driving power output condition at Standby ON.
level Condition

VRP V1 VM VRN

VIN1 VSS VSS VSS

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5.2.9. Addressing Mode Set (30H)

Table 47. Addressing mode set
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0 0

0 0

1 GSM

1 DSG

0 SGF

0 SGP

0

0 SGM

GSM: Gray Scale Mode - 0: 65,536 color mode(Initial status) - 1: 4,096 color mode (refer to “Display data Write/Read”) DSG: Duty Adjust Setting - 0: Dummy subgroup is one subgroup (Initial status) - 1: Dummy subgroup is none SGF: Sub Group Frame Inversion mode setting - 0: SG Frame inversion OFF (Initial status) - 1: SG Frame inversion ON SGM: Sub Group inversion mode setting - 0: SG inversion OFF (Initial status) - 1: SG inversion ON SGP: Sub Group Phase mode setting - 00: Same phase in all pixels (Initial status) - 01: Different phase by 1pixel-unit - 10: Different phase by 2pixel-unit - 11: Different phase by 4pixel-unit

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5.2.10. Row Vector Mode Set (32H) Setting ROW function

Table 48. Row vector mode set
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0 0

0 0

1 0

1 0

0

0 INC

1

0 VEC

INC: Row Vector Increment Mode. This Parameter set up Row vector increment period (INC = 000 initial status)

Table 49. VEC register set
DB3 DB2 DB1 Row Vector Increment Period

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

Every subgroup Every 2subgroup Every 4subgroup Every 8subgroup Every 16subgroup Every 16subgroup Every 16subgroup Every subframe

VEC: ROW Vector Sequence Mode - 0: R1->R2->R3->R4 -> R1….. (initial status) - 1: R1->R3->R2->R4 -> R1…..

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Mobile Display Driver IC

5.2.11. N-block Inversion Set (34H) This instruction set up N block inversion for AC driving.

Table 50. N-block inversion set
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0 FIM

0 FIP

1 0

1

0

1 N-block inversion

0

0

FIM: Forcing Inversion Mode FIM = 0: Forcing Inversion OFF (Initial status) FIM = 1: Forcing Inversion ON FIP: Forcing Inversion Period FIP = 0: Forcing Inversion Period is one frame (Initial status) FIP = 1: Forcing Inversion Period is two frames N-block Inversion: This parameter indicates the basic period of polarity inversion. The whole period of polarity inversion is decided by FIM, FIP and this parameter. (N-block Inversion = 00h initial status)

Table 51. Polarity inversion set
DB7 DB6 DB5 DB4 – DB0 Polarity Inversion Period

x 0 : 0 1 : 1 1 : 1

X X : X 0 : 0 1 : 1

x x : x x : x x : x

0 1 : 31 1 : 31 1 : 31

Every frame Every 1 block : Every 31 blocks Every 1 block and every frame : Every 31 blocks and every frame Every 1 block and every 2 frames : Every 31 blocks and every 2 frames

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Mobile Display Driver IC

5.2.12. Driving Mode Set (36H) This instruction controls the internal driving mode.

Table 52. Driving mode set
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0 0

0 0

1 0

1 0

0 0

1 0

1 0

0 LFS

LFS: Low frame frequency set for low power consumption. LFS = 0 : Low frequency set OFF (Initial status) LFS = 1 : Low frequency set ON
note. fFR @(LFS=1) = fFR @(LFS=0) / 2

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Mobile Display Driver IC

5.2.13. Entry Mode Set (40H) Setting internal function mode.

Table 53. Entry mode set
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0 16B

1 0

0 0

0 0

0 0

0 MDI

0 Y/X

0 RMW

16B: Selection data bus width. 16B = 0: 16bit data bus (Initial status) 16B = 1: 8bit data bus MDI: Memory data inversion setting for low power consumption. MDI = 0: Memory data inversion OFF (Initial status) MDI = 1: Memory data inversion ON

<MDI=0> Display Data Write Display Data Read Data Bus Memory 00h 00h

<MDI=1> Display Data Write Display Data Read 00h FFh

00h

00h Figure 39. MDI function

FFh

00h

Y/X: Selection Address Count. Y/X = 0 : Column address count first (Initial status) Y/X = 1 : Row address count first RMW: Read modify write mode ON/OFF select RMW = 0 : Read modify write OFF (Initial status) RMW = 1: Read modify write ON. When this mode is on, X(Y) address of on-chip display RAM is not increment in reading display data but in writing display data.

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Mobile Display Driver IC

Table 54. Entry Mode Set Table
Display Data Direction Entry Mode Set Y/X MX MY Stored data into DDRAM Display Data Direction Entry Mode Set Y/X MX MY Stored data into DDRAM

column S S

column

E column E
X-Y Exchange Y-Mirror

row

Normal

0

0

0

row

X-Y Exchange

1

0

0

E column E

row

Y-Mirror

0

0

1

1

0

1

S column S
X-Y Exchange X-Mirror

row S column S row E

X-Mirror

0

1

0

row

1

1

0

E
column E
X-Y Exchange X-Mirror Y-Mirror

column E

row

row

X-Mirror Y-Mirror

0

1

1

1

1

1

S

S

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Mobile Display Driver IC

5.2.14. Row Address Area Set (42H) This instruction and parameter set up the Y address areas of the on-chip display data RAM.

Table 55. Row address area set
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1

1

0

0

0

0

1

0

Y start address set (Initial Status = 00H) Y end address set (Initial Status = 83H)

The current Y address of the on-chip display data RAM is the Y start address by setting this instruction. In Y address count mode (Y/X = “H”), the Y address is increased from Y start address to Y end address. When Y address is equal to the Y end address, the X address is increased by 1 and the Y address returns to Y start address. The Y start and Y end addresses must be set as a pair and Y start address must be less than Y end address.

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Mobile Display Driver IC

5.2.15. Column Address Area Set (43H) This instruction and parameter set up the X address areas of the on-chip display data RAM.

Table 56. Column address area set
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1

1

0

0

0

0

1

1

X start address set (Initial Status = 00H) X end address set (Initial Status = 83H)

The current X address of the on-chip display data RAM is the X start address by setting this instruction. In X address count mode (Y/X = “L”), the X address is increased from X start address to X end address. When X address is equal to the X end address, the Y address is increased by 1 and the X address returns to X start address. The X start and X end address must be set as a pair and X start address must be less than X end address.

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Mobile Display Driver IC

5.2.16. RAM Skip Area Set (45H) This instruction and parameter set up the X address areas of the on-chip display data RAM.

Table 57. RAM skip area set
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0 0

1 0

0 0

0 0

0 0

1 0

0 RSK

1

RSK: RAM Skip function ON/OFF set RSK = 00: No Skip (initial status) RSK = 01: X address 34h-4Fh skip ( 104 RGB ) RSK = 10: X address 3Ch-47h skip ( 120 RGB ) RSK = 11: X address 30h-53h skip ( 96RGB ) 5.2.16.1. RAM Skip Area Set RAM Skip Area Set can skip a part of RAM X-address area. After setting RAM skip area, X-address counts skip this area and count. In other words, X address after skip area is changed into X address which added a part for skip area.

Figure 40. RAM Skip Area

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5.2.17. Display OFF (50H) Turn the display OFF (Initial status). When display is off, all segment and common output are VSS level.

Table 58. Display off
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0

1

0

1

0

0

0

0

Function and Pin condition at Display OFF

Table 59. Booster and Drivers operation in display off
Function/Pin Condition

DC/DC booster (1’st, 2’nd, 3’rd) SEG and COM outputs

ON (Operate) VSS

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Mobile Display Driver IC

5.2.18. Display ON (51H) Turn the display ON. In case of being standby mode, this instruction does not work. This instruction is executed after Standby mode off

Table 60. Display on
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0

1

0

1

0

0

0

1

Function and Pin condition at Display ON

Table 61. Booster and Drivers operation in display on
Function/Pin Condition

DC/DC booster (1’st, 2’nd, 3’rd) COM outputs SEG outputs

ON(Operate) VRP or VM or VRN V1 or VSS

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Mobile Display Driver IC

5.2.19. Specified Display Pattern Set (53H) This instruction sets the specified display pattern.

Table 62. Sepecified display pattern set
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0 0

1 0

0 0

1 0

0 0

0 0

1 SDP

1

SDP: Specified Display Pattern set SDP = 00: Normal display (Initial status) SDP = 01: Reverse display: Display data reversing mode setting without the contents of the display RAM SDP = 10: Whole display pattern becomes OFF regardless of the RAM data. SDP = 11: Whole display pattern becomes ON regardless of the RAM data.

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5.2.20. Partial Display Mode Set (55H)

Table 63. Partial display mode set
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0 0

1 0

0 0

1 0

0 0

1 0

0 0

1 PT

PT: Partial Display ON/OFF PT = 0: Partial display OFF = Normal mode (Initial status) PT = 1: Partial display ON

Figure 41. Partial display mode

5.2.20.1. Operation in Partial Display Mode On scanning except partial display area - SEG output select V0 or V1 level depend on “FR” value. - All of COM output is fixed VM level. On scanning partial display area - It is equal to be in normal mode

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Mobile Display Driver IC

5.2.21. Partial Display Start Line Set (56H), Partial Display End Line Set (57H) These 2 instructions set the partial display area and it is possible to display a part as 3-lines unit. 5.2.21.1. Partial Display Start Line Set (56H)

Table 64. Partial display start line set
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0

1

0

1

0

1

1

0

Partial start line

EX) Partial start line : 0, 3, 6, 9, …, 126, 129 (3 Lines step)

Figure 42. Partial Display Start Line Set

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5.2.21.2. Partial Display End Line Set (57H)

Table 65. Partial Display End Line Set
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0

1

0

1

0

1

1

1

Partial end line

EX) Partial end line : 2, 5, 8, 11, …, 128, 131 (3 Lines step)

Figure 43. Partial Display End Line Set

Parameter set appoints display line number. Parameter size is able to be set as 3-line unit. Partial end line must set bigger number than Partial start line

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S6B3306X11 Data Sheet_ Rev. 0.00 5.2.22. Display Data Write/Read Table 66. Display Data Write/Read
RS WRB RDB
DB15 ~ DB8

Preliminary

Mobile Display Driver IC

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

1 1

0 1

1 0

Display RAM write in data Display RAM read out data

5.2.22.1. GSM = 0 (65,536 Color Mode) Table 67. 16bit access mode
15 1’st cycle 2’nd cycle R4 R4 14 R3 R3 13 R2 R2 12 R1 R1 11 R0 R0 10 G5 G5 9 G4 G4 8 G3 G3 7 G2 G2 6 G1 G1 5 G0 G0 4 B4 B4 3 B3 B3 2 B2 B2 1 B1 B1 0 B0 B0

Table 68. 8bit access mode
7 1’st cycle 2’nd cycle 3’rd cycle 4’th cycle R4 G2 R4 G2 6 R3 G1 R3 G1 5 R2 G0 R2 G0 4 R1 B4 R1 B4 3 R0 B3 R0 B3 2 G5 B2 G5 B2 1 G4 B1 G4 B1 0 G3 B0 G3 B0

5.2.22.2. GSM = 1 (4,096 Color Mode) Table 69. 16bit access mode
15 1’st cycle 2’nd cycle X X 14 X X 13 X X 12 X X 11 R3 R3 10 R2 R2 9 R1 R1 8 R0 R0 7 G3 G3 6 G2 G2 5 G1 G1 4 G0 G0 3 B3 B3 2 B2 B2 1 B1 B1 0 B0 B0

Table 70. 8bit access mode
7 1’st cycle 2’nd cycle 3’rd cycle 4’th cycle X G3 X G3 6 X G2 X G2 5 X G1 X G1 4 X G0 X G0 3 R3 B3 R3 B3 2 R2 B2 R2 B2 1 R1 B1 R1 B1 0 R0 B0 R0 B0

Figure 44. 4,096 Color Mode Data Format Page 86/109
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5.2.23. Booster Boosting Set (70H) This instruction sets the Booster Boosting ratio.

Table 71. Booster Boosting Set
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

0 0

0 0

1

1 NDC[2:0]

1

0

0 DC[2:0]

0

NDC[2:0] : Select 3rd Booster Boosting ratio Table 72. 3rd Booster Boosting Ratio DB5 0 0 0 0 1 1 1 1 DB4 0 0 1 1 0 0 1 1 DB3 0 1 0 1 0 1 0 1 Boosting ratio (M3) X-3 X-3 X-4 X-4 X-4 X-4 X-4 X-4 default Remark

DC[2:0] : Select 2rd Booster Boosting ratio Table 73. 2nd Booster Boosting Ratio DB2 0 0 0 0 1 1 1 1 DB1 0 0 1 1 0 0 1 1 DB0 0 1 0 1 0 1 0 1 Boosting ratio (M2) X3 X3 X4 X4 X5 X5 X5 X5 default Remark

The 2nd, 3rd Booster efficiency is changed according to M2 and M3. (See DC CHARACTERISTICS(1))

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5.2.24. Frame Frequency Set (7FH) This instruction sets the Frame Frequency.

Table 74. Frame Frequency Set
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 0

1

1

1

1 0

1 0

1 0

1 0

Frame Frequency ( Initial Status = 2H )

Table 75. Frame Frequency Control
DB[6] DB[5] DB[4] Frame Frequency[Hz] Remark

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

Don’t Use Don’t Use 198 148 119 99 85 74 Default

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5.2.25. Status Read MTP_RD = 0 : Normal Status Read (Initial status)

Table 76. Status Read (MTP_RD=0, ST_RD_MODE=0)
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

BUSY

Y/X

MPRT

0

PT

STB

REV

DP

This instruction indicates the internal status of the S6B3306. DP : (0 : Display OFF Status, 1 : Display ON Status ) REV : (0 : Display Image Non-Reversing, 1 : Display Image Reversing ) STB : (0 : Standby Mode OFF Status, 1 : Standby Mode ON Status ) PT Y/X : (0 : Partial Display Mode OFF Status, 1 : Partial Display Mode ON Status ) : (0: X-address Count Mode, 1 : Y-address Count Mode ) MPRT: (0: MTP cell non-protection status, 1: MTP cell protection status) BUSY: (0: No Busy, 1: Busy ) MTP_RD = 1: MTP Status Read

Table 77. Status Read (MTP_RD=1, ST_RD_MODE=0)
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

0

MPRT

MOV5

MOV4

MOV3

MOV2

MOV1

MOV0

This instruction indicates the MTP cell values of the S6B3306. (Refer to EEPROM CELL STRUCTURE)

ST_RD_MODE = 1: CID Status Read (refer to DAh command)

Table 78. Status Read (MTP_RD=0, ST_RD_MODE=1)
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

0

0

0

0

0

0

CID[1]

CID[0]

CID[1:0]: This instruction indicates the status of CID[1:0] pins

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5.2.26. Preliminary Instruction (8CH) This instruction is used to write / erase MTP cell. Table 79. Preliminary Instruction
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

1 0

0 0

0 0

0 0

1 1

1 1

0 1

0 1

Parameter default (F0h) 5.2.27. CID Read Mode On (DAH) CID read mode enable (ST_RD_MODE = 1). Table 80. CID Read Mode On
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

1

1

0

1

1

0

1

0

5.2.28. CID Read Mode Off (DBH) CID read mode disable (ST_RD_MODE = 0, initial status). Table 81. CID Read Mode Off
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

1

1

0

1

1

0

1

1

5.2.29. MTP Load (E5H) This command is used to load MTP cell.

Table 82. MTP Load
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

1

1

1

0

0

1

0

1

This command is valid at standby ON.

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S6B3306X11 Data Sheet_ Rev. 0.00 5.2.30. MTP Read Mode (E6H) This command is used to read MTP cell. Table 83. MTP Read Mode
RS WRB RDB DB7 DB6

Preliminary

Mobile Display Driver IC

DB5

DB4

DB3

DB2

DB1

DB0

1 0 0 1 0

1 0

1 0

0 0

0 0

1 0

1 0

0 MTP_R D

MTP_RD: MTP Read Mode - MTP_RD = 0: Normal Status Mode (Initial status) - MTP_RD = 1: MTP Status Mode 5.2.31. MTP Initial Disable (E8H) This command is used to turn MTP initial mode off. (Initial status) Table 84. MTP Initial Disable
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

1

1

1

0

1

0

0

0

5.2.32. MTP Initial Enable (E9H) This command is used to turn MTP initial mode on. Table 85. MTP Initial Enable
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

1

1

1

0

1

0

0

1

5.2.33. MTP Select Mode Off (EAH) This command is used to turn MTP select mode off. Table 86. MTP Select Mode
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

1

1

1

0

1

0

1

0

5.2.34. MTP Select Mode On (EBH) This command is used to turn MTP select mode on. (Initial status) Table 87. MTP Select Mode On
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

1

1

1

0

1

0

1

1

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S6B3306X11 Data Sheet_ Rev. 0.00 5.2.35. Offset Volume Set (EDH)

Preliminary

Mobile Display Driver IC

This command is used to set offset value x (-32 to +31) to electronic volume by 2s complement. Table 88. Offset Volume Set
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

1 0

1 0

1 OV5

0 OV4

1 OV3

1 OV2

0 OV1

1 OV0

Table 89. Offset Volume Control
OV5 OV4 OV3 OV2 OV1 OV0 Offset Volume

0 : 0 0 1

1 : 0 0 1 :

1 : 0 0 1 : 0

1 : 0 0 1 : 0

1 : 0 0 1 : 0

1 : 1 0 1 : 0

31

1 0 -1 : -32

1

0

5.2.36. MTP Write Disable (EEH) This command is used to cut off offset value (OV) from EEPROM cells. Table 90. MTP Write Disable
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

1

1

1

0

1

1

1

0

5.2.37. MTP Write Enable (EFH) This command is used to write offset value (OV) into EEPROM cells.

Table 91. MTP Write Enable
RS WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

0

1

1

1

1

0

1

1

1

1

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Mobile Display Driver IC

5.3. INSTRUCTION PARAMETERS
Table 92. Instruction Parameter
Instruction Oscillation Mode Set Driver Output Mode Set Monitor Signal control
Temperature Compensation Set

Hex 02H 10H 18H 28H 2AH 30H 32H 34H 36H 40H

Para 1 1 1 1 1 1 1 1 1 1

DB7 0 0 0 0 0 0 0 FIM 0 16B

DB6 0

DB5 0

DB4

DB3

DB2

DB1

DB0

Contrast Control Addressing Mode Set ROW Vector Mode Set N-block Inversion Set Driving Mode Set Entry Mode Set

Row address Area Set RAM Skip Area Set

42H 45H

2 1 0

Column Address Area Set Specified Display Pattern Set Partial Display Mode Set Partial Display Start Line Set Partial Display End Line Set Booster Boosting Set Frame Frequency Set MTP Read Mode Offset Volume Set

43H 53H 55H 56H 57H 70H 7FH E6H EDH

2 1 1 1 1 1 1 1 1 0 0 0 0 0 0

0 0 0 EXT 0 Initial value (00h) 0 DLN MY MX SWP CDIR Initial value (00h) 0 0 0 0 PM CL FR Initial value (00h) 0 0 0 0 0 TCS Initial value (00h) Contrast control value(0 to 127) Initial value (00h) 0 GSM DSG SGF SGP SGM Initial value (00h) 0 0 0 INC VEC Initial value (00h) FIP 0 N-block Inversion Initial value (00h) 0 0 0 0 0 0 LFS Initial value (00h) 0 0 0 0 MDI Y/X RMW Initial value (00h) Y Start address set Initial value (00h) Y end address set Initial value (83h) 0 0 0 0 0 RSK Initial value (00h) X start address set Initial value (00h) X end address set Initial value (83h) 0 0 0 0 0 SDP Initial value (00h) 0 0 0 0 0 0 PT Initial value (00h) Partial start line Initial value (00h) Partial end line Initial value (00h) 0 NDC[2:0] DC[2:0] Initial value (1Ch) Frame Frequency 0 0 0 0 Initial value (40h) MTP_R 0 0 0 0 0 0 D Initial value (00h) 0 OV5 OV4 OV3 OV2 OV1 OV0 Initial value (00h)

Parameter: The number of parameter bytes that follows instruction data.

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Mobile Display Driver IC

5.4. RESET OPERATION
When RSTB becomes “L”, following procedure is occurred.
z z z z z X start address: 0, X end address: 131 Y start address: 0, Y end address: 131 Display OFF Read Modify Write Mode OFF Function Mode Set ? ? ? ? ? ? ? ? z EXT = 0: Internal Oscillator Mode LFS = 0: Normal Frequency Mode 16B = 0: Data Bus Width 8bit Mode MDI = 0: Memory Data Inversion OFF MX = 0: Column Address increment MY = 0: Row Address increment Y/X = 0: X-address Count Mode Standby Mode ON

Duty Set ? Display Duty : DLN = 00 (132 duty)

z

N-block inversion ? ? FIM =0: Forcing Inversion OFF N-block inversion = 00H: frame inversion

z

Partial Display Mode ? PT = 0: Partial Display Mode OFF

z

Partial Display Area Set ? ? Partial start line = 00H Partial end line = 00H

z

Addressing Mode Set ? ? ? DSG = 0: Mode 0 SGF = 0: SG Frame Inversion OFF SGP = 00: Same phase in all pixels

z

Row Vector Mode Set ? ? INC =000: Increment every subgroup VEC=0: R1->R2->R3->R4->R1->…

z

CID Read Mode Off

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Mobile Display Driver IC

CHAPTER 6

APPENDIX
6.1 Display Application 6.2 Application Circuit 6.3 PAD Center Coordinates 6.4 External Component 6.5 About Power On Sequence 6.6 About Wake Up Sequence

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Mobile Display Driver IC

6.

APPENDIX

6.1. DISPLAY APPLICATIONS
By combination of DLN, CDIR, RSK bits setting, LCD panel and S6B3306 can be connected in many ways. 6.1.1. 132 Duty Display (ZIGZAG_MODE=0)

Figure 45. Display application (132 Duty, ZIGZAG_MODE=0)

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Mobile Display Driver IC

6.1.2. 104 Duty Display (ZIGZAG_MODE=0)

Figure 46. Display application (104 Duty, ZIGZAG_MODE=0)

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Mobile Display Driver IC

6.1.3. 96 Duty Display (ZIGZAG_MODE=0)

Figure 47. Display application (96 Duty, ZIGZAG_MODE=0)

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Mobile Display Driver IC

6.1.4. 80 Duty Display (ZIGZAG_MODE=0)

Figure 48. Display application (80 Duty, ZIGZAG_MODE=0)

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Mobile Display Driver IC

6.2. APPLICATION CIRCUIT
6.2.1. Internal Power Mode

VDD3 VDD3 VDD, VDDO REG OUT

VSS, VSSA, VSSB, VSSO

DB15 to DB0 /RD /WR MPU /CS1 CS2 D/I RST

DB15 to DB0 /RD /WR /CS1 CS2 D/I RST

VOUT45 VIN45

S6B3306
VIN1 VIN1, VIN1A, VIN1R EXCLK

V1OUT V1IN

VEE VRN

VMOUT VMIN

VCC VRP

Figure 49. Application Circuit (80 Series MPU, Internal Power Mode)

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Mobile Display Driver IC

6.2.2. External Power Mode

VDD3 VDD3 VDD VDD, VDDO REG OUT VSS, VSSA, VSSB, VSSO

DB15 to DB0 /RD /WR MPU /CS1 CS2 D/I RST

DB15 to DB0 /RD /WR /CS1 CS2 D/I RST `

VIN1 VIN1, VIN1A, VIN1R EXCLK VEE VRN V1OUT V1IN VMIN VMOUT VMIN VCC VRP VCC VEE

V1IN

Figure 50. Application Circuit (80 Series MPU, External Power Mode)

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Mobile Display Driver IC

6.3. PAD CENTER COORDINATES

Table 93. Pad Center Coordinates(–X11) [Unit: μm]
NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NAME DUMMY<1> DUMMY<2> MTPV MTPV V0IN V0IN RTEST VSS3 REGOUT REGOUT VDDO VDDO VDD VDD VDD VDD VDD3 VDD3 VDD3 VDD3 FUSE_EN V1IN V1IN V1IN V1IN V1OUT V1OUT V1T VMOUT VMOUT VMIN VMIN VMIN VMIN MODE<1> MODE<0> EXCLK VDD3 ZIGZAG_MODE VSS3 CL PM FR RSTB RS VSS3 WRB RDB VDD3 TEST<2> X -5157.5 -5097.5 -5037.5 -4977.5 -4917.5 -4857.5 -4797.5 -4737.5 -4677.5 -4617.5 -4557.5 -4497.5 -4437.5 -4377.5 -4317.5 -4257.5 -4197.5 -4137.5 -4077.5 -4017.5 -3957.5 -3897.5 -3837.5 -3777.5 -3717.5 -3657.5 -3597.5 -3537.5 -3477.5 -3417.5 -3357.5 -3297.5 -3237.5 -3177.5 -3117.5 -3057.5 -2997.5 -2937.5 -2877.5 -2817.5 -2757.5 -2672.5 -2587.5 -2502.5 -2442.5 -2382.5 -2322.5 -2262.5 -2202.5 -2142.5 Y -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 NO 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 NAME CID<1> CID<0> DB<0> DB<1> DB<2> DB<3> DB<4> DB<5> DB<6> DB<7> DB<8> DB<9> DB<10> DB<11> DB<12> DB<13> DB<14> DB<15> VSS3 PS VDD3 MPU VSS3 CS2 VDD3 CS1B VSSO VSSO VSS VSS VSS VSS VSS VSS VSS VSS VSSA VSSA VSSA VSSA VSS3 VSS3 VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB X -2082.5 -2022.5 -1962.5 -1877.5 -1792.5 -1707.5 -1622.5 -1537.5 -1452.5 -1367.5 -1282.5 -1197.5 -1112.5 -1027.5 -942.5 -857.5 -772.5 -687.5 -602.5 -542.5 -482.5 -422.5 -362.5 -302.5 -242.5 -182.5 -122.5 -62.5 -2.5 57.5 117.5 177.5 237.5 297.5 357.5 417.5 477.5 537.5 597.5 657.5 717.5 777.5 837.5 897.5 957.5 1017.5 1077.5 1137.5 1197.5 1257.5 Y -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 NO 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 NAME VIN1R VIN1R VIN1R VIN1R VIN1A VIN1A VIN1A VIN1A VIN1 VIN1 VIN1 VIN1 VIN1 VIN1 VIN1 VIN1 VIN1 VIN1 VIN45 VIN45 VIN45 VOUT45 VOUT45 VOUT45 DUMMY<3> DUMMY<4> DUMMY<5> DUMMY<6> VRN VRN VRN VEE VEE VEE DUMMY<7> VCC VCC VCC VRP VRP VRP DUMMY<8> DUMMY<9> DUMMY<10> DUMMY<11> DUMMY<12> DUMMY<13> DUMMY<14> DUMMY<15> DUMMY<16> X 1317.5 1377.5 1437.5 1497.5 1557.5 1617.5 1677.5 1737.5 1797.5 1857.5 1917.5 1977.5 2037.5 2097.5 2157.5 2217.5 2277.5 2337.5 2397.5 2457.5 2517.5 2577.5 2637.5 2697.5 2757.5 2817.5 2877.5 2937.5 2997.5 3057.5 3117.5 3177.5 3237.5 3297.5 3357.5 3417.5 3477.5 3537.5 3597.5 3657.5 3717.5 3777.5 3837.5 3897.5 3957.5 4017.5 4077.5 4137.5 4197.5 4257.5 Y -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260

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Mobile Display Driver IC

Table 94. Pad Center Coordinates (–X11, Continued) [Unit: μm]
NO 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 NAME DUMMY<17> DUMMY<18> DUMMY<19> DUMMY<20> DUMMY<21> DUMMY<22> DUMMY<23> DUMMY<24> DUMMY<25> DUMMY<26> DUMMY<27> V0IN V0IN DUMMY<28> DUMMY<29> DUMMY<30> COM<14> COM<13> COM<12> COM<11> COM<10> COM<9> COM<8> COM<7> COM<6> COM<5> COM<4> COM<3> COM<2> COM<1> COM<0> COM<15> COM<16> COM<17> COM<18> COM<19> COM<20> COM<21> COM<22> COM<23> COM<24> COM<25> COM<26> COM<27> COM<28> COM<29> COM<30> COM<31> COM<32> COM<33> X 4317.5 4377.5 4437.5 4497.5 4557.5 4617.5 4677.5 4737.5 4797.5 4857.5 4917.5 4977.5 5037.5 5097.5 5157.5 5370 5350 5330 5310 5290 5270 5250 5230 5210 5190 5170 5150 5130 5110 5090 5070 5050 5030 5010 4990 4970 4950 4930 4910 4890 4870 4850 4830 4810 4790 4770 4750 4730 4710 4690 Y -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 -260 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 NO 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 NAME COM<34> COM<35> COM<36> COM<37> COM<38> COM<39> COM<40> COM<41> COM<42> COM<43> COM<44> COM<45> COM<46> COM<47> COM<48> COM<49> COM<50> COM<51> COM<52> COM<53> COM<54> COM<55> COM<56> COM<57> COM<58> COM<59> COM<60> COM<61> COM<62> COM<63> COM<64> COM<65> DUMMY<31> DUMMY<32> DUMMY<33> DUMMY<34> SEGC<0> SEGB<0> SEGA<0> SEGC<1> SEGB<1> SEGA<1> SEGC<2> SEGB<2> SEGA<2> SEGC<3> SEGB<3> SEGA<3> SEGC<4> SEGB<4> X 4670 4650 4630 4610 4590 4570 4550 4530 4510 4490 4470 4450 4430 4410 4390 4370 4350 4330 4310 4290 4270 4250 4230 4210 4190 4170 4150 4130 4110 4090 4070 4050 4030 4010 3990 3970 3950 3930 3910 3890 3870 3850 3830 3810 3790 3770 3750 3730 3710 3690 Y 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 NO 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 NAME SEGA<4> SEGC<5> SEGB<5> SEGA<5> SEGC<6> SEGB<6> SEGA<6> SEGC<7> SEGB<7> SEGA<7> SEGC<8> SEGB<8> SEGA<8> SEGC<9> SEGB<9> SEGA<9> SEGC<10> SEGB<10> SEGA<10> SEGC<11> SEGB<11> SEGA<11> SEGC<12> SEGB<12> SEGA<12> SEGC<13> SEGB<13> SEGA<13> SEGC<14> SEGB<14> SEGA<14> SEGC<15> SEGB<15> SEGA<15> SEGC<16> SEGB<16> SEGA<16> SEGC<17> SEGB<17> SEGA<17> SEGC<18> SEGB<18> SEGA<18> SEGC<19> SEGB<19> SEGA<19> SEGC<20> SEGB<20> SEGA<20> SEGC<21> X 3670 3650 3630 3610 3590 3570 3550 3530 3510 3490 3470 3450 3430 3410 3390 3370 3350 3330 3310 3290 3270 3250 3230 3210 3190 3170 3150 3130 3110 3090 3070 3050 3030 3010 2990 2970 2950 2930 2910 2890 2870 2850 2830 2810 2790 2770 2750 2730 2710 2690 Y 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228

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Mobile Display Driver IC

Table 95. Pad Center Coordinates (–X11, Continued) [Unit: μm]
NO 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 NAME SEGB<21> SEGA<21> SEGC<22> SEGB<22> SEGA<22> SEGC<23> SEGB<23> SEGA<23> SEGC<24> SEGB<24> SEGA<24> SEGC<25> SEGB<25> SEGA<25> SEGC<26> SEGB<26> SEGA<26> SEGC<27> SEGB<27> SEGA<27> SEGC<28> SEGB<28> SEGA<28> SEGC<29> SEGB<29> SEGA<29> SEGC<30> SEGB<30> SEGA<30> SEGC<31> SEGB<31> SEGA<31> SEGC<32> SEGB<32> SEGA<32> SEGC<33> SEGB<33> SEGA<33> SEGC<34> SEGB<34> SEGA<34> SEGC<35> SEGB<35> SEGA<35> SEGC<36> SEGB<36> SEGA<36> SEGC<37> SEGB<37> SEGA<37> X 2670 2650 2630 2610 2590 2570 2550 2530 2510 2490 2470 2450 2430 2410 2390 2370 2350 2330 2310 2290 2270 2250 2230 2210 2190 2170 2150 2130 2110 2090 2070 2050 2030 2010 1990 1970 1950 1930 1910 1890 1870 1850 1830 1810 1790 1770 1750 1730 1710 1690 Y 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 NO 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 NAME SEGC<38> SEGB<38> SEGA<38> SEGC<39> SEGB<39> SEGA<39> SEGC<40> SEGB<40> SEGA<40> SEGC<41> SEGB<41> SEGA<41> SEGC<42> SEGB<42> SEGA<42> SEGC<43> SEGB<43> SEGA<43> SEGC<44> SEGB<44> SEGA<44> SEGC<45> SEGB<45> SEGA<45> SEGC<46> SEGB<46> SEGA<46> SEGC<47> SEGB<47> SEGA<47> SEGC<48> SEGB<48> SEGA<48> SEGC<49> SEGB<49> SEGA<49> SEGC<50> SEGB<50> SEGA<50> SEGC<51> SEGB<51> SEGA<51> SEGC<52> SEGB<52> SEGA<52> SEGC<53> SEGB<53> SEGA<53> SEGC<54> SEGB<54> X 1670 1650 1630 1610 1590 1570 1550 1530 1510 1490 1470 1450 1430 1410 1390 1370 1350 1330 1310 1290 1270 1250 1230 1210 1190 1170 1150 1130 1110 1090 1070 1050 1030 1010 990 970 950 930 910 890 870 850 830 810 790 770 750 730 710 690 Y 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 NO 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 NAME SEGA<54> SEGC<55> SEGB<55> SEGA<55> SEGC<56> SEGB<56> SEGA<56> SEGC<57> SEGB<57> SEGA<57> SEGC<58> SEGB<58> SEGA<58> SEGC<59> SEGB<59> SEGA<59> SEGC<60> SEGB<60> SEGA<60> SEGC<61> SEGB<61> SEGA<61> SEGC<62> SEGB<62> SEGA<62> SEGC<63> SEGB<63> SEGA<63> SEGC<64> SEGB<64> SEGA<64> SEGC<65> SEGB<65> SEGA<65> SEGC<66> SEGB<66> SEGA<66> SEGC<67> SEGB<67> SEGA<67> SEGC<68> SEGB<68> SEGA<68> SEGC<69> SEGB<69> SEGA<69> SEGC<70> SEGB<70> SEGA<70> SEGC<71> X 670 650 630 610 590 570 550 530 510 490 470 450 430 410 390 370 350 330 310 290 270 250 230 210 190 170 150 130 110 90 70 50 30 10 -10 -30 -50 -70 -90 -110 -130 -150 -170 -190 -210 -230 -250 -270 -290 -310 Y 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228

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Preliminary

Mobile Display Driver IC

Table 96. Pad Center Coordinates (–X11, Continued) [Unit: μm]
NO 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 NAME SEGB<71> SEGA<71> SEGC<72> SEGB<72> SEGA<72> SEGC<73> SEGB<73> SEGA<73> SEGC<74> SEGB<74> SEGA<74> SEGC<75> SEGB<75> SEGA<75> SEGC<76> SEGB<76> SEGA<76> SEGC<77> SEGB<77> SEGA<77> SEGC<78> SEGB<78> SEGA<78> SEGC<79> SEGB<79> SEGA<79> SEGC<80> SEGB<80> SEGA<80> SEGC<81> SEGB<81> SEGA<81> SEGC<82> SEGB<82> SEGA<82> SEGC<83> SEGB<83> SEGA<83> SEGC<84> SEGB<84> SEGA<84> SEGC<85> SEGB<85> SEGA<85> SEGC<86> SEGB<86> SEGA<86> SEGC<87> SEGB<87> SEGA<87> X -330 -350 -370 -390 -410 -430 -450 -470 -490 -510 -530 -550 -570 -590 -610 -630 -650 -670 -690 -710 -730 -750 -770 -790 -810 -830 -850 -870 -890 -910 -930 -950 -970 -990 -1010 -1030 -1050 -1070 -1090 -1110 -1130 -1150 -1170 -1190 -1210 -1230 -1250 -1270 -1290 -1310 Y 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 NO 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 NAME SEGC<88> SEGB<88> SEGA<88> SEGC<89> SEGB<89> SEGA<89> SEGC<90> SEGB<90> SEGA<90> SEGC<91> SEGB<91> SEGA<91> SEGC<92> SEGB<92> SEGA<92> SEGC<93> SEGB<93> SEGA<93> SEGC<94> SEGB<94> SEGA<94> SEGC<95> SEGB<95> SEGA<95> SEGC<96> SEGB<96> SEGA<96> SEGC<97> SEGB<97> SEGA<97> SEGC<98> SEGB<98> SEGA<98> SEGC<99> SEGB<99> SEGA<99> SEGC<100> SEGB<100> SEGA<100> SEGC<101> SEGB<101> SEGA<101> SEGC<102> SEGB<102> SEGA<102> SEGC<103> SEGB<103> SEGA<103> SEGC<104> SEGB<104> X -1330 -1350 -1370 -1390 -1410 -1430 -1450 -1470 -1490 -1510 -1530 -1550 -1570 -1590 -1610 -1630 -1650 -1670 -1690 -1710 -1730 -1750 -1770 -1790 -1810 -1830 -1850 -1870 -1890 -1910 -1930 -1950 -1970 -1990 -2010 -2030 -2050 -2070 -2090 -2110 -2130 -2150 -2170 -2190 -2210 -2230 -2250 -2270 -2290 -2310 Y 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 NO 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 NAME SEGA<104> SEGC<105> SEGB<105> SEGA<105> SEGC<106> SEGB<106> SEGA<106> SEGC<107> SEGB<107> SEGA<107> SEGC<108> SEGB<108> SEGA<108> SEGC<109> SEGB<109> SEGA<109> SEGC<110> SEGB<110> SEGA<110> SEGC<111> SEGB<111> SEGA<111> SEGC<112> SEGB<112> SEGA<112> SEGC<113> SEGB<113> SEGA<113> SEGC<114> SEGB<114> SEGA<114> SEGC<115> SEGB<115> SEGA<115> SEGC<116> SEGB<116> SEGA<116> SEGC<117> SEGB<117> SEGA<117> SEGC<118> SEGB<118> SEGA<118> SEGC<119> SEGB<119> SEGA<119> SEGC<120> SEGB<120> SEGA<120> SEGC<121> X -2330 -2350 -2370 -2390 -2410 -2430 -2450 -2470 -2490 -2510 -2530 -2550 -2570 -2590 -2610 -2630 -2650 -2670 -2690 -2710 -2730 -2750 -2770 -2790 -2810 -2830 -2850 -2870 -2890 -2910 -2930 -2950 -2970 -2990 -3010 -3030 -3050 -3070 -3090 -3110 -3130 -3150 -3170 -3190 -3210 -3230 -3250 -3270 -3290 -3310 Y 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228

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Preliminary

Mobile Display Driver IC

Table 97. Pad Center Coordinates (–X11, Continued) [Unit: μm]
NO 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 NAME SEGB<121> SEGA<121> SEGC<122> SEGB<122> SEGA<122> SEGC<123> SEGB<123> SEGA<123> SEGC<124> SEGB<124> SEGA<124> SEGC<125> SEGB<125> SEGA<125> SEGC<126> SEGB<126> SEGA<126> SEGC<127> SEGB<127> SEGA<127> SEGC<128> SEGB<128> SEGA<128> SEGC<129> SEGB<129> SEGA<129> SEGC<130> SEGB<130> SEGA<130> SEGC<131> SEGB<131> SEGA<131> DUMMY<35> DUMMY<36> DUMMY<37> DUMMY<38> COM<131> COM<130> COM<129> COM<128> COM<127> COM<126> COM<125> COM<124> COM<123> COM<122> COM<121> COM<120> COM<119> COM<118> X -3330 -3350 -3370 -3390 -3410 -3430 -3450 -3470 -3490 -3510 -3530 -3550 -3570 -3590 -3610 -3630 -3650 -3670 -3690 -3710 -3730 -3750 -3770 -3790 -3810 -3830 -3850 -3870 -3890 -3910 -3930 -3950 -3970 -3990 -4010 -4030 -4050 -4070 -4090 -4110 -4130 -4150 -4170 -4190 -4210 -4230 -4250 -4270 -4290 -4310 Y 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 NO 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 NAME COM<117> COM<116> COM<115> COM<114> COM<113> COM<112> COM<111> COM<110> COM<109> COM<108> COM<107> COM<106> COM<105> COM<104> COM<103> COM<102> COM<101> COM<100> COM<99> COM<98> COM<97> COM<96> COM<95> COM<94> COM<93> COM<92> COM<91> COM<90> COM<89> COM<88> COM<87> COM<86> COM<85> COM<84> COM<83> COM<82> COM<81> COM<66> COM<67> COM<68> COM<69> COM<70> COM<71> COM<72> COM<73> COM<74> COM<75> COM<76> COM<77> COM<78> X -4330 -4350 -4370 -4390 -4410 -4430 -4450 -4470 -4490 -4510 -4530 -4550 -4570 -4590 -4610 -4630 -4650 -4670 -4690 -4710 -4730 -4750 -4770 -4790 -4810 -4830 -4850 -4870 -4890 -4910 -4930 -4950 -4970 -4990 -5010 -5030 -5050 -5070 -5090 -5110 -5130 -5150 -5170 -5190 -5210 -5230 -5250 -5270 -5290 -5310 Y 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 NO 701 702 703 NAME COM<79> COM<80> DUMMY<39> X -5330 -5350 -5370 Y 228 228 228

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Preliminary

Mobile Display Driver IC

6.4. EXTERNAL COMPONENT

Table 98. External Component
Name C1 C2 C3 C4 C5 C6 Device Capacitors Capacitors Capacitors Capacitors Capacitors Capacitors Value 1.0μF to 4.7μF 1.0μF 1.0μF 1.0μF 1.0μF 1.0μF Item REG_OUT – GND VOUT45 – GNDVm – GND V1 – GND VRP – GND VRN – GND Maximum Rating Voltage of Capacitors 3V 10V 3V 10V 18V 18V

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Preliminary

Mobile Display Driver IC

6.5. ABOUT THE POWER ON SEQUENCE
The wait time at Power On Sequence is needed for stabilization wait time of outputs which are VRP, VRN, V1, VM. But, if those outputs are stabilized before Display On, the wait time is changeable.

Power On

Reset

Waiting for Releasing Reset

Standby mode OFF (OSC/DCDC1/AMP/DCDC2 /DCDC3 On automatically)

Outputs Stabilization Wait Time Needed

Set various registers and RAM data if needed ( MX,MY,Y/X, MDI,EXT,DIV,DLN, DC,FIM,FIP,N-block, PT,DSG,SGF, SGP,SGM, INC,VEC, Display Data )

Display ON

Figure 51. About Power On Sequence

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Preliminary

Mobile Display Driver IC

6.6. ABOUT THE WAKE UP SEQUENCE
The wait time at Wake Up Sequence is needed for stabilization wait time of outputs which are VRP, VRN, V1, VM. But, if those outputs are stabilized before Display On, the wait time is changeable.

Operation

Display OFF

Standby Mode On
(DCDC1/AMP/DCDC2/DCDC3 OFF, OSC OFF)

Standby Mode Off (Wake up)
(OSC/DCDC1/AMP/DCDC2/DCDC3 On automatically)

Display ON

Figure 52. About Wake Up Sequence

Page 109/109

2008-09-19


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