A Novel Topology for Multiple Output DCDC
Converters
for One Cycle
Ravindra Kumar Singh
Control
Abstract Multiple output DCDC converters are needed by many utilities/ industry applications. The Control of multiple output converters is challenging as the outputs derive the input power form same source and thereby have a strong coupling. A novel Multiple Output converters topology has been proposed to have decoupling of outputs from individual control. A closed loop control has been suggested for the proposed converter such that it has one cycle control of all the outputs individually as well as collectively. The proposed converter has been verified by simulation and experimentation. Index Terms DCDC Converter.
I. INTRODUCTION
Amultiple output DCDC converter consists of a DC power supply and desired number of regulated outputs [1]. The power circuit of such converters normally employs either a fly back or a forward topology. The control design of such converters is aimed at providing constant and stable output voltages at individual outputs for admissible load and input voltage changes. Regulation against load changes of individual outputs by different methods reported in literature has a minimum error in all outputs. In [25] the circuit topology has been modified to minimize the errors in outputs by magnetic coupling of secondary windings and other techniques. For example, in [3] one output is operated in Continuous Conduction Mode (CCM) and the other output in Discontinuous Conduction Mode (DCM) to regulate load perturbations in a dual converter. However the uncontrolled charging of the capacitors does not allow independent regulation of the outputs and the response time is a strong function of the system parameters and the switching frequency. The problem of uncontrolled charging has been solved in [6] for a single output DCDC converter. The conventional fly back converter has a diode for each output. A switch to obtain better control has replaced the diode in this topology. The same principle has been applied to multipleoutput converter to obtain to obtain a new converter topology. In the proposed converter shown in Fig. 1, each of the two outputs can be individually controlled between specified minimum and maximum instantaneous values. An energy recovery winding has been used to facilitate opening of all switches whenever
Ravindra kumar singh is working as a senior Lecturer with the department of Electrical Engineering, Motilal Nehru National Institute of Technology, Allahabad, U.P, India.
0780397711/06/$20.00 C 2006 IEEE.
required. If we call load switch along with capacitor and load as load subcircuit, additional load subcircuits will realize a converter topology with increased numbers of outputs. Fig.1 (a) can be called nonisolated topology as the fly back inductor is common to input and output, whereas Fig.1 (b) is isolated topologies for two output converter. The proposed converter has been analyzed in steady state operating condition to obtain input/output voltage relationship. Small signal analysis has been carried out to characterize the dynamic behavior of the converter. It has been found that the dynamic model is to complex for designing a physically realizable controller. Moreover, the proposed converter can be used for achieving faster dynamic response. Therefore, a hysteresis based closed loop controller has been designed. The proposed converter has response time of utmost one cycle of the hysteresis controlled closed loop converter frequency.
II. STEADY STATE ANALYSIS The steady state operation of the converter in constant frequency has been shown by switching diagram in Fig. 2. The switching diagram is drawn for two outputs. The main switch builds flux in the core and is used in sequence by two load circuits in intervals d1T and d2T respectively to charge the output capacitors. This may be followed by an energy recovery
interval derT if required. However, the energy recovery period can be positioned in any place in a switching periodT. The average output voltages are not a function of the position of the energy recovery position as can be seen from (1). The isolated version of the converter topology also has almost the same switching diagram. The output voltage governs the turn ratio of the main transformer. The equivalent circuit diagrams for different switching intervals are shown in Fig. 3. The inductorcharging interval DT starts with closing of main switch and opening of load switches Sw1 & Sw2. The equivalent circuit is shown in Fig. 3(a). This interval follows by opening of the main switch Swm and closing of load switch Sw1 (equivalent circuit given in Fig. 3(b). This interval is followed by closing of load switch Sw2 and opening of Sw1 (equivalent circuit given in Fig. 3(c). Fig. 3(d) shows the equivalent circuit of the optional energy recovery interval, where all the switches are open. The core mmf is defined as 3 = NuiLl + N2ier . Fig. 2 shows the waveform of
the converter operating at constant frequency (1/ T ) in CCM.
VI'"
L
(a)
R
V.
L
C<
CR+
(b)
L1(c)
I(R
(d)
V
+
VoI
1V02
(a) NonIsolated multiple output fly back converters
Sv4
Vdc
1
SIQ
VoI
V02
The increment in flux takes place when the inductor is connected to dc source and it reduces when the stored. magnetic energy of the inductor is used for charging capacitor connected across the load and during the energy recovery interval. The voltage waveform across the inductor represented by VL1 is shown in Fig. 2. The magnitudes of the average inductor voltage in different duty intervals are marked in the figure. Applying voltsec balance across the inductor gives
VodT + aVdCdERT
=
Fig. 3. Equivalent circuits of multiple output converter for (a) main Switch conducting (b) load Switch 1 conducting (c) load switch 2 conducting and (d) Energy recovery operating.
VdCDT
C24
Fig. 1. Proposed converter in twotopology.
(b) Isolated multiple output fly back converters
Where a = N1 I N2 is the turn ratio of the coupled inductors as stated above. Inductors L1 and L2 are assumed to be tightly coupled and there is no leakage. The expression for output voltages are obtained by voltsec balance of the core and charge balance across capacitors. The resulting equation are given by
Vol
Sw
,
D ader
F
V02
F
D ader
(1)
DT
. T
j(k+I)T
Id d + d
to
d2 d2
d2 1
R2
tl
2d d2
B2
22
1±
t2
d) Rj
t3
dI
1
2dT
.
dER
t
1, 1
2,
A3, B3
_r
Nlim + N2iER
VoI
V02
Lo 1I~~
VII
The single output modified buckboost converter has three independent subintervals, namely main switch ON interval, load switch ON subinterval and energy recovery interval. The main and load duty ratio is independently controllable. The state space equations for the converter in different intervals of the converter operation can be written from equivalent circuits shown in Fig. 3. The small signal model for a multiple subinterval has been derived in section 2.5 of chapter 2 of [7] and it is given by
Fig. 4. Timing diagram of the converter.
x(t") =7}jltJo +rJ$ i=1 i=1
n7 n7
~~i=1
J7J$] X(to) + E!).(e)
n7
n
nj
nj
j=l j=l
O.Je dc(2 j=l
(2)
Fig. 2. Switching diagram for multiple output converter.
The main switch Swm is closed at the beginning of each cycle, for a time DT. Note that D in this chapter refers to duty ratio of the main switch Swm . For a converter operating in steady state the voltagesecond product across the inductor, which is equal to net change in core flux over a cycle, must be zero. Similarly, net increment in capacitor charge must be zero over a cycle in steady state.
III.
SMALL SIGNAL MODEL
The timing diagram of the converter is drawn in Fig. 4 on the basis of the switching diagram given in Fig. 2. The switching instants and interval lengths are given along with the state matrices in these subintervals. The timing diagram of the converter is drawn in Fig. 4 on the basis of the switching diagram given in Fig. 2. The switching instants and interval
lengths are given along with the state matrices in these subintervals.
Let the state transition matrices in the intervals DT, dT and derT be (D1 ,D2 and (D3 respectively. Substituting these in
0DL
'I30
15I
Actual
7Model
0
a) 0
.........
(2), we get
x(t3) =J7[CD'(to)+
i=l
3
3
i=l
f i X(to)
i=l77
3
C)
j=l \, j=l
+ E n ~i ()j nO i ()j Vdc
3 ' 3j
3j
j=l
(3)
.: 1 00 0
UQ
n
a) 200
0
3
Time in
9
A. Linear Model of the Converter
Fig. 6.
converter.
Linear STM based prediction of perturbation of states of the
However, the prediction model has been tested at different operating point did not succeed as shown in Fig. 6. The The higher order terms of the expansion of the series has not converter is assumed to be in steady state at D=06 and d=0.1. been considered. Equation 4 is linear perturbation model of The main duty remains unchanged while load duty is changed the converter. It is a MISO (MultiInput Single Output) by 0.2. The state dynamics and prediction dynamics don't match at all. Thus linear prediction model is not sufficient to system. model the converter for all operating modes. x(t3 ) (D3(D2CDlx(to)
The expanded expression for the small signal perturbation model has been given in (4).
L(CD3A2D2ACD1
+ (C 3A2

((D3A(D2C1B
')2CD1

A3CD3CD2CDi)x(to)TS
A3D3CD2?1 )VdcTs

3B3VdCTs
CD3B3VdcIsj
1D (4)
j
)vdCT A3 CD3 CD2 C1)
The model developed is validated through extensive simulation study. The simulation results are given in Fig. 5 and
B. Bilinear Modeling and Controller Design The linear prediction model of the modified buckboost converter is not capable of predicting the perturbation in states for all possible modes. Hence a bilinear model of the converter has been developed in this section. The bilinear model has been derived from (3) by retaining product term of state and duty ratio along with the linear terms of the expansion. The model thus obtained is given in (5).
Fig.6. The converter in Fig. 5 is running at duty ratio of 5x(t3) 43 () 2 () I5X(to) main and load switches at 0.5 and 0.2 respectively. 0.2, which ) 2A1 1) I + [(3 2F)1)x(to)TS + is a considerably large perturbation, perturbs the main duty, E) L(1' 3 (1) 2 (1) I BI  A3 (1) 3 (1) 20 )Vd, Ts O 3 B Vd Ts while the load duty ratio remains constant. The prediction and D converter state trajectories overlap. 2D1  A3 D3cF2c1)x(to)Ts + + [( 3A2 E) E) A 2 (' 20  A 3 ( 3 (1 20 )Vd, Ts (1 3 B 3Vd, Ts 0)4 3 Linear STM Model + [(t) t) A1I ) I  A3 4)D3) D1)Tjs (to )D 80O
A3c)3F1)
3

(5)

3
2
2
+
[() 3 A2t' 2 (D I A3D3
D2(DS11)Tj(to)d
C. Model Verification
Time in
2000
C)
In order to verify the model, a number of simulations have been carried out. The simulation results are given in Figs. 7 to 8 and are summarized in Table 1. It can be seen that the predicted curve almost matches the simulated curve for fairly large perturbations. The failure case Fig. 8 has been reported to show that bilinear model too has a limitation.
D. Controller Design Based on Small Signal Model
0
0.006
Time in Sec
0.012
0.018
Fig. 5. Linear STM based prediction of perturbation of states of the converter.
Let the instant to be the reference instant k that coincides with the closing of the switch. The final switching instant t3 then be defined is the (k+1), where k =0,1,2 discrete time index. We can therefore express (4) in discrete
can as
...........
TABLE I SUMMARY OF BILINEAR PREDICTION RESULTS
The output equation thus becomes Yref (k) = [C O] Xe (k)
=
(12)
Steady state main duty
(Do )
0.6 0.2
Steady state load duty
(
(d
(do)
0.1 0.75
Model Prediction
CiXe (k)
Bilinear Prediction Model
(Figure)
Fig. 7
n
0 0.6
0.2
 0.65
0 150
0 CU
300
.....
..
Fig. 8
L g50( ) ... ~0.006
9n
C
0.012
0.018
Bilinear Corner Point Prediction Model
Actual ...Model Predictih 9o
() 500
cz
0
10
250
Hi3
/0.006
0.012 Time in Sec.
......
.:
0
c
c
* 0 10 0 * 0
U
n~
3 6
U(
0.65.
0.018
0
91
Fig. 8.
d
Bilinear prediction for
Do
=
0.2, do
=
0.75 and
D
=
0.6,
.
40X
U 80
Time in Sec.
Fig.7. Bilinear prediction for
x
Do
0.6,
do
=
0.1 and D= 0, d
0.2.
(k + 1) = F3(k) + Gd(k) (6) and the output equation can be expressed as (7) (7) y(k) = Cx(k) It is desired that the controller be able to track any step change in the reference voltage Yref Note that Yref is a change/desired perturbation in the output from the steady state value. For example, if the converter output is operating at 20V in steady state and we want an output of 30V, then the Yref will be OV. Similarly, if it is desired to have an output voltage of tOV, Yref will be OV. To facilitate the tracking function; we include a pseudointegrator action on the error function e(k) in the feedback loop. This is given by e(k) = y(k)  Yref (k) (8)
Based on this state space formulation of the converter, a controller can be designed by control techniques such as pole placement, LQR or LQG controller. In these methods, a control law will be derived in terms of the states of the converter. The control law in this case happens to be the expression of the duty ratio. This duty ratio can be computed from DSP based processors if the states are measured and fed as input to the DSP controller. The complexity of the controller therefore results in smart algorithm development on DSP processors.
V
z(k + 1) (I c)z(k) + e(k)
=
(9)
now
where E is a very small positive number. We extended state vector as
Xe(k)
define
an
(10)
Then combining (6) and (9) we get an extended state representation as
Xe,(k+ 1)
F
space
lOglXe(k)+KIU(k) + rYref (k)
Fe
Xe
(k) + Ge u (k) + Je Yref (k)
The model proposed for controller design is however based linear model of the converter. As discussed above that the linear model of the converter has a poor open loop prediction, i.e. the model is valid for small perturbation only. Therefore a nonlinear (bilinear) model based controller needs to be designed. The derivation of the control law may be mathematically complex in algebraic expression but can always be derived. The derived model however will become practically impossible or cost ineffective. Therefore a simple control law has been proposed in next section. The prime objective of a closed loop controller for a DCon
Fig. 9. Schematic diagram of hysteresis controller for two outputs modified BuckBoost converter.
DC converter is to reject input and load disturbances without losing stability. Improvements in response time, extension of zone of validation, etc. are some of other possible secondary objectives of closed loop controllers. But a better dynamic performance is essential for critical loads. Changing the duty ratio controls the output of a DCDC converter. Other methods are derived methods of duty ratio control to achieve a better control than direct control of duty. 0 2 1 nnr One such method is known as current programmed converter. a,) 1 yuu)Ur U,)~0 The current programmed closed loop control has been widely 0 )o studied in the literature. Inclusion of feedforward loop in nclosed loop controller has been suggested to improve dynamic 2 '~0 1 Time in ms response. It is possible to compensate the supply disturbance Fig. 10. Cold start behavior of the converter. in one cycle as reported in [8].
.10
TABLE II SIMULATION RESULTS OF THE CONVERTER
Test ConditionsConditions Test
Cold Start Behavior
~~~~~~~~~
Fg
Supply Disturbance
Load & supply Disturbance on Output 1 & 2 Load & supply Disturbance on Output 1 & 2
Behavlor~ Fig.10
AVdc AR,
2 AR2
3 
4
3
4
15
0

12 9 3.5 7
6
1
Result ~~~Shown in
cN
4
4
4,5
0
0
10
Fig. 11
3.5
4
4.5
10
10
10
Fig. 12
00
80
10
25
25
Fig. 13
3.5U 3.5
4
4.5 Time in ms
5
Fig. 1 1. Effect of supply disturbance, supply going up by 1 OV.
Although the theory of hysteresis control is well established, this is repeated here for sake of continuity. A variable(s) to be controlled is identified in a given circuit. The desired closed loop state trajectory is described for the variable. The feasibility study and stability requirements of the closed loop trajectory are made by suitable control theorems. This trajectory is now set as the reference value for the variable. We form a band called hysteresis band around this reference. The circuit is switched in such a manner that the actual state trajectory never goes out of this band. The average states of the converter therefore follow the set reference with high frequency component due to switching. This method of closed loop is called hysteresis control. The operation of the converter in closed loop control can be described as follows. The core mmf builds when the main switch of the converter is closed. The stored magnetic energy is then used for charging load circuit. If the core energy is more than the energy required for load circuit in a switching cycle, the excess energy is fed back to the input by energy recovery circuit. In case the load rejection takes place in the circuit, the amount of the excess energy goes up and thus the energy recovery interval is proportionately increased. However, if the energy demand of the load goes up, there is no
7R
0
to
73
0
68
Fig. 12. Effect of combined Load and supply disturbance both resistance decreased by 10 Q and supply dips by lOV.
3
4.
6
7.5
on
Output
1
& 2,
This will make the dynamic response slow. Had there been available when required by the load, the compensation could have been done instantaneously. Keeping this in view, the closed loop controller has been designed. The reference core energy is chosen to account for maximum loading condition. If the loading is less, the energy recovery is more and if the loading is at its peak, there is no energy
some excess energy
'I
Fav
N
0
7
T
v
(14)
4
4.
0
6
where T = tonM + tonl + ton2 is the cycle period if there is no energy recovery. Solving (13) and (14) we obtain (15).
Fav =( R1 )( Vdc V02 (15) In order to calculate the reference MMF for this experiment, we calculate the MMF from (15) and perform the simulation study starting with this value. The actual reference MMF is 5000 to 60% of the calculated average MMF as calculated from (15). The critical resistance for outputs can be calculated in the same line as done for the single output [6].
Fa
.70Q
"Id
(NIVO, I+1 Vol + Vol015
4
4.
683.
Time in
4
4.
Fig. 13. Effect of combined Load and supply disturbance on Output 1 & 2; both the Output resistances increased by 25 Q and supply rises by lOV.
recovery. The output voltage starts dropping for loads more
then the designed maximum load. This is also known as folding characteristics of the converter. The block diagram of the hysteresis controller for this converter is shown in Fig. 9. The performance of the closed lop controller has been tested by extensive simulation and experiments. The closed controller uses three feedback loops. The first feedback loop is for core mmf, second for output 1 and third for the output 2. The core mmf controller is given the top priority followed by controller for the output 1 and the output 2 is assigned last in the priority. The choice of the priority among the voltage loops is not strict and can be changed if required by the logic circuit. In Fig. 9, the voltage loop for output 1 is given higher priority compared to output 2. The switching ON of the load switch 1 is done when the switching state of the main switch is in OFF condition and similarly the switching ON of the load switch 2 is carried out when the main switch and load switch is simultaneously OFF. A. Analysis of Hysteresis Controlled Closed Loop System The reference voltages for different outputs are set equal to the desired outputs and the ripple requirements decide the hysteresis bandwidth. It is necessary to get a criterion to choose a reference value of core MMF for given outputs and possible variations. It is assumed here that the ripple content of the core MMF and output voltages are very small. Let the core mmf is operated with hysteresis band of A3 around an average core mmf of 3av and let the ON for a period of main switch, load switch 1 and load switch 2 be denoted by tonM, tonl and ton2 respectively. These intervals can be calculated from the averaging technique and are given by,
B. Simulation Results of TwoOutput Converter The summary of the simulation study for converter operation in Buck mode with possible disturbances is given in Table II The output voltages of the output 1 and output 2 are 12 V and 6 V respectively. The nominal load resistances are 25 Q and 15 Q for output 1 and output 2 respectively. Simulation study has been carried out for cold start behavior, load and source disturbances when acting alone and when they are acting together. The disturbance in supply or load (if any) has been marked by an arrow in the simulation results
presented below.
IV. EXPERIMENTAL VERIFICATION The parameters of the hardware components with their nominal loads are given in Appendix. The experiment has been carried out to verify the some of the simulation results. The scaling factors for voltages at output 1 and 2 are respectively 4.82 and 2.85 in the oscillograms i.e. waveforms of the variables shown on the oscilloscope. The core MMF has got a scaling factor of 150. The experiments are carried out at low frequency as the energy recovery transformer has got a considerable leakage inductance and hence coupling noise among the windings are high. The frequency of operation can be made high if a better energy recovery winding is used
AZ A3Z L & A3 A tn N1 LI t A2Vo2 LI (13) N1 Vdc N1 Vol MMF calculated over any subinterval in a The average core cycle must be equal to the average value over a cycle since the ripple in the MMF is small. Thus, tonM
Fig. 14. Experimental waveforms of Output voltage 1 and core MMF in steady state.
The experiments have been carried out for different condition to verify the simulation study for closed loop change
il 2 *O°Vf 2 2. OOV
&Q. o S
200tz=
+2 STOP
V. CONLUSION
u
i
t
~ ~
..
...
~
~
~
~
~
~
~
~
~
~
~
~
~ ~~~~...
A new topology for multiple output DCDC converter has been proposed which is capable of rejecting the disturbance if operated with hysteresis band closed loop controller in utmost one switching cycle.
VI. APPANDIX
Fi.1. Exeimna
waeom
of Oupt IA
hnla i eetdo
The parameters for simulation and experiments are given below.
L1
output 1. 1 2.OOV 2 2.OOV
=
3.5mH, C1 = C2
=
=
330pF, R1
=
R2
=
=
15Q, Vdc
=
20V,
a
3/2
Zav
,0.005
750AT, AS
=
O.1* av, AV0
0.05VO N1
150
200!:/
0 utpUt l 
It is to be noted that parameter 'a' is the turn ratio of the main winding to energy recovery winding. The value of the inductance of the energy recovery winding can be obtained
from turn ratio as L2 L1 a Please note that ESR of the capacitor and resistance of the inductance have been calculated indirectly from open loop experiment of the
converter.
Fi.1. Exeimna waeom of Oupt I l!l l l l increase'ld.
2 .hnlanotu I
 l!l p ' !
is
VII. ACKNOWLEDGMENT
The author gratefully acknowledges contributions of Arindham Ghosh and Avinash Joshi for the supervision of Ph. D. thesis of the author. This work has been carried out as Ph. D. work of the author.
[1] [2]
VIII. REFERENCES N. Mohan, T. M. Undelend, and W. P. Robbins: Power Electronics: Converters, Applications and Design, John Wiley & Sons, Singapore, 1989. Y. Chen, D. Y. Chen and Y. Wu, "Control Loop Modeling of Multiple Output Feedback of Forward Converter," IEEE Transactions on Power Electronics, Vol. 8, No. 3, pp. 320328, July 1993. J. sebastian and J. Uceda, "The Double Converter: A fully Regulated Two Output DcDC Converter," IEEE Transactions on Power Electronics, Vol. PE2, No. 3, pp. 239246, July 1987. F. Kurokawa and H. Matsuo, "A Multiple Output Hybrid Power Supply," IEEE Transactions on Power Electronics, Vol. 3, No. 4, pp. 239246, October 1988. T. Charanasomboon, M. J. Devaney and R. G. Hoft, " Single Switch Dual Output DCDC Converter Performance," IEEE Transactions on Power Electronics, Vol. 5, No. 2, pp. 241244, April 1990. R. K. Singh, A. Joshi, A. Ghosh, "A modified flyback DCDC converter," in Proc. 1998 IEEE Applied Power Electronics Conf, pp. 337343. R. K. Singh, "Modeling and Control of Conventional and Modified BuckBoost DCDC Converter," Ph.D. dissertation, Dept. Elec. Eng., I.I.T. Kanpur, India, 2001. K. M. Smedley and S. Cuk, "Onecycle control of switching converter," IEEE Trans. Power Electronics, Vol. 10, No. 6, pp. 625633, 1995.
[3]
[4] [5]
Fig. 17. Experimental waveforms of Outputs 1 & 2 when load is rejected on output 2.
1 2*00V
2 2.00OV
0.00S 200
fi STOP
[6]
[7]
[8]
~~ ~. ...
hysteresis control of converter. It can be seen from the above figures that the dynamics of the converter in closed loop converter has minor frequency deviation corresponding to supply is rejected in same cycle.
Fig. 18. Experimental waveforms of Outputs 1 & 2 when load on output 2 is increased.
Ravindra Kumar Singh was born on December 30, 1965 in Chapra, Bihar, India. He graduated from the Bhagalpur University, Bihar. He did his post graduation from IT, BHU and Ph. D. fro IIT Kanpur, India He is presently serving in M.N.N.I.T. Allahabad, India. He is also Fellow of Institution of Engineers
IX. BIOGRAPHIES
(India).