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SN74LVC1G08
SCES217Y – APRIL 1999 – REVISED APRIL 2014

SN74LVC1G08 Single 2-Input Positive-AND Gate
1 Features
1

3 Description
2

?

? ? ? ? ? ? ? ? ?

Available in the Ultra Small 0.64-mm Package (DPW) With 0.5-mm Pitch Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Provides Down Translation to VCC Max tpd of 3.6 ns at 3.3 V Low Power Consumption, 10-μA Max ICC ±24-mA Output Drive at 3.3 V Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)

This single 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G08 device performs the Boolean function or Y = A ? B or Y = A + B in positive logic. The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range. The SN74LVC1G08 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm. white space white space Device Information(1)
DEVICE NAME PACKAGE SOT-23 (5) SC70 (5) SN74LVC1G08 X2SON (4) SON (6) SON (6) BODY SIZE 2.9mm × 1.6mm 2.0mm × 1.25mm 0.8mm × 0.8mm 1.45mm × 1.0mm 1.0mm × 1.0mm

2 Applications
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ATCA Solutions Active Noise Cancellation (ANC) Barcode Scanner Blood Pressure Monitor CPAP Machine Cable Solutions DLP 3D Machine Vision, Hyperspectral Imaging, Optical Networking, and Spectroscopy E-Book Embedded PC Field Transmitter: Temperature or Pressure Sensor Fingerprint Biometrics HVAC: Heating, Ventilating, and Air Conditioning Network-Attached Storage (NAS) Server Motherboard and PSU Software Defined Radio (SDR) TV: High-Definition (HDTV), LCD, and Digital Video Communications System Wireless Data Access Card, Headset, Keyboard, Mouse, and LAN Card X-ray: Baggage Scanner, Medical, and Dental

(1) For all available packages, see the orderable addendum at the end of the datasheet.

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74LVC1G08
SCES217Y – APRIL 1999 – REVISED APRIL 2014 www.ti.com

Table of Contents
1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications.........................................................
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 Absolute Maximum Ratings ..................................... Handling Ratings....................................................... Recommended Operating Conditions ...................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics, CL = 15 pF ...................... Switching Characteristics, 1.8 V and 2.5 V .............. Switching Characteristics, 3.3 V and 5 V ................. Operating Characteristics.......................................... Typical Characteristics ............................................

1 1 1 2 3 4
4 4 5 5 6 6 6 7 7 7

8

Detailed Description ............................................ 10
8.1 8.2 8.3 8.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 10 10 10 10

9

Application and Implementation ........................ 11
9.1 Application Information............................................ 11 9.2 Typical Application ................................................. 11

10 Power Supply Recommendations ..................... 12 11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12 11.2 Layout Example .................................................... 12

12 Device and Documentation Support ................. 13
12.1 Trademarks ........................................................... 13 12.2 Electrostatic Discharge Caution ............................ 13 12.3 Glossary ................................................................ 13

7

Parameter Measurement Information .................. 8

13 Mechanical, Packaging, and Orderable Information ........................................................... 13

4 Revision History
Changes from Revision X (March 2014) to Revision Y ? ? ? ? ? ? ? Page

Updated Handling Ratings table. ........................................................................................................................................... 4 Added Thermal Information table. ......................................................................................................................................... 5 Added Typical Characteristics. .............................................................................................................................................. 7 Added Detailed Description section. .................................................................................................................................... 10 Added Application and Implementation section. ................................................................................................................. 11 Added Power Supply Recommendations section. .............................................................................................................. 12 Added Layout section. ......................................................................................................................................................... 12

Changes from Revision W (July 2013) to Revision X ? ? ?

Page

Added Applications. ................................................................................................................................................................ 1 Added Device Information table. ............................................................................................................................................ 1 Moved Tstg to Handling Ratings table. .................................................................................................................................... 4 Page

Changes from Revision V (November 2012) to Revision W ?

Added parameter values for –40 to 125°C temperature ratings............................................................................................. 6

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SN74LVC1G08
www.ti.com SCES217Y – APRIL 1999 – REVISED APRIL 2014

5 Pin Configuration and Functions
DBV PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) DRL PACKAGE (TOP VIEW) DSF PACKAGE (TOP VIEW)

A B

1

5

VCC

A B

1 2 3

5

VCC

A B GND

1 2 3

5

VCC Y

A
B GND

1 2 3

6

VCC NC Y

5 4

2

4

GND
3 4

4

Y

GND

Y

DPW PACKAGE (TOP VIEW)

YZP PACKAGE (BOTTOM VIEW)

DRY PACKAGE (TOP VIEW)

GND

B A

1 3 2

5 4

VCC Y

GND B A

3 4 2 1 5

Y VCC

A
B

1 2 3

6

VCC NC Y

5 4

GND

NC – No internal connection See mechanical drawings for dimensions.

Pin Functions
PIN NAME A B GND Y VCC NC DBV, DCK, DRL, YZP 1 2 3 4 5 DRY, DSF 1 2 3 4 6 5 DPW 2 1 3 4 5 DESCRIPTION Input Input Ground Output Power pin Not connected

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SN74LVC1G08
SCES217Y – APRIL 1999 – REVISED APRIL 2014 www.ti.com

6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN VCC VI VO VO IIK IOK IO Supply voltage range Input voltage range
(2)

MAX 6.5 6.5 6.5 VCC + 0.5 –50 –50 ±50 ±100

UNIT V V V V mA mA mA mA

–0.5 –0.5 –0.5 –0.5

Voltage range applied to any output in the high-impedance or power-off state (2) Voltage range applied to any output in the high or low state (2) (3) Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND VI < 0 VO < 0

(1) (2) (3)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the Recommended Operating Conditions table.

6.2 Handling Ratings
MIN Tstg Storage temperature range Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) –65 0 0 MAX 150 2000 V 1000 UNIT °C

V(ESD)

Electrostatic discharge

(1) (2)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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SN74LVC1G08
www.ti.com SCES217Y – APRIL 1999 – REVISED APRIL 2014

6.3 Recommended Operating Conditions (1)
MIN VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VI VO Input voltage Output voltage VCC = 1.65 V VCC = 2.3 V IOH High-level output current VCC = 3 V VCC = 4.5 V VCC = 1.65 V VCC = 2.3 V IOL Low-level output current VCC = 3 V VCC = 4.5 V VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V Δt/Δv TA (1) Input transition rise or fall rate Operating free-air temperature VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V –40 0 0 1.65 1.5 0.65 × VCC 1.7 2 0.7 × VCC 0.35 × VCC 0.7 0.8 0.3 × VCC 5.5 VCC –4 –8 –16 –24 –32 4 8 16 24 32 20 10 5 125 °C ns/V mA mA V V V V MAX 5.5 UNIT V

All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

6.4 Thermal Information
SN74LVC1G08 THERMAL METRIC (1) DBV 5 PINS RθJA RθJCtop RθJB ψJT ψJB RθJCbot Junction-to-ambient thermal resistance Junction-to-case (top) thermal resistance Junction-to-board thermal resistance Junction-to-top characterization parameter Junction-to-board characterization parameter Junction-to-case (bottom) thermal resistance 207.6 145.2 53.5 37.5 53.1 – DCK 5 PINS 283.1 92.3 60.9 1.7 60.1 – DRL 5 PINS 242.9 77.5 77.5 9.6 77.3 – DRY 6 PINS 438.8 276.8 271.7 83.8 271.4 – YZP 5 PINS 130 54 51 1 50 – DPW 4 PINS 340 215 294 41 294 250 °C/W UNIT

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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SN74LVC1G08
SCES217Y – APRIL 1999 – REVISED APRIL 2014 www.ti.com

6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = –100 μA IOH = –4 mA VOH IOH = –8 mA IOH = –16 mA IOH = –24 mA IOH = –32 mA IOL = 100 μA IOL = 4 mA VOL IOL = 8 mA IOL = 16 mA IOL = 24 mA IOL = 32 mA II Ioff ICC ΔICC Ci A or B inputs VI = 5.5 V or GND VI or VO = 5.5 V VI = 5.5 V or GND, IO = 0 One input at VCC – 0.6 V, Other inputs at VC C or GND VI = VCC or GND VCC 1.65 V to 5.5 V 1.65 V 2.3 V 3V 4.5 V 1.65 V to 5.5 V 1.65 V 2.3 V 3V 4.5 V 0 to 5.5 V 0 1.65 V to 5.5 V 3 V to 5.5 V 3.3 V 4 –40°C to 85°C MIN VCC – 0.1 1.2 1.9 2.4 2.3 3.8 0.1 0.45 0.3 0.4 0.55 0.55 ±5 ±10 10 500 4 TYP (1) MAX –40°C to 125°C RECOMMENDED MIN VCC – 0.15 1.2 1.9 2.4 2.3 3.8 0.1 0.45 0.3 0.4 0.55 0.55 ±5 ±10 10 500 μA μA μA μA pF V V TYP MAX UNIT

(1)

All typical values are at VCC = 3.3 V, TA = 25°C.

6.6 Switching Characteristics, CL = 15 pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
–40°C to 85°C PARAMETER FROM (INPUT) A or B TO (OUTPUT) Y VCC = 1.8 V ± 0.15 V MIN tpd 1.5 MAX 7.2 VCC = 2.5 V ± 0.2 V MIN 0.7 MAX 4.4 VCC = 3.3 V ± 0.3 V MIN 0.8 MAX 3.6 VCC = 5 V ± 0.5 V MIN 0.8 MAX 3.4 ns UNIT

6.7 Switching Characteristics, 1.8 V and 2.5 V (1)
over recommended operating free-air temperature range, (unless otherwise noted) (see Figure 4)
–40°C to 85°C PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V ± 0.15 V MIN tpd A or B Y 2.4 MAX 8 –40°C to 125°C RECOMMENDED VCC = 1.8 V ± 0.15 V MIN 2.4 MAX 10 –40°C to 85°C VCC = 2.5 V ± 0.2 V MIN 1.1 MAX 5.5 –40°C to 125°C RECOMMENDED VCC = 2.5 V ± 0.2 V MIN 1.1 MAX 7 ns UNIT

(1)

On products compliant to MIL-PRF-38535, this parameter is not production tested.

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SN74LVC1G08
www.ti.com SCES217Y – APRIL 1999 – REVISED APRIL 2014

6.8 Switching Characteristics, 3.3 V and 5 V (1)
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 4)
–40°C to 85°C PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN tpd A or B Y 1 MAX 4.5 –40°C to 125°C RECOMMENDED VCC = 3.3 V ± 0.3 V MIN 1 MAX 6 –40°C to 85°C VCC = 5 V ± 0.5 V MIN 1 MAX 4 –40°C to 125°C RECOMMENDED VCC = 5 V ± 0.5 V MIN 1 MAX 5 ns UNIT

(1)

On products compliant to MIL-PRF-38535, this parameter is not production tested.

6.9 Operating Characteristics
TA = 25°C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC = 1.8 V TYP 21 VCC = 2.5 V TYP 24 VCC = 3.3 V TYP 26 VCC = 5 V TYP 31 UNIT pF

6.10 Typical Characteristics
6 5 4

8 TPD 7 6

TPD - ns

TPD - ns
TPD

5 4 3 2

3 2 1 0 -100

1 0
-50 0 50 Temperature - ° C 100 150
D001

0

1

2

3 Vcc - V

4

5

6
D002

Figure 1. TPD Across Temperature at 3.3V Vcc

Figure 2. TPD Across Vcc at 25°C

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SN74LVC1G08
SCES217Y – APRIL 1999 – REVISED APRIL 2014 www.ti.com

7 Parameter Measurement Information
VLOAD From Output Under Test CL (see Note A) RL RL S1 Open GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open VLOAD GND

LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI VCC VCC 3V VCC tr/tf ?2 ns ?2 ns ?2.5 ns ?2.5 ns VM VCC/2 VCC/2 1.5 V VCC/2 VLOAD 2 × VCC 2 × VCC 6V 2 × VCC CL 15 pF 15 pF 15 pF 15 pF RL 1 MW 1 MW 1 MW 1 MW VD 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input tW VI Input VM VOLTAGE WAVEFORMS PULSE DURATION VI Input tPLH Output tPHL VM VM VM VM 0V tPHL VOH VM VOL tPLH VOH Output VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at VLOAD (see Note B) tPZH VM VM 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM tPZL VM VM 0V tPLZ VLOAD/2 VOL + VD tPHZ VOH – VD VOH ?0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING VOL Data Input tsu VM th VI VM 0V VM 0V

Output Control

NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ? 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices.

Figure 3. Load Circuit and Voltage Waveforms

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SN74LVC1G08
www.ti.com SCES217Y – APRIL 1999 – REVISED APRIL 2014

Parameter Measurement Information (continued)
VLOAD From Output Under Test CL (see Note A) RL RL S1 Open GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open VLOAD GND

LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI VCC VCC 3V VCC tr/tf ?2 ns ?2 ns ?2.5 ns ?2.5 ns VM VCC/2 VCC/2 1.5 V VCC/2 VLOAD 2 × VCC 2 × VCC 6V 2 × VCC CL 30 pF 30 pF 50 pF 50 pF RL 1 kW 500 W 500 W 500 W VD 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input tW VI Input VM VOLTAGE WAVEFORMS PULSE DURATION VI Input tPLH Output tPHL VM VM VM VM 0V tPHL VOH VM VOL tPLH VOH Output VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at VLOAD (see Note B) tPZH VM VM 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM tPZL VM VM 0V tPLZ VLOAD/2 VOL + VD tPHZ VOH – VD VOH ?0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING VOL Data Input tsu VM th VI VM 0V VM 0V

Output Control

NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ? 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices.

Figure 4. Load Circuit and Voltage Waveforms

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SN74LVC1G08
SCES217Y – APRIL 1999 – REVISED APRIL 2014 www.ti.com

8 Detailed Description
8.1 Overview
The SN74LVC1G08 device contains one 2-input positive AND gate device and performs the Boolean function Y = A ? B or Y = A + B . This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves significant board space over other package options while still retaining the traditional manufacturing friendly lead pitch of 0.5 mm.

8.2 Functional Block Diagram

8.3 Feature Description
? ? ? ? Wide operating voltage range. – Operates from 1.65 V to 5.5 V. Allows down voltage translation. Inputs and outputs accept voltages to 5.5 V. Ioff feature allows voltages on the inputs and outputs when VCC is 0 V.

8.4 Device Functional Modes
Function Table
INPUTS A H L X B H X L OUTPUT Y H L L

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SN74LVC1G08
www.ti.com SCES217Y – APRIL 1999 – REVISED APRIL 2014

9 Application and Implementation
9.1 Application Information
The SN74LVC1G08 is a high drive CMOS device that can be used for implementing AND logic with a high output drive, such as an LED application. It can produce 24 mA of drive current at 3.3 V making it Ideal for driving multiple outputs and good for high speed applications up to 100 MHz. The inputs are 5.5 V tolerant allowing it to translate down to VCC.

9.2 Typical Application
AND Logic Function VCC Basic LED Driver VCC

A- uC or Logic Y- uC or Logic B- uC or Logic LVC1G08

A- uC or Logic B- uC or Logic LVC1G08

9.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads so routing and load conditions should be considered to prevent ringing. 9.2.2 Detailed Design Procedure 1. Recommended Input Conditions – Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table. – Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table. – Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating Conditions table at any valid VCC. 2. Recommend Output Conditions – Load currents should not exceed (IO max) per output and should not exceed total current (continuous current through VCC or GND) for the part. These limits are located in the Absolute Maximum Ratings table. – Outputs should not be pulled above VCC.

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SN74LVC1G08
SCES217Y – APRIL 1999 – REVISED APRIL 2014 www.ti.com

Typical Application (continued)
9.2.3 Application Curves
10 8 6 Icc Icc Icc Icc 1.8V 2.5V 3.3V 5V

Icc - mA

4 2 0 -2 -20

0

20 40 Frequency - MHz

60

80
D003

Figure 5. Icc vs Frequency

10 Power Supply Recommendations
The power supply can be any voltage between the min and max supply voltage rating located in the Recommended Operating Conditions table. Each Vcc pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, a 0.1-μF capacitor is recommended and if there are multiple Vcc pins then 0.01-μF or 0.022-μF capacitor is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results.

11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to Gnd or Vcc whichever make more sense or is more convenient.

11.2 Layout Example
VCC Unused Input Input Output Input Unused Input Output

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SN74LVC1G08
www.ti.com SCES217Y – APRIL 1999 – REVISED APRIL 2014

12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.

12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.3 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms and definitions.

13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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SN74LVC1GXX and SN74AUP1GXX

PACKAGE OUTLINE
X2SON - 0.4 mm max height
SCALE 12.000

DPW0005A-C01

PLASTIC SMALL OUTLINE - NO LEAD

B

0.85 0.75

A

PIN 1 INDEX AREA

0.85 0.75

0.4 MAX

C SEATING PLANE NOTE 4

(0.1) THERMAL PAD 2 4 2X 0.48 1 0.27 0.17 (0.06) 3X 0.32 0.23 3 NOTE 4 0.25 0.1 0.05 0.00

5 4X 0.27 0.17 0.1 C A 0.05 C

B

4221849/A 12/2014

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 4. The size and shape of this feature may vary.

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SN74LVC1GXX and SN74AUP1GXX

EXAMPLE BOARD LAYOUT
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

DPW0005A-C01

(0.78) 4X (0.42) 1 4X (0.22) 5 SYMM ( 0.1) VIA 0.05 MIN ALL AROUND TYP

SYMM 3 2 (R0.05) TYP 4X (0.06) ( 0.25)

4X (0.26) (0.48)

4

SOLDER MASK OPENING, TYP METAL UNDER SOLDER MASK TYP

LAND PATTERN EXAMPLE
SOLDER MASK DEFINED SCALE:60X

4221849/A 12/2014

NOTES: (continued) 5. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271).

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SN74LVC1GXX and SN74AUP1GXX

EXAMPLE STENCIL DESIGN
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

DPW0005A-C01

4X (0.42)

4X (0.06)

4X (0.22)

1 ( 0.24) 4X (0.26)

5

SYMM SOLDER MASK EDGE 3

(0.21) TYP

(0.48)

2

4

(R0.05) TYP

SYMM (0.78)

BASED ON 0.1 mm THICK STENCIL EXPOSED PAD 92% PRINTED SOLDER COVERAGE BY AREA SCALE:100X

SOLDER PASTE EXAMPLE

4221849/A 12/2014

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

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PACKAGE OPTION ADDENDUM

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18-Sep-2015

PACKAGING INFORMATION
Orderable Device SN74LVC1G08DBVR Status
(1)

Package Type Package Pins Package Drawing Qty SOT-23 DBV 5 3000

Eco Plan
(2)

Lead/Ball Finish
(6)

MSL Peak Temp
(3)

Op Temp (°C) -40 to 125

Device Marking
(4/5)

Samples

ACTIVE

Green (RoHS & no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

(C085 ~ C08F ~ C08K ~ C08R ~ C08T) (C08P ~ C08S) (C085 ~ C08F ~ C08K ~ C08R ~ C08T) (C08P ~ C08S) (C085 ~ C08F ~ C08K ~ C08R ~ C08T) (C08P ~ C08S) (C085 ~ C08F ~ C08K ~ C08R) (C08H ~ C08P ~ C08S) (C085 ~ C08F ~ C08K ~ C08R) (C08H ~ C08P ~ C08S) (C085 ~ C08F ~ C08K ~ C08R) (C08H ~ C08P ~ C08S) (CE5 ~ CEF ~ CEK ~ CER ~ CET) (CEH ~ CEP ~ CES) (CE5 ~ CEF ~ CEK ~ CER ~ CET) (CEH ~ CEP ~ CES) (CE5 ~ CEF ~ CEK ~ CER ~ CET) (CEH ~ CEP ~ CES) (CE5 ~ CEF ~ CEK ~ CER ~ CET) (CEH ~ CEP ~ CES)

SN74LVC1G08DBVRE4

ACTIVE

SOT-23

DBV

5

3000

Green (RoHS & no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125

SN74LVC1G08DBVRG4

ACTIVE

SOT-23

DBV

5

3000

Green (RoHS & no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125

SN74LVC1G08DBVT

ACTIVE

SOT-23

DBV

5

250

Green (RoHS & no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125

SN74LVC1G08DBVTE4

ACTIVE

SOT-23

DBV

5

250

Green (RoHS & no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125

SN74LVC1G08DBVTG4

ACTIVE

SOT-23

DBV

5

250

Green (RoHS & no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125

SN74LVC1G08DCKR

ACTIVE

SC70

DCK

5

3000

Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125

SN74LVC1G08DCKRE4

ACTIVE

SC70

DCK

5

3000

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125

SN74LVC1G08DCKRG4

ACTIVE

SC70

DCK

5

3000

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125

SN74LVC1G08DCKT

ACTIVE

SC70

DCK

5

250

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

18-Sep-2015

Orderable Device SN74LVC1G08DCKTE4

Status
(1)

Package Type Package Pins Package Drawing Qty SC70 DCK 5 250

Eco Plan
(2)

Lead/Ball Finish
(6)

MSL Peak Temp
(3)

Op Temp (°C) -40 to 125

Device Marking
(4/5)

Samples

ACTIVE

Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

(CE5 ~ CEF ~ CEK ~ CER ~ CET) (CEH ~ CEP ~ CES) (CE5 ~ CEF ~ CEK ~ CER ~ CET) (CEH ~ CEP ~ CES) M4 (CE7 ~ CER) (CE7 ~ CER) CE CE CE CE (CE ~ CE2 ~ CE7)

SN74LVC1G08DCKTG4

ACTIVE

SC70

DCK

5

250

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125

SN74LVC1G08DPWR SN74LVC1G08DRLR SN74LVC1G08DRLRG4 SN74LVC1G08DRY2 SN74LVC1G08DRYR SN74LVC1G08DSF2 SN74LVC1G08DSFR SN74LVC1G08YZPR

ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE

X2SON SOT SOT SON SON SON SON DSBGA

DPW DRL DRL DRY DRY DSF DSF YZP

4 5 5 6 6 6 6 5

3000 4000 4000 5000 5000 5000 5000 3000

CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU | CU NIPDAUAG SNAGCU

Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM

-40 to 125 -40 to 125 -40 to 125 -40 to 125 -40 to 125 -40 to 125 -40 to 125 -40 to 85

(1)

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

18-Sep-2015

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(4)

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVC1G08 :

? Automotive: SN74LVC1G08-Q1 ? Enhanced Product: SN74LVC1G08-EP
NOTE: Qualified Version Definitions:

? Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects ? Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 3

PACKAGE MATERIALS INFORMATION
www.ti.com 3-Oct-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins Type Drawing SOT-23 SOT-23 SOT-23 SOT-23 SC70 SC70 SC70 SC70 SOT SON SON SON SON SON SON DSBGA DBV DBV DBV DBV DCK DCK DCK DCK DRL DRY DRY DRY DSF DSF DSF YZP 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 5

SPQ

Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 178.0 178.0 178.0 178.0 178.0 180.0 178.0 178.0 180.0 180.0 180.0 180.0 180.0 180.0 180.0 180.0 9.0 9.2 9.0 9.2 9.2 9.2 9.2 9.0 8.4 9.5 8.4 9.5 9.5 8.4 9.5 8.4 3.23 3.3 3.23 3.3 2.4 2.3 2.4 2.4 1.98 1.6 1.65 1.15 1.16 1.16 1.16 1.02

B0 (mm) 3.17 3.2 3.17 3.2 2.4 2.55 2.4 2.5 1.78 1.15 1.2 1.6 1.16 1.16 1.16 1.52

K0 (mm) 1.37 1.55 1.37 1.55 1.22 1.2 1.22 1.2 0.69 0.75 0.7 0.75 0.5 0.63 0.5 0.63

P1 (mm) 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0

W Pin1 (mm) Quadrant 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 Q3 Q3 Q3 Q3 Q3 Q3 Q3 Q3 Q3 Q3 Q3 Q1 Q3 Q3 Q2 Q1

SN74LVC1G08DBVR SN74LVC1G08DBVR SN74LVC1G08DBVT SN74LVC1G08DBVT SN74LVC1G08DCKR SN74LVC1G08DCKT SN74LVC1G08DCKT SN74LVC1G08DCKT SN74LVC1G08DRLR SN74LVC1G08DRY2 SN74LVC1G08DRY2 SN74LVC1G08DRYR SN74LVC1G08DSF2 SN74LVC1G08DSF2 SN74LVC1G08DSFR SN74LVC1G08YZPR

3000 3000 250 250 3000 250 250 250 4000 5000 5000 5000 5000 5000 5000 3000

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com 3-Oct-2015

*All dimensions are nominal

Device SN74LVC1G08DBVR SN74LVC1G08DBVR SN74LVC1G08DBVT SN74LVC1G08DBVT SN74LVC1G08DCKR SN74LVC1G08DCKT SN74LVC1G08DCKT SN74LVC1G08DCKT SN74LVC1G08DRLR SN74LVC1G08DRY2 SN74LVC1G08DRY2 SN74LVC1G08DRYR SN74LVC1G08DSF2 SN74LVC1G08DSF2 SN74LVC1G08DSFR SN74LVC1G08YZPR

Package Type SOT-23 SOT-23 SOT-23 SOT-23 SC70 SC70 SC70 SC70 SOT SON SON SON SON SON SON DSBGA

Package Drawing DBV DBV DBV DBV DCK DCK DCK DCK DRL DRY DRY DRY DSF DSF DSF YZP

Pins 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 5

SPQ 3000 3000 250 250 3000 250 250 250 4000 5000 5000 5000 5000 5000 5000 3000

Length (mm) 180.0 180.0 180.0 180.0 180.0 205.0 180.0 180.0 202.0 184.0 202.0 184.0 184.0 202.0 184.0 182.0

Width (mm) 180.0 180.0 180.0 180.0 180.0 200.0 180.0 180.0 201.0 184.0 201.0 184.0 184.0 201.0 184.0 182.0

Height (mm) 18.0 18.0 18.0 18.0 18.0 33.0 18.0 18.0 28.0 19.0 28.0 19.0 19.0 28.0 19.0 20.0

Pack Materials-Page 2

MECHANICAL DATA
DSF (S-PX2SON-N6) PLASTIC SMALL OUTLINE NO-LEAD

A

1.05 0.95

B

PIN 1 INDEX AREA

1.05 0.95

0.4 MAX

C SEATING PLANE 0.05 C (0.11) TYP SYMM 3 0.05 0.00 4 SYMM

2X 0.7

4X 0.35 1 (0.1) PIN 1 ID 6 6X 6X 0.45 0.35 0.22 0.12 0.07 0.05

C A C

B

4208186/F 10/2014

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MO-287, variation X2AAF.

www.ti.com

D: Max = 1.418 mm, Min =1.358 mm E: Max = 0.918 mm, Min =0.858 mm

IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. 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