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High Breakdown Voltage AlGaN–GaN Power-HEMT Design and High Current Density Switching Behavior


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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 12, DECEMBER 2003

High Breakdown Voltage AlGaN–GaN Power-HEMT Design and High Current Density Switching Behavior
Wataru Saito, Associate Member, IEEE, Yoshiharu Takada, Masahiko Kuraguchi, Kunio Tsuda, Ichiro Omura, Member, IEEE, Tsuneo Ogura, Member, IEEE, and Hiromichi Ohashi, Member, IEEE

Abstract—AlGaN–GaN power high-electron mobility transistors (HEMTs) with 600-V breakdown voltage are fabricated and demonstrated as switching power devices for motor drive and power supply applications. The fabricated power HEMT realized the high breakdown voltage by optimized field plate technique and the low on-state resistance of 3.3 m cm2 , which is 20 times lower than that of silicon MOSFETs, thanks to the high critical field of GaN material and the high mobility in 2DEG channel. The fabricated devices also demonstrated the high current cm2 turn-off. These results show density switching of 850 that AlGaN–GaN power-HEMTs are one of the most promising candidates for future switching power device for power electronics applications.




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Index Terms—GaN, high voltage device, power semiconductor device.

I. INTRODUCTION OWER SEMICONDUCTOR switching devices with breakdown voltages of several hundred volts have been studied with a view to reducing the power loss for switching mode power supplies and inverter systems [1]. In the Si power MOSFET, which is the most popular power-switching device, the on-resistance of 110% of the Si-limit has been realized [2]. In addition, superjunction MOSFETs have broken through the Si-limit and achieved the on-resistance of 35 m cm for 600-V class devices [3]. For more dramatic reduction of the on-resistance, AlGaN–GaN heterostructure devices are attractive, due to high carrier mobility in two-dimensional electron gas (2DEG) channel and large critical electric field [4]–[6]. Recently, high breakdown voltage AlGaN–GaN devices have been demonstrated and showed the ultralow on-resistance below the Si-limit [7]–[10]. In the previous work, high voltage GaN devices are designed with only a minor change of radio frequency high-electron mobility transistors (RF-HEMTs) and thus they have not been optimized as high-voltage switching devices [7], [10]. In addition, power devices are required to have turnoff switching capability even under high current condition at a high dc-link voltage such as 300 V, which is typical voltage for power supply system and motor drive applications.
Manuscript received April 28, 2003; revised August 22, 2003. This review of this paper was arranged by Editor M. Ayman Shibib. W. Saito, I. Omura and T. Ogura are with Toshiba Corporation, Semiconductor Company, Kawasaki, Japan (e-mail: wataru3.saito@ toshiba.co.jp). Y. Takada, M. Kuraguchi, K. Tsuda and H. Ohashi are with Toshiba Research and Development Center, Kawasaki 212-8583, Japan. Digital Object Identifier 10.1109/TED.2003.819248

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Fig. 1.Cross-sectional structures of fabricated AlGaN–GaN HEMT with FP-HEMT and electric field distribution along the interface of AlGaN Layer with field plate (solid line) and without field plate (broken line).

In this paper, AlGaN–GaN HEMTs are optimized for a 600-V class switching power device and experimentally demonstrated sufficient breakdown voltage and the ultralow on-state resistance. The device also shows the high current density switching capability under 300 V dc-link voltage showing the potential of AlGaN–GaN HEMT for power electronics applications. II. DEVICE STRUCTURE AND EXPERIMENTAL RESULTS The field plate structure shown in Fig. 1 is employed for high breakdown voltage design for AlGaN–GaN HEMTs. The field plate structure is chosen because of the following. 1) No additional doping is required. 2) Fabrication process is compatible to conventional HEMT process. 3) The effect has been proved by silicon device. The field plate is placed over the gate electrode and the edge of the field plate must be closer to the drain than the gate electrode edge so that the electric field concentration near the gate edge is efficiently eased and the electric field rather uniformly distributes between gate and drain electrodes [8]. The same figure compares the electric field in the interface of AlGaN layer and

0018-9383/03$17.00 ? 2003 IEEE

SAITO et al.: HIGH BREAKDOWN VOLTAGE AlGaN–GaN POWER-HEMT DESIGN

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Fig. 2. Off-state I –V

characteristics of AlGaN–GaN HEMT withFP-HEMT.

insulation layer. The electric field with the field plate is distributed between drain and gate while the electric field without field plate concentrates near the gate electrode edge. The AlGaN–GaN heterostructure was grown on highly resistive n-type (0001) 4H-SiC substrate by metal-organic chremical vapor deposition (MOCVD). The material growth began with a 100-nm-thick AlN buffer layer, followed by 3-mm-thick undoped GaN layer as a channel layer. Finally, spacer, a 10-nm-thick a 3-nm-thick undoped cm ) carrier supply and a Si doped (5 barrier layer were grown. 5-nm-thick undoped The device processing consisted of conventional HEMT fabrication steps. After mesa etching by ECR-RIBE, a Ti/Al layered metallization was evaporated and lifted off for source and drain ohmic contact. The gate electrode was formed with Ni/Au. As passivation films, 360-nm-thick SiN and were deposited by CVD. The field plate 600-nm-thick electrode connecting to the source electrode was formed on passivation layer. The gate length and width the were 1.5 m and 200 m, respectively. The gate-source length was 5 or 10 m. was 1.5 m. The gate-drain offset length and 10 m devices were The active device areas for and 8.27 cm , respectively. 6.93 The breakdown voltage was drastically improved using the field plate structure. Field plate structures (FP-HEMTs) with m and m showed the breakdown voltage of 350 V, which is three times larger than that of the HEMT without the field plate, as shown in Fig. 2. The breakand increased down voltage was improved to 600-V, as to 10 m and 5 m, respectively. The threshold gate voltage . The breakdown voltage and the on-resistance were was and 0 V, respectively. The substrate was measured at connected to the source during the measurements. The specific of fabricated devices with the breakdown on-resistances voltage of 350 V and 600-V were 1.9 and 3.3 m cm (5.5 and 8.0 mm), respectively. III. OPTIMIZATION OF TRADEOFF CHARACTERISTICS

Fig. 3. Breakdown voltage as a function of (a) field plate length L GaN layer thickness d .

and (b)

The on-resistance and the breakdown voltage ( - ) tradeoff characteristics can be improved by design optimization. The device characteristics were calculated using twodimensional device simulator ISE-Dessis [11]. Simulation was performed under ideal condition. Detail simulation condition is

as follows. The GaN layer doping concentration was assumed cm , and the surface state at the interface to be 1 between the passivation film and the semiconductor was neglected. The avalanche breakdown parameter from [12] was used in the simulation, and the Schottky barrier tunneling was considered for the gate leakage current calculation. The breakdown voltage design is discussed as follows. The and the undoped GaN layer thickness field plate length were chosen as the simulation parameter as shown in Fig. 3, because the breakdown voltage can be increased by relaxation of the gate and drain electric field peaks. Fig. 3(a) shows the relation between the breakdown voltage . Although the crystal quality and the field plate length and surface state were not especially improved in the fabricated device, the simulation results show good agreement with the experimental results, and the relation between the breakdown shows same tendency with the previous expervoltage and imental results [13]. From these results, the simulation tool is useful to high voltage device design. up to 3 m due to The breakdown voltage increases with reduction of electric field at the edge of the gate electrode. The of over 3 m breakdown voltage slightly decreases with due to increase of the drain side electric field by decreasing of the space between the field plate edge and the drain electrode. is also very important paThe GaN layer thickness rameter for the breakdown voltage as shown in Fig. 3(b). Up . This is to 6 m, the breakdown voltage increases with simply because the SiC substrate is electrically grounded and thus the applied voltage is vertically sustained across the undoped GaN layer between the drain electrode and the SiC subrelaxes the vertical elecstrate. Therefore the increase of

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 12, DECEMBER 2003

Fig. 5. Turn-off waveform of 600-V FP-HEMT with dc-link voltage of 300 V. Fig. 4. Tradeoff characterisitics between specific on-resistance and breakdown voltage of AlGaN–GaN devices and theoretical GaN-limit.

tric field beneath the drain electrode. In the case of undoped GaN layer thickness of over 6 m, however, the breakdown voltage decreases. It is because the SiC substrate has the same voltage as the source electrode and thus works as a backside field plate. Therefore increase of the undoped GaN layer thickness decreases the shielding effect of the backside field plate and thus the breakdown occurs at the gate edge. In this case, the optimized undoped GaN layer thickness is almost same as the field plate length. tradeoff Another important point to improve the of the device is excess area management. The specific on-resistance can be reduced by the shrinking of excess area such as contact, gate-source offset and channel regions, because cell number in a unit area can be increased. Since the source/drain contact area dominates the fabricated device area, the on-resistance was larger than the previous reported data [7], [8]. The tradeoff characteristics can be improved by optimized design as shown in Fig. 4. In the calculation, both the gate and the gate-source offset lengths were 0.5 m. At the fabriwas 50 cm . The cated device, the contact resistivity on-resistance can be 0.92 m cm with breakdown voltage of 600-V by only shrinking of the excess area. In addition, the lower source/drain contact resistivity can be further reduced the cm , the on-resistance can be on-resistance. At 0.51 m cm with breakdown voltage of 600-V. IV. SWITCHING CHARACTERISTICS Maximum switching current density of the switching power device is an important parameter for the device design, such as the chip shrink and the switching speed. The fabricated FP-HEMTs achieved high current density switching under high supplied voltage condition. The switching current density was (350 mA/mm) at for 600-V devices. 850 Fig. 5 shows the turnoff waveform for 600-V-FP-HEMT at the resistive load. The pulse-wise gate-source voltage swinging from 0 to 8 V is supplied using a pulse generator through an external gate resistor of 50 . This switching current density is ten times larger than that of 600-V class conventional Si MOSFETs. The switching speed is discussed as follows. The switching time depended on the charge and discharge of the drain-source

capacitance, because both the current rise and fall times were and the fall time was inversely proportional proportional to 300 V and cm (drain current to . At ), the current rise time and the current fall time were 126 and 274 ns, respectively. From the turnoff waveform of the drain current, the drain-source charge at the turn-off is estimated to be about 9.5 nC. This charge comes from parasitic capacitance between the drain electrode pad and SiC substrate. While the intrinsic drain-source charge is estimated to be about 0.11 nC. Since the difference of the switching speed between experimental and simulation results must be equivalent to the difference between the electrode pad capacitance and the active device capacitance, the intrinsic rise and fall times are estimated to be 1.5 and 3.2 ns. The ultrahigh-speed switching with high current density can be expected by reduction of parasitic capacitance. The fabricated GaN-HEMT demonstrated high current density switching, which was ten times higher than that of Si powerMOSFETs. However the power density of the device increases with the current density, and heat dissipation from the chip becomes difficult. Although the GaN-HEMT realizes dramatic reduction of both the chip area and the power loss due to low on-resistance and high current density switching, the heat dissipation technique is important to bring out the potential of the GaN-HEMT. In the power electronics application device, the heat spreading technique such as using SiC substrate or diamond heat spreader is also important developing point. V. CONCLUSION The high breakdown voltage AlGaN–GaN HEMT with the field plate structure (FP-HEMT) was fabricated. The breakdown voltage of 600-V is obtained by optimizing the field plate length and gate-drain offset . The specific on-resistance was 3.3 m cm for the 600-V breakdown voltage FP-HEMT with m and m. It is also found by 2-D device simulation that the tradeoff characteristics between the breakdown voltage and the on-resistance can be further improved by , the undoped GaN layer thickness the optimized design of and the electrode contact length and the electrode contact resistivity reduction. The fabricated FP-HEMT achieved high current density switching under high dc-link voltage of 300 V. The achieved switching current density was ten times larger than that of 600-V class conventional Si MOSFETs.

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REFERENCES
[1] B. J. Baliga, “Trends in power semiconductor devices,” IEEE Trans. Electron Devices, vol. 43, pp. 1717–1731, Nov., 1996. [2] T. Kobayashi, H. Abe, Y. Niimura, T. Yamada, A. Kurosaki, T. Hosen, and T. Fujihira, “High voltage power MOSFETs reached almost to the silicon limit,” in Proc. ISPSD, 2001, pp. 435–438. [3] G. Deboy, M. M?rz, J. -P. Stengl, H. Strack, J. Tihanyi, and H. Weber, “A new generation of high voltage MOSFETs breaks the limit line of silicon,” in IEDM Tech. Dig., 1998, pp. 683–685. [4] T. P. Chow and R. Tyagi, “Wide bandgap compound semiconductors for superior high-voltage unipolar power devices,” IEEE Trans. Electron Devices, vol. 41, pp. 1481–1483, Aug., 1994. [5] M. Trivedi and K. Shenai, “Performance evaluation of high-power wide band-gap semiconductor rectifiers,” J. Appl. Phys., vol. 85, pp. 6889–6897, 1999. , “Practical limit of high-voltage thyristors on wide band-gap ma[6] terials,” J. Appl. Phys., vol. 88, pp. 7313–7320, 2000. [7] G. Shimin, X. Hu, N. Ilinskaya, A. Kumar, A. Koudymov, J. Zhang, = current M. A. Khan, R. Gaska, and M. S. Shur, “7.5 switch using AlGaN–GaN metal-oxide-semiconductor heterostructure field effect transistors on SiC substrates,” Electron Lett., vol. 36, pp. 2043–2044, 2000. [8] N. -Q. Zhang, S. Keller, G. Parish, S. Heilman, S. P. DenBaars, and U. K. Mishra, “High breakdown GaN HEMT with overlapping gate structure,” IEEE Electron Device Lett., vol. 21, pp. 421–423, Sept. 2000. [9] N. -Q. Zhang, B. Moran, S. P. DenBaars, U. K. Mishra, X. W. Wang, and T. P. Ma, “Effects of surface traps on breakdown voltage and switching speed of GaN power switching HEMTs,” in IEDM Tech. Dig., 2001, pp. 589–592. [10] S. Yoshida, H. Ishii, J. Li, D. Wang, and M. Ichikawa, “A high-power AlGaN–GaN heterojunction field-effect transistor,” Solid State Electron., vol. 47, pp. 589–592, 2003. [11] ISE TCAD Manuals, release 8 ed., pt. 11, ISE Integrated Systems Engineering AG, Zurich, Switzerland, 2002. [12] K. Kunihiro, K. Kasahara, Y. Takahashi, and Y. Ohno, “Experimental evaluation of impact ionization coefficients in GaN,” IEEE Electron Device Lett., vol. 20, pp. 608–610, Dec., 1999. [13] Y. Ando, Y. Okamoto, H. Miyamoto, T. Nakayama, T. Inoue, and M. Kuzuhara, “10-W/mm AlGaN–GaN HFET with a field modulating plate,” IEEE Electron Device Lett., vol. 24, pp. 289–291, May, 2003.

Kunio Tsuda received the B.E. degree in electrical engineering in 1983 from Tohoku University, Sendai, Japan. In 1983, he joined the Toshiba Research and Development Center, Kawasaki, Japan, where he has been engaged in the research and development of compound semiconductor devices. Mr. Tsuda is a member of the Japan Society of Applied Physics and the Institute of Electronics, Information and Communication Engineers.

kW mm

Ichiro Omura (M’93) received the M.S. degree in mathematics from Osaka University, Osaka, Japan, in 1987 and the Ph.D. degree in electrical engineering from the Swiss Federal Institute of Technology (ETH), Zürich, Switzerland, in 2001. From 1987 to 1999, he was with Research and Development Center, Toshiba Corporation, Kawasaki, Japan. From 1996 to 1997, he was a Visiting Researcher at ETH. Since 1999, he has been with the Microelectronics Center, Semiconductor Company, Toshiba Corporation. He has been engaged in the research and development of high power semiconductor devices Dr. Omura is a member of the Japan Society of Applied Physics.

Wataru Saito (A’99) received the B.S., M.S., and Ph.D. degrees in electrical and electronics engineering from Tokyo Institute of Technology, Tokyo, Japan, in 1994, 1996, and 1999, simultaneously. He joined Discrete Semiconductor Division, Toshiba Corporation Semiconductor Company, Kawasaki, Japan, in 1999, where he has been engaged in the development of power semiconductor devices. Dr. Saito is a member of the Japan Society of Applied Physics. Yoshiharu Takada received the B.S. degree in physics from Tokyo University of Science, Tokyo, Japan, in 1993 and the M.S. degree in imaging science and engineering from Tokyo Institute of Technology in 1995. He joined Toshiba Research and Development Center, Kawasaki, Japan, in 1995, where he has been engaged in the development of compound semiconductor devices. His current interest is basic researches on GaN power device. Mr. Takda is a member of the Japan Society of Applied Physics. Masahiko Kuraguchi received the B.S., M.S., and Ph.D. degrees in physics from the University of Tokyo, Tokyo, Japan in 1997, 1999 and 2002, respectively. He joined Toshiba Research and Development Center, Kawasaki, Japan, in 2002, where he has been engaged in the research of III-V compound semiconductor devices. Dr. Kuraguchi is a member of the Japan Society of Applied Physics.

Tsuneo Ogura (M’89) received the B.E. and M.E. degrees in electronics engineering from Keio University, Japan, in 1975 and 1977, respectively. In 1977, he joined the Research and Development Center, Toshiba Corporation, Kawasaki, Japan. Since 1999, he has been with the Microelectronics Center, Semiconductor Company, Toshiba Corporation, Kawasaki, Japan. He has been engaged in the research and development of high-power semiconductor devices, such as LTTs, GTOs, and IEGTs. Mr. Ogura is a member of the Institute of Electrical Engineers of Japan.

Hiromichi Ohashi (M’81) received the B.S and M.S degrees in electrical engineering from Hosei University, and Sophia University, Tokyo, Japan, in 1965 and 1969, respectively, and the Ph.D. degree in electrical engineering from Tohoku University, Sendai, Japan, in 1989. In 1969, he joined Toshiba Research and Development Center, Kawasaki, Japan. Since 1972, he has been engaged in research and development of power semiconductor devices such as GTOs, LTTs, IGBTs, and applications of silicon-wafer direct bonding technology for power ICs. From 1994 to 2002, as a Senior Fellow, he was responsible in Toshiba, for research planning and developments of next-generation power devices and related application technologies. He retired from Toshiba cooperation in 2003. He is now a Professor owith the Tokyo Institute of Technology and the Deputy Director of Power Electronics Research Center of National Institute of Advanced Industrial and Science Technology. His current interest is basic researches on the power electronics system integration as well as next generation power semiconductor devices including wide band-gap semiconductor materials applications. He holds 86 patents and has published over 63 papers in technical journals and refereed conferences. Dr. Ohashi was the General Chairman of ISPSD’95. In 1999, he was awarded the Purple Ribbon Medal by the Government of Japan for his contributions to power devices researches and its applications. He is a member of the Institute of Electrical Engineers of Japan.


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