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苹果MACBOOK+A1278+mcp79


8

7

6

5

4

3
REV

2
ZONE ECN DESCRIPTION OF CHANGE

1
CK APPD ENG APPD DATE DATE

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

M97A MLB SCHEMATIC
REFERENCED FROM T18 03/11/2009
Date (.csa) Date (.csa)

C

681298

PRODUCTION RELEASED

03/11/09 ?

D
(.csa)

D
Date

Page
TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

Contents
1

Sync
08/22/2007 T17_MLB 12/12/2007 T18_MLB 03/13/2008 DRAGON

Page
TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

Contents
45

Sync
04/14/2008 CHANGZHANG 01/18/2008 YUAN.MA 05/28/2008 YUAN.MA 06/26/2008

Page
TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

Contents
100

Sync
01/04/2008 T18_MLB 01/04/2008 T18_MLB 01/04/2008 T18_MLB 12/14/2007 T18_MLB 03/19/2008 T18_MLB 01/04/2008 T18_MLB M97_MLB M97_MLB

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C

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B

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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Table of Contents
2

System Block Diagram
3

Power Block Diagram
4

TABLE_TABLEOFCONTENTS_ITEM

BOM Configuration
5

M97_MLB
TABLE_TABLEOFCONTENTS_ITEM

Revision History
6

M97_MLB 04/04/2008
TABLE_TABLEOFCONTENTS_ITEM

JTAG Scan Chain
7

BEN
TABLE_TABLEOFCONTENTS_ITEM

FUNC TEST
8

M97_MLB 04/21/2008
TABLE_TABLEOFCONTENTS_ITEM

Power Aliases
9

BEN
TABLE_TABLEOFCONTENTS_ITEM

SIGNAL ALIAS
10

M97_MLB 12/12/2007
TABLE_TABLEOFCONTENTS_ITEM

CPU FSB
11

T18_MLB 12/12/2007
TABLE_TABLEOFCONTENTS_ITEM

CPU Power & Ground
12

T18_MLB 03/31/2008
TABLE_TABLEOFCONTENTS_ITEM

CPU Decoupling
13

RAYMOND 12/12/2007
TABLE_TABLEOFCONTENTS_ITEM

eXtended Debug Port (XDP)
14

T18_MLB 04/04/2008
TABLE_TABLEOFCONTENTS_ITEM

MCP CPU Interface
15

T18_MLB 04/04/2008
TABLE_TABLEOFCONTENTS_ITEM

MCP Memory Interface
16

T18_MLB 04/04/2008
TABLE_TABLEOFCONTENTS_ITEM

MCP Memory Misc
17

T18_MLB 04/04/2008
TABLE_TABLEOFCONTENTS_ITEM

MCP PCIe Interfaces
18

T18_MLB 04/04/2008
TABLE_TABLEOFCONTENTS_ITEM

MCP Ethernet & Graphics
19

T18_MLB 04/04/2008
TABLE_TABLEOFCONTENTS_ITEM

MCP PCI & LPC
20

T18_MLB 04/04/2008
TABLE_TABLEOFCONTENTS_ITEM

MCP SATA & USB
21

T18_MLB 06/26/2008
TABLE_TABLEOFCONTENTS_ITEM

MCP HDA & MISC
22

T18_MLB 04/04/2008
TABLE_TABLEOFCONTENTS_ITEM

MCP Power & Ground
24

T18_MLB 03/08/2008
TABLE_TABLEOFCONTENTS_ITEM

MCP79 A01 Silicon Support
25

T18_MLB 04/04/2008
TABLE_TABLEOFCONTENTS_ITEM

MCP Standard Decoupling
26

T18_MLB 12/12/2007
TABLE_TABLEOFCONTENTS_ITEM

MCP Graphics Support
28

T18_MLB 04/05/2008
TABLE_TABLEOFCONTENTS_ITEM

SB Misc
29

RAYMOND 03/31/2008
TABLE_TABLEOFCONTENTS_ITEM

FSB/DDR3 Vref Margining
31

BEN 06/30/2008
TABLE_TABLEOFCONTENTS_ITEM

DDR3 SO-DIMM Connector A
32

BEN 05/09/2008
TABLE_TABLEOFCONTENTS_ITEM

DDR3 SO-DIMM Connector B
33

BEN 04/04/2008
TABLE_TABLEOFCONTENTS_ITEM

DDR3 Support
34

T18_MLB 04/22/2008
TABLE_TABLEOFCONTENTS_ITEM

Right Clutch Connector
35

YITE 03/13/2008
TABLE_TABLEOFCONTENTS_ITEM

VENICE CONNECTOR
37

YITE 05/23/2008
TABLE_TABLEOFCONTENTS_ITEM

Ethernet PHY (RTL8211CL)
38

SUMA 07/01/2008
TABLE_TABLEOFCONTENTS_ITEM

Ethernet & AirPort Support
39

SUMA 04/04/2008
TABLE_TABLEOFCONTENTS_ITEM

ETHERNET CONNECTOR

SUMA
TABLE_TABLEOFCONTENTS_ITEM

36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

SATA Connectors
46

External USB Connectors
48

Front Flex Support
49

TABLE_TABLEOFCONTENTS_ITEM

SMC
50

T18_MLB 05/28/2008
TABLE_TABLEOFCONTENTS_ITEM

SMC Support
51

YUAN.MA 05/09/2008
TABLE_TABLEOFCONTENTS_ITEM

LPC+SPI Debug Connector
52

CHANGZHANG 04/21/2008
TABLE_TABLEOFCONTENTS_ITEM

M97 SMBUS CONNECTIONS
53

BEN 02/04/2008
TABLE_TABLEOFCONTENTS_ITEM

VOLTAGE SENSING
54

YUNWU 04/07/2008
TABLE_TABLEOFCONTENTS_ITEM

71 72 73 74 75 76 77 78

CPU/FSB Constraints
101

Memory Constraints
102

MCP Constraints 1
103

MCP Constraints 2
104

Ethernet Constraints
106

SMC Constraints
107

M97 SPECIAL CONSTRAINTS
109

M97 RULE DEFINITIONS

Current Sensing
55

YUNWU 03/20/2008 YUNWU 01/18/2008 CHANGZHANG 04/22/2008 YUAN.MA 05/09/2008 YUAN.MA 06/26/2008 YUNWU 05/02/2008 CHANGZHANG 07/01/2008 AUDIO 07/03/2008 AUDIO 07/01/2008 AUDIO 07/01/2008 AUDIO 07/01/2008 AUDIO 03/13/2008 JACK 01/31/2008 RAYMOND 02/08/2008 RAYMOND 01/31/2008 RAYMOND 01/31/2008 RAYMOND 01/31/2008 RAYMOND 02/08/2008 RAYMOND 01/23/2008 RAYMOND 04/22/2008 YUAN.MA 04/04/2008 YUAN.MA 04/04/2008 NMARTIN 04/18/2008 AMASON 06/30/2008 AMASON 08/12/2008 YITE 06/30/2008 YITE

Thermal Sensors
56

Fan
57

WELLSPRING 1
58

WELLSPRING 2
59

SMS
61

SPI ROM
62

C

AUDIO: CODEC
63

AUDI0: MIKEY
66

AUDI0: SPEAKER AMP
67

AUDIO: JACK
68

AUDIO: JACK TRANSLATORS
69

DC-In & Battery Connectors
70

PBUS Supply/Battery Charger
72

5V/3.3V SUPPLY
73

1.5V/0.75V DDR3 SUPPLY
74

IMVP6 CPU VCore Regulator
75

MCP VCORE REGULATOR
76

CPU VTT(1.05V) SUPPLY
77

MISC POWER SUPPLIES
78

POWER SEQUENCING
79

POWER FETS
90

LVDS CONNECTOR
93

DISPLAYPORT SUPPORT
94

B

DisplayPort Connector
97

LCD BACKLIGHT DRIVER
98

LCD Backlight Support

TABLE_TABLEOFCONTENTS_ITEM

POST-RAMP
DIMENSIONS ARE IN MILLIMETERS XX

METRIC
DRAFTER DESIGN CK

APPLE INC.
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

A
Schematic / PCB #’s
PART NUMBER
051-7918 820-2327

X.XX

A

X.XXX ENG APPD ANGLES QA APPD DESIGNER MFG APPD

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART TITLE

QTY
1 1

DESCRIPTION
SCHEM,MLB,M97A PCBF,MLB,M97

REFERENCE DES
SCH PCB

CRITICAL
CRITICAL CRITICAL

BOM OPTION

DO NOT SCALE DRAWING RELEASE SCALE NONE SIZE MATERIAL/FINISH NOTED AS APPLICABLE DRAWING NUMBER REV.

SCHEM,MLB,M97A

THIRD ANGLE PROJECTION

D

051-7918
SHT

C
1
OF

109

8

7

6

5

4

3

2

1

8

7

6
U1000

5
U1300

4

3

2

1

INTEL CPU
2.X OR 3.X GHZ PENRYN
PG 9

XDP CONN
PG 12

FSB

D
PG 13

64-Bit 800/1067/1333 MHz

J6950

D
DC/BATT POWER SUPPLY
PG 60

J2900

2 UDIMMs MAIN

GPIOs

FSB INTERFACE MEMORY
PG 14

DDR2-800MHZ DDR3-1067/1333MHZ

DIMM
U4900 PG 25,26

TEMP SENSOR
Misc
CLK
PG 24 U6100 PG 41

SYNTH

POWER SENSE
PG 45

SPI
J4510

Boot ROM
SATA Conn
PG 38 1.05V/3GHZ.

J5650,5600,5610,5611,5660,5720,5730,5750

SPI
PG 52 PG 20

FAN CONN AND CONTROL
PG 48,49

HD
J4520

NVIDIA
J4900

SATA Conn
PG 38 1.05V/3GHZ.

B,0

BSB

ADC

Fan

Ser
J5100

SATA
PG 19

MCP79
LPC

SMC
PG 41

Prt

LPC Conn Port80,serial
PG 43

C
J9000

ODD

C

PG 18

U1400

LVDS CONN
PG 71

PWR
LVDS OUT

CTRL

RGB OUT
J4720 J4700 J4710 J4710 J3900,4635,4655

J9400

DP OUT

Bluetooth
PG 40

TRACKPAD/ KEYBOARD
PG 40

IR
PG 40

CAMERA
PG 40

EXTERNAL USB
Connectors
PG 39

DISPLAY PORT CONN
PG 71

HDMI OUT

(UP TO 12 DEVICES)

DVI OUT TMDS OUT

USB

0

1

2 UP TO 20 LANES3

3

4

5

6

PG 17

PG 19

7

8

9

PCI-E

PG 16

B

B
SMB
PG 20

SMB CONN

RGMII
PG 17

PCI
(UP TO FOUR PORTS)
PG 18

HDA
DIMM’s
PG 20

PG 44

U6200

Audio Codec
PG 53

U6301 U3700

U6400

U6500

U6600,6605,6610,6620

System Block Diagram
SYNC_MASTER=T18_MLB SYNC_DATE=12/12/2007

A

GB

Line In Amp
PG 54

HEADPHONE Amp
PG 55

Line Out Amp
PG 56

Speaker Amps
PG 57

E-NET
88E1116
PG 31

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

A

J3400

U3900

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

Mini PCI-E AirPort
PG 28

E-NET Conn
PG 33

J6800,6801,6802,6803

Audio Conns
PG 59

SIZE

DRAWING NUMBER
051-7918

REV.
C

D
APPLE INC.
SCALE NONE

SHT
2

OF
109

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

M97 POWER SYSTEM ARCHITECTURE
D6905
PPVIN_G3H_P3V42G3H

02
ENABLE

D6905

PBUS_VSENSE

D
01
CHGR_EN (S5)

7A FUSE PPVBAT_G3H_CHGR_REG

V
PPBUS_G3H

3.425V G3HOT LT3470 VOUT U6990

PP3V42_G3H_REG 03

SMC PWRGD RN5VD30A-F

04

Q5315
02
VIN EN_PSV VOUT

U5000

D

23
PPCPUVTT_S0_REG_R (8A MAX CURRENT) R5492 PPCPUVTT_S0

CPUVTTS0_EN (S0)

CPUVTT
(1.05V)

AC DCIN(16.5V) ADAPTER IN

6A FUSE

U7970

ENABLES VIN VOUT

A
SMC_DCIN_ISENSE

U5403
SMC_BATT_ISENSE

TPS51117 U7600
PGOOD

MCP79
PWRBTN*

06-1

PBUS SUPPLY/ BATTERY CHARGER ISL6258A U7000
J6950
3S2P Q7050 BATT_POS_F
PPVBAT_G3H_CHGR_OUT

31
PLTRST* RSMRST*

A
01 02

CPUVTTS0_PGOOD

LPC_RESET_L

U5480
CPU VCORE
VIN VOUT

V

SMC_CPU_VSENSE

MCP_PS_PWRGD PS_PWRGD

ISL9504B IMVP_VR_ON
VR_ON PGOOD

A SMC_CPU_ISENSE PPVCORE_CPU_S0_REG (44A MAX CURRENT)
28
VR_PWRGOOD_DELAY

29 26
U2850

CPUPWRGD(GPIO49)
CPU_RESET#

CPU_PWRGD

30
FSB_CPURST_L

U1400

C

(9 TO 12.6V)

25

U7400

06 P1V05S0_EN

1.05V SO
FETS
(Q7951 TO Q7953)

PP1V05_S0_FET

CPU
22
EN VIN

C

CHGR_BGATE

PPBUS_G3H
1.05V (S5)

4.6V AUDIO MAX8902A

PWRGOOD PP4V6_AUDIO_ANALOG RESET*

U6201
VOUT

MCP79
PM_SLP_S4_L

11

11-1

P3V3S3_EN

RC DELAY

06 P1V05_S5_EN 02
VIN
EN1

TPS62510 U7750
VOUT

PP1V05_S5_REG 08

U1000

32

SMC
15
SLP_S3#
11-3 P16

U4900

04
SMC_PM_G2_EN

P5VRTS0_EN_L
Q7800

5V
(RT)

VOUT1

PP5VRT_S0_REG
(4A MAX CURRENT)

PP5VRT_S0 PP3V3_S5 Q7910 PP3V3_S3_FET

17 07

U1400
PCI_RESET0#

RC DELAY

DDRREG_EN

P60

(S5)

05
P3V3S5_EN_L
VOUT2

PP3V3_S5_REG
EN2

3.3V

(4A MAX CURRENT)

15-1

11-2

02 P5VLTS3_EN
VIN

SMC_PM_G2_EN

TPS51125 U7200
PGOOD1,2
VREG3

13
P3V3S3_EN

RC DELAY

BKLT_EN

GOSHAWK6P U9701
ENA VOUT

P5V3V3_PGOOD

PPVOUT_S0_LCDBKLT

B
15
PM_SLP_S3_L

24
Q7930 PP3V3_S0_FET
ALL_SYS_PWRGD

SMC
RSMRST_OUT(P15)
PWRGD(P12) 99ms DLY

PM_RSMRST_L
IMVP_VR_ON

10

B

18 09
RSMRST_PWRGD SMC_ONOFF_L

Q3801
PM_ENET_EN_L

1.2V YUKON VIN U3850

16

ENETADD_EN P1V2ENET_EN

RUN1 RUN2

VOUT1

(1.9V) PPVOUT_ENET_AVDD_REG

LTC34074
VOUT2

(0.8A MAX CURRENT)
PP1V2_ENET_REG

(0.8A MAX CURRENT)

P3V3S0_EN Q3810 P3V3_ENET_FET
P5V3V3_PGOOD

05

IMVP_VR_ON(P16) RSMRST_IN(P13) PLT_RST* PWR_BUTTON(P90) P17(BTN_OUT) RST*

25

PM_PWRBTN_L SMC_RESET_L

Q3802 WOL_EN SMC_ADAPTER_EN
04-1

SLP_S5_L SLP_S4_L SLP_S3_L

P3V3ENET_EN_L

MCPCORESO_PGOOD CPUVTTS0_PGOOD
P5V_LT_S3_PGOOD

SLP_S5_L(P95) SLP_S4_L(P94) SLP_S3_L(P93)

02
VIN

S3 TO S0 FETS
(Q7901 & Q7971)

R5491
PP1V5_S0_FET PP1V5_S0

21
1.8V LDO
TPS79918DRV U7760

S0PGOOD_PWROK
PP1V8_S0_REG

U4900

=DDRREG_EN PM_SLP_S3_L

S5 S3

1.5V
VOUT1

=DDTVTT_EN
16-2

0.75V VOUT2

14

PP1V5_S3_REG (12A MAX CURRENT) PP0V75_S0_REG (1A MAX CURRENT)

19-1

RST*
PP3V3_S0 PP1V5_S0 PP1V05_S0 V1 V2 V3

Power Block Diagram
SYNC_MASTER=DRAGON SYNC_DATE=03/13/2008

A

RC DELAY

P1V8S0_EN

16-3

P1V05S0_EN (S0) P3V3S0_EN (S0) PBUSVSENS_EN (S0) P5VRTS0_EN_L (S0)
16-2

TPS51116 U7300 MCP_CORE
PPVCORE_S0_MCP_REG_R

20
R5490 PPVCORE_S0_MCP
VOUT2

LTC2909 U7870

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

A

RC DELAY

MCPDDR_EN
16-2

MCPCORES0_EN
16-2 11-2

EN2

(25A MAX CURRENT)
PP5VLT_S3_REG

RC DELAY

CPUVTTS0_EN

16-3

P5VLTS3_EN
EN1

5V (LT)
VOUT1

12

PP5VLT_S3

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

REV.
C

(7A MAX CURRENT)
ISL6236

RC DELAY

MCPCORES0_EN

16-1

VIN

D
APPLE INC.
SCALE NONE

16-4

02

SHT
3

OF
109

U7500

8

7

6

5

4

3

2

1

8
BOM Variants
BOM NUMBER
630-9937 630-9938

7
BOM NAME
PCBA,MLB,BETTER,M97A PCBA,MLB,BEST,M97A

6
TABLE_BOMGROUP_HEAD

5
PART NUMBER
TABLE_BOMGROUP_ITEM

4
Bar Code Labels / EEE #’s
QTY
1 1

3
REFERENCE DES
[EEE:6KM] [EEE:6KN]

2
BOM OPTION
EEE_6KM EEE_6KN

1

BOM OPTIONS
M97A_COMMON,CPU_2_0GHZ,EEE_6KM
TABLE_BOMGROUP_ITEM

DESCRIPTION
LBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL
CRITICAL CRITICAL

826-4393 826-4393

M97A_COMMON,CPU_2_4GHZ,EEE_6KN,KB_BL

BOM Groups

D

TABLE_BOMGROUP_HEAD

BOM GROUP
M97A_COMMON M97A_MCP M97A_MISC M97A_PROGPARTS M97A_DEBUG_ENG M97A_DEBUG_PVT M97A_DEBUG_PROD

BOM OPTIONS
TABLE_BOMGROUP_ITEM

D

COMMON,ALTERNATE,M97A_MCP,M97A_MISC,M97A_DEBUG_PROD,M97A_PROGPARTS
TABLE_BOMGROUP_ITEM

MCP_B02,MCP_PROD,MEMRESET_HW,MEMRESET_MCP,BOOT_MODE_USER,MCPSEQ_SMC,MCP_CS1_NO
TABLE_BOMGROUP_ITEM

ONEWIRE_PU,BKLT_PLL_NOT,DP_ESD,PROD_BMON,MIKEY
TABLE_BOMGROUP_ITEM

BOOTROM_PROG,SMC_PROG,IR_PROG,WELLSPRING_PROG
TABLE_BOMGROUP_ITEM

SMC_DEBUG_YES,XDP,XDP_CONN,LPCPLUS,VREFMRGN,TPAD_DEBUG
TABLE_BOMGROUP_ITEM

SMC_DEBUG_YES,XDP,LPCPLUS,NO_VREFMRGN
TABLE_BOMGROUP_ITEM

SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN

Module Parts
PART NUMBER
337S3693 337S3680 338S0635

QTY
1 1 1

DESCRIPTION
PDC,SLG8E,PRQ,2.0,25W,1066,R0,3M,BGA PDC,SLB4N,PRQ,2.4,25W,1066,R0,3M,BGA IC,GMCP,MCP79,35X35MM,BGA1437,B02

REFERENCE DES
U1000 U1000 U1400

CRITICAL
CRITICAL CRITICAL CRITICAL

BOM OPTION
CPU_2_0GHZ CPU_2_4GHZ MCP_B02

C

Programmable Parts
338S0563 341S2444 335S0610 341S2440 338S0375 341S2093 337S2983 341S2348 1 1 1 1 1 1 1 1
IC,SMC,HS8/2117,9X9MM,TLP,HF IC,SMC,M97A
IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

C
U4900 U4900 U6100 U6100 U4800 U4800 U5701 U5701 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL SMC_BLANK SMC_PROG BOOTROM_BLANK BOOTROM_PROG IR_BLANK IR_PROG WELLSPRING_BLANK WELLSPRING_PROG

IC,PRGRM,EFI BOOTROM,UNLOCK,M97A IC,CY7C63833,ENCORE II,USB CONTROLLER IC,IR CONTROLLER,M97A IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794 IC,WELLSPRING CONTROLLER,M97A

M97 BOARD STACK-UP
Top 2 3 4 5 6 7 8 9 10 11 BOTTOM SIGNAL GROUND SIGNAL(High SIGNAL(High GROUND POWER POWER GROUND SIGNAL(High SIGNAL(High GROUND SIGNAL Speed) Speed)

LOCKED M97A BOOTROM IS 341S2442

Alternate Parts
TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER 152S0693 152S0685 152S0138 157S0055 104S0023 128S0218 152S0516 152S0586 353S1912 337S3693 337S3680 341S2444 341S2440

BOM OPTION

REF DES

COMMENTS:
TABLE_ALT_ITEM

152S0778 152S0796 152S0694 157S0058

ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL

CYNTEC AS ALTERNATE
TABLE_ALT_ITEM

CYNTEC AS ALTERNATE
TABLE_ALT_ITEM

MAGLAYERS AS ALTERNATE
TABLE_ALT_ITEM

DELTA AS ALTERNATE
TABLE_ALT_ITEM

B

104S0018 128S0093 152S0874 152S0847 353S1381 337S3646 337S3639 341S2287 341S2285

DALE/VISHAY AS ALTERNATE
TABLE_ALT_ITEM

KEMET AS ALTERNATE
TABLE_ALT_ITEM

B

MAGLAYERS AS ALTERNATE
TABLE_ALT_ITEM

MAGLAYERS AS ALTERNATE
TABLE_ALT_ITEM

INTERSIL ISL60002 AS ALTERNATE
TABLE_ALT_ITEM

M0 CPU AS ALTERNATE FOR R0 CPU
TABLE_ALT_ITEM

M0 CPU AS ALTERNATE FOR R0 CPU
TABLE_ALT_ITEM

Speed) Speed)

M97 SMC AS ALTERNATE
TABLE_ALT_ITEM

M97 BOOTROM AS ALTERNATE

BOM Configuration

A

SYNC_MASTER=M97_MLB

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
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Revision History

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BOM CHANGES FROM M97:
REMOVE U5850, L5850, R5854, R5855, C5850, C5855, J5815 ON BETTER BOM. STUFF R5932. CHANGE R6302 FROM 10K(114S315) TO 1K(114S0218). STUFF L6300. NOSTUFF L6301. UPDATE CPU APNS TO R0 STEPPING. UPDATE M97A 630 NUMBERS AND EEE CODES, AND 051 NUMBER. UPDATE 341 NUMBERS FOR SMC AND BOOTROM. CHANGE U3700 FROM 338S0570 TO 338S0694, REALTEK PHY WITH ALDPS FIXED. ADD MOLEX SODIMM CONNECTORS AS ALTERNATE. CHANGE R9717-R9722 FROM 10.2OHM(103S0198) TO 0OHM(116S0004). CHANGE R9730 FROM 0.1OHM(114S0538) TO 0OHM(116S0004). CHANGE J3900 FROM 514-0596 TO 514-0636. CHANGE J4600 AND J4610 FROM 514-0606 TO 514-0638. CHANGE J9400 FROM 514-0610 TO 514-0637. ADD INTERSIL ISL60002(353S1381) AS ALTERNATE FOR TI REF3333(353S1912).

D

D

C

C

B

B

C

A

SYNC_MASTER=M97_MLB

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
SCALE NONE

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NOTE: All page numbers are .csa, not PDF.

See page 1 for .csa -> PDF mapping.

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D 1.05V TO 3.3V LEVEL TRANSLATOR (M97: ON ICT FIXTURE)
=PP3V3_S0_XDP
13D6 8C5

D

=PP1V05_S0_CPU
12B6 11C6 10D5 8D7 13D6

From XDP connector
JTAG_ALLDEV
1

JTAG_ALLDEV
1

C0601
0.1UF

C0602
0.1UF

71A3 13B6 10C6 10A6 6C7 71A3 13B3 10C6 10B6 71A3 13B3 10C6 10B6 6C7 71A3 13B3 10C6 10A6 6C7

IN IN IN IN

20% 2 10V CERM 402

20% 2 10V CERM 402

XDP_TCK XDP_TDI XDP_TMS XDP_TRST_L

U1000 CPU
71A3 10C6 10B6

To XDP connector and/or level translator
XDP

R0603
XDP_TDO 0
XDP_TDO_CONN
OUT
13B3

5% 1/16W MF-LF 402

XDP connector

JTAG_ALLDEV

R06011
10K
5% 1/16W MF-LF 402 2

11

1

VCCA VCCB

C
71A3 13B6 10C6 10A6 6D6

XDP_TCK XDP_TMS XDP_TRST_L

NOSTUFF

R06021
0
5% 1/16W MF-LF 402 2

71A3 13B3 10C6 10B6 6C6 71A3 13B3 10C6 10A6 6C6

2 3 4 5 12

UQFN A1 A2 A3 JTAG_ALLDEV A4 OE* GND 6

NLSV4T244
B1 B2 B3 B4 10 9 8 7

U0600

From XDP connector or via level translator
JTAG_MCP_TCK JTAG_MCP_TDI JTAG_MCP_TMS JTAG_MCP_TRST_L
13B6 21B7

U1400 MCP
XDP
13C3 21B7 23C5 13C3 21B7 23C5 13C3 21B7 21B7

C
R0604
JTAG_MCP_TDO 0
JTAG_MCP_TDO_CONN
OUT
13C3

JTAG_LVL_TRANS_EN_L

5% 1/16W MF-LF 402

XDP connector

B

B

JTAG Scan Chain

A

SYNC_MASTER=BEN

SYNC_DATE=04/04/2008

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
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Functional Test Points
Fan Connectors
TRUE TRUE TRUE PP5VRT_S0 FAN_RT_PWM FAN_RT_TACH
(NEED 3 TP)
7D3 8D5 46B4 46C4

D

I12 I15 I16

I303 I301 I302 I300 I299 I298 I293

(NEED TO ADD 3 GND TP)

I238 I237 I239

MIC FUNC_TEST MIC_HI_CONN TRUE MIC_LO_CONN TRUE MIC_SHLD_CONN TRUE SPEAKER TRUE TRUE TRUE TRUE TRUE TRUE FUNC_TEST SPKRAMP_L_N_OUT SPKRAMP_L_P_OUT SPKRAMP_R_N_OUT SPKRAMP_R_P_OUT SPKRAMP_SUB_N_OUT SPKRAMP_SUB_P_OUT

54B1 54D2

I297
54B1 54D2

I294
54D2 55A6

I288 I292 I296
53B2 54D2 53B2 54D2 53C3 54C2 53C3 54C2 53B2 54C2 53C2 54C2

I227 I226 I228 I230 I229 I231

I291 I295 I290 I271 I289

RIGHT CLUTCH CONN PP5V_S3_BTCAMERA_F TRUE PCIE_MINI_D2R_P TRUE PCIE_MINI_D2R_N TRUE PCIE_MINI_R2D_P TRUE PCIE_MINI_R2D_N TRUE PCIE_CLK100M_MINI_CONN_P TRUE PCIE_CLK100M_MINI_CONN_N TRUE USB_CAMERA_CONN_P TRUE USB_CAMERA_CONN_N TRUE PP5V_WLAN TRUE PCIE_WAKE_L TRUE SMBUS_SMC_A_S3_SCL TRUE SMBUS_SMC_A_S3_SDA TRUE CONN_USB2_BT_P TRUE CONN_USB2_BT_N TRUE MINI_CLKREQ_Q_L TRUE MINI_RESET_CONN_L TRUE
31C7 17B6 31C7 73D3 17B6 31C7 73D3 31C7 73D3 31C7 73D3 31B7 74C3 31B7 74C3 7C3 31C5 17B6 23C5 31C7 7B5 42D2 76D3 7B5 42D2 76D3 31B7 74C3 31B7 74B3 31C7 31A7

DEBUG VOLTAGE
I287 I286 I285 I284 I280
31C7 73D3

I281
31C7 73D3

I282 I376 I283 I279 I278 I270 I379 I273 I274 I275 I276 I272

(NEED TO ADD 3 GND TP)

I232 I233

I259 I258

C

I260 I245 I262 I261 I256 I257 I255 I252 I253 I254 I250 I251 I313 I246 I247 I248 I249

THERMAL FUNC_TEST MCPTHMSNS_D2_P TRUE MCPTHMSNS_D2_N TRUE LVDS FUNC_TEST PP3V3_LCDVDD_SW_F TRUE PP3V3_S0_LCD_F TRUE PPVOUT_S0_LCDBKLT TRUE LVDS_IG_DDC_CLK TRUE LVDS_IG_DDC_DATA TRUE LVDS_IG_A_DATA_N<0> TRUE LVDS_IG_A_DATA_P<0> TRUE LVDS_IG_A_DATA_N<1> TRUE LVDS_IG_A_DATA_P<1> TRUE LVDS_IG_A_DATA_N<2> TRUE LVDS_IG_A_DATA_P<2> TRUE LVDS_IG_A_CLK_F_N TRUE LVDS_IG_A_CLK_F_P TRUE LED_RETURN_1 TRUE LED_RETURN_2 TRUE LED_RETURN_3 TRUE LED_RETURN_4 TRUE LED_RETURN_5 TRUE LED_RETURN_6 TRUE
(NEED TO ADD 5 GND TP)

I319 I314 I315 I318 I317 I316

45B5 77D3 45B5 77D3

7C3 66C2 66C3

SATA HDD CONN PP5V_S0_HDD_FLT TRUE SATA_HDD_R2D_P TRUE SATA_HDD_R2D_N TRUE SATA_HDD_D2R_C_P TRUE SATA_HDD_D2R_C_N TRUE SATA_ODD_R2D_N TRUE

I393

(NEED 4 TP)
7C3 36B7 36A7 73A3 36A7 73A3 36A7 73A3 36A7 73A3 7B7 36C5 73A3

I392 I391 I390 I389 I388 I387 I386 I385 I384

(NEED TO ADD 4 GND TP)

7C3 66B2 69B3 69C1 18B3 66C5 18A3 66C5 18B3 66C2 73B3 18B3 66C2 73B3 18B3 66C2 73B3 18B3 66C2 73B3 18B3 66C2 73B3 18B3 66C2 73B3

I375 I374 I373 I372 I370 I371 I369 I368 I361 I366 I367 I365 I363 I364 I362 I360

66C2 73B3

66C2 73B3 66B3 69C1 66B3 69C1 66B3 69B1 66B3 69B1 66B3 69B1 66B3 69B1

I264 I268 I269 I267 I265 I266

SATA ODD CONN (NEED PP5V_SW_ODD TRUE SMC_ODD_DETECT TRUE SATA_ODD_D2R_C_P TRUE SATA_ODD_D2R_C_N TRUE SATA_ODD_R2D_P TRUE SATA_ODD_R2D_N TRUE
(NEED TO ADD 4 GND TP)

I359

4 TP) 7C3
36B7 39B8 36B5 73A3

I357
36D3

I358 I377 I378
36B5 73A3 36C5 73A3 7C5 36C5 73A3

IPD_FLEX_CONN PP3V3_S3_LDO TRUE PP18V5_S3 TRUE TPAD_GND_F TRUE Z2_CS_L TRUE Z2_DEBUG3 TRUE Z2_MOSI TRUE Z2_MISO TRUE Z2_SCLK TRUE Z2_BOOST_EN TRUE Z2_HOST_INTN TRUE Z2_BOOT_CFG1 TRUE Z2_CLKIN TRUE Z2_KEY_ACT_L TRUE Z2_RESET TRUE PSOC_MISO TRUE PSOC_MOSI TRUE PSOC_SCLK TRUE SMBUS_SMC_A_S3_SDA TRUE SMBUS_SMC_A_S3_SCL TRUE PSOC_F_CS_L TRUE PICKB_L TRUE KEYBOARD CONN

I383 I382 I381 I380

7C3 48B4 48C3 7C3 48C1 48D3 48B4 48C3 48C4 48C7 47C8 48C3

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

PPVCORE_S0_CPU PPCPUVTT_S0 PPVCORE_S0_MCP PP0V75_S0 PP1V05_S0 PP1V5_S0 PP1V8_S0 PP5VRT_S0 PP3V3_S0 PP1V5_S3 PP3V3_S3 PP5VLT_S3 PP1V1R1V05_S5 PP3V3_S5 PP3V42_G3H PPBUS_G3H PP3V3_ENET_PHY PP1V2R1V05_ENET PP3V3_G3_RTC PP5V_WLAN PP5V_SW_ODD PP5V_S0_HDD_FLT PP3V3_S5_AVREF_SMC PP18V5_S3 PP3V3_S3_LDO PP3V3_LCDVDD_SW_F PPVOUT_S0_LCDBKLT BKL_VREF_4V9 PP4V6_AUDIO_ANALOG SMC_PM_G2_EN PM_SLP_S4_L PM_SLP_S3_L

8D7 8D7 8C7 8C7 8C7 8B7 8B7 7D7 8D5 8C5 8D3 7B5 8D3 8C3 8B3 8B3 7A7 7B5 8D1 8C1 8B1 8B1

D

21C8 22A5 26D4 7D5 31C5 7B7 36D3 7C5 36B7 39D4 40C6

7C5 48C1 48D3 7C5 48B4 48C3 7C7 66C2 7C7 66B2 69B3 69C1

69B6 69B8 69C4 69C8 51A3 51D3 52D6

C

39D5 64D8

21C3 39C5 40A2 64C8 21C3 34B7 39C5 41A5 64D5 68D8

(NEED TO ADD 4 GND TP)

47C8 48C3 47C8 48C3 47C8 48C3

47C8 48C3 48C3 48C5 47D8 48C3 47C8 48C3 47C6 48C3 47C8 48C1 47C8 48C1 47C8 48C1 47C8 48C1 47C8 48C1 7D5 42D2 76D3 7D5 42D2 76D3

47C8 48C1 47D8 48C1

B
I312 I304

DC POWER CONN PP18V5_DCIN_FUSE TRUE ADAPTER_SENSE TRUE
(NEED TO ADD 4 GND TP)

B
7D3 8D3 7A7 7C3 8D1 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C2 47C6 47C2 47C2 47C2 47D6 47C2 47D7 47C2 47D7 47C2 47D7 47C2 47D7 47C2 47D7 47C2 47D7 47C2 47B3 47B5 47C2 47B3 47B5 47C2

(NEED 3 TP) 56D6
56D7

I354 I355 I344 I345 I346 I347 I349

I305 I306 I322 I321 I320

BATT POWER CONN PPVBAT_G3H_CONN_F TRUE GND_BATT_CONN TRUE SMBUS_SMC_BSA_SCL TRUE SMBUS_SMC_BSA_SCL TRUE SMC_BS_ALRT_L TRUE

I348

(NEED 3 TP) (NEED 3 TP)
7A7 42C5 76D3 7A7 7B7 42C5 76D3

I350
56A8

I352
56A8

I351 I353 I327

39C5 40B2 56A8

I328 I329 I343

I326 I323 I324 I325

BATT SIGNAL CONN (NEED 3 TP) PP3V42_G3H TRUE SMBUS_SMC_BSA_SCL TRUE SMBUS_SMC_BSA_SCL TRUE SMC_BIL_BUTTON_DB_L TRUE
56A5

I342 I341 I339 I340 I338 I336 I337 I333

7B5 7C3 8D1 7A7 7B7 42C5 76D3 7A7 7B7 42C5 76D3

(NEED TO ADD 3 GND TP)

A
I310 I311 I309 I308 I307

FRONT FLEX CONN PP3V42_G3H_LIDSWITCH_R TRUE PP5V_S3_IR_R TRUE IR_RX_OUT TRUE SMC_LID_R TRUE SYS_LED_ANODE_R TRUE
38B6 38B4 38C4 38B6 38B6

I335
38B6

I334 I332 I330 I331

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

PP3V3_S3 PP3V42_G3H WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD_ONOFF_L WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD

FUNC TEST
SYNC_MASTER=M97_MLB

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

A

47B3 47B5 47C2

(NEED TO ADD 1 GND TP)

(NEED TO ADD 2 GND TP)

I356

KBD BACKLIGHT CONN KBDLED_ANODE TRUE

SIZE
48A4

DRAWING NUMBER
051-7918

REV.
C

(NEED TO ADD 2 GND TP) APPLE INC.

D
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"S0,S0M" RAILS
59C1 60D1

"S3" RAILS
=PP1V5_S3_REG
58B8 7D3

"G3H" RAILS
7D3 56B4

=PPVCORE_S0_CPU_REG
(CPU VCORE PWR)

PPVCORE_S0_CPU
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=1.25V MAKE_BASE=TRUE

=PP5VRT_S0_REG

PP5VRT_S0
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE

PP1V5_S3
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE

=PP3V42_G3H_REG

PP3V42_G3H
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.42V MAKE_BASE=TRUE

7A7 7B5 7C3

7D3 7D7

=PPVCORE_S0_CPU =PPVCORE_S0_CPU_VSENSE

11B5 11D6 12D6 43D8

D
65A6 62C2

=PP5V_S0_HDD =PP5V_S0_LPCPLUS =PP5V_S0_FAN_RT

36B5 41D5 46C5 60D8 36D5 65D6 48A5 67B6 62C8

=PP5V_S0_CPU_IMVP
=PPCPUVTT_S0_REG PPCPUVTT_S0
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE
7D3

=PP1V5_S3_P1V5S0FET =PP1V5_S3_MEM_A =PP1V5_S3_MEM_B =PP1V5_S3_MEMRESET =PP3V3_S3_FET PP3V3_S3
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE

65D3 28D7 29D7 30C6

=PP5V_S0_ODD =PP5V_S0_KBDLED =PP5V_S0_DP_AUX_MUX =PP5V_S0_CPUVTTS0

7B5 7D3

=PPVIN_S5_SMCVREF =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_PWRCTL =PP3V42_G3H_CHGR =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_LIDSWITCH =PP3V42_G3H_TPAD =PP3V42_G3H_BATT
=PP3V3_S5_SMC =PP3V3_S5_LPCPLUS =PP3V42_G3H_RTC_D =PP3V42_G3H_BMON_ISNS

40C8 42C5 64B3 64D3 64D8 57A8 57C6 57D5 37B8 38B4 47B5 47C2 47C3 47C5 56A3 56B3 39D4 40C1 40C7 40D8 49D7 41C3 41C7 41D5 26D8 44B8

D

=PP1V05_S0_CPU =PP1V05_S0_MCP_FSB =PP1V05_S0_SMC_LS

6D8 10D5 11C6 12B6 13D6 9C2 14A2 14B7 22D3 24C8 40D3

61C1 44D8

=PPMCPCORE_S0_REG

PPVCORE_S0_MCP_R
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_PDCISENS =PP3V3_S3_SMBUS_SMC_MGMT =PP3V3_S3_VREFMRGN =PP3V3_S3_WLAN =PP3V3_S3_MCP_GPIO =PP3V3_S3_TPAD =PP3V3_S3_SMS

42D3 59B3 42B5 27D8 31A6 21A3 47A6 47B5 47C5 47D2 49B7 49D5 56D1 56C8

=PP18V5_DCIN_CONN

PP18V5_G3H
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=18.5V MAKE_BASE=TRUE

=PPVCORE_S0_MCP_REG_R
(MCP VCORE REG. OUTPUT)

=PP18V5_G3H_CHGR
43D8 61C8

57D8

=PPVCORE_S0_MCP_VSENSE

=PP5VLT_S3_REG

PP5VLT_S3
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE

7D3 57C1

=PPBUS_G3H

PPBUS_G3H
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 MM VOLTAGE=12.6V MAKE_BASE=TRUE

7C3

44D7 22D5 24D8 61B1

=PPVCORE_S0_MCP
(MCP VCORE AFTER SENSE RES)

PPVCORE_S0_MCP
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

7D3 65C6

=PP3V3_S0_FET

PP3V3_S0
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE

7D3

C
59C8

=PP0V75_S0_REG

PP0V75_S0
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE

7D3

=PPVTT_S0_VTTCLAMP =PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B

65B3 28A4 29A4

=PP3V3_S0_XDP =PP3V3_S0_MCP =PP3V3_S0_MCP_DAC_UF =PP3V3_S0_MCP_VPLL_UF =PP3V3_S0_ODD =PP3V3_S0_LPCPLUS =PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMBUS_MCP_0 =PP3V3_S0_FAN_RT =PP3V3_S0_AUDIO

6D8 13D6 21C2 22B3 24B8 25D4 25C7 36C7 36D5 41C3 42D5 42C3 42D8

=PP5V_S3_EXTUSB =PP5V_S3_IR =PP5V_S3_BTCAMERA =PP5V_S3_VTTCLAMP =PP5V_S3_MCPDDRFET =PP5V_S3_SYSLED =PP5V_S3_TPAD =PP5V_S3_WLAN =PP5V_S3_1V5S30V75S0 =PP5V_S3_AUDIO =PP5V_S3_AUDIO_AMP =PP5V_S3_P1V05S0FET

37C7 38B4 38D7 31C3 65A3 65D4 40B8 48C8 31C1 59C5 51A7 55D4 53B8 53C8 53D8 65B8

=PPBUS_S0_LCDBKLT =PPVIN_S0_MCPCORES0 =PPVIN_S0_MCPREG_VIN =PPVIN_S5_1V5S30V75S0 =PPVIN_S5_3V3S5 =PPVIN_S0_5VRTS0 =PPVIN_S3_5VLTS3 =PPBUS_G3HRS5 =PPCPUVCORE_VTT_ISNS_R

70D8 61C3 61C6 59C2 58C3 58C6 61D8 43B8 44B8

C

(BEFORE HIGH SIDE SENSING RES.)

44B7 46C5 51A7 51D8 52D6 54D8 55B5 60D8 66C5 18C1 19D1 21A4 25B8 24B6 21D3 21D8 24A8 40A1 40D2 45C6 45D6 44D7 68B8 68C8 28A8 29A8 64A5 64B8 44C7 44C7 63C5 32C3 63B4 48A6 42C8 34D2 59D7 27D3

=PPCPUVCORE_VTT_ISNS

PPBUS_G3H_CPU_ISNS
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 MM VOLTAGE=12.6V MAKE_BASE=TRUE

=PP3V3_S0_IMVP
65A5

(AFTER HIGH SIDE CPU VCORE & CPU VTT SENSING RES.)

=PP1V05_S0_FET

PP1V05_S0
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.1V MAKE_BASE=TRUE

7D3

=PP3V3_S0_LCD =PP3V3_S0_MCP_GPIO =PP3V3_S0_HDCPROM

=PPVTT_S3_DDR_BUF

PPVTT_S3_DDR_BUF
MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V MAKE_BASE=TRUE

=PPVIN_S0_CPUVTTS0 =PPVIN_S5_CPU_IMVP

62C6 60C2 60D4 60D8

=PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_AVDD_UF =PP1V05_S0_MCP_PLL_UF =PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_MCP_HDMI_VDD =PP1V05_S0_VMON =PP1V5_S0_FET PP1V5_S0_R
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE

8A8 24D8 24D4 24C4 8A8 24D6 18A6 25D7 64A8

=PP3V3_S0_MCP_PLL_UF
=PP3V3R1V5_S0_MCP_HDA =PP3V3_S0_SMC =PP3V3_S0_MCPTHMSNS =PP3V3_S0_CPUTHMSNS =PP5VR3V3_S0_MCPCOREISNS =PP3V3_S0_DPCONN =PPSPD_S0_MEM_A =PPSPD_S0_MEM_B =PP3V3_S0_PWRCTL =PP3V3_S0_VMON =PP3V3_S0_MCPDDRISNS =PP3V3_S0_CPUVTTISNS =PPVIN_S0_P1V8S0 =PP3V3_FC_CON =PP3V3_S0_TPAD =PP3V3_S0_SMBUS_MCP_1

"ENET" RAILS
=PP3V3_ENET_FET PP3V3_ENET_PHY
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE
7C3

65D1 44C8

=PP3V3_ENET_MCP_RMGT =PP3V3_ENET_PHY
33D7

18D3 18D7 24A5 24B6

=PP1V5_S0_FET_R

(DDR PWR REG. OUTPUT)

=PP1V5_S0_CPU =PP1V5_S0_VMON =PP1V5_FC_CON

11B6 12B6 64A8 32C3

"S5" RAILS
34B2

=PP1V05_ENET_FET

PP1V2R1V05_ENET
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

7C3

B
=PP1V5_S0 (DDR PWR AFTER SENSE RES.)
44C7

=PP1V05_S5_REG

PP1V1R1V05_S5
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

7D3

PP1V5_S0
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V05_ENET_MCP_PLL_MAC =PP1V05_ENET_MCP_RMGT

24A8

B

7D3

18D3 24D6

=PP1V8R1V5_S0_MCP_MEM =PP1V5_S0_MEM_MCP

16C3 16C7 24C8 29B3

=PP1V05_S5_MCP_VDD_AUXC =PP1V05_ENET_P1V05ENETFET =PP1V05_S5_P1V05S0FET

22A3 24D8 34C4 65B6

=PP1V05_ENET_PHY

33D2

63C2

=PP1V8_S0_REG

PP1V8_S0
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE

7D3

58B1

=PP3V3_S5_REG

PP3V3_S5
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE

7D3

=PP3V3R1V8_S0_MCP_IFP_VDD

18B6 25D7

PEX & SATA AVDD/DVDD aliases
24D1

PP1V05_S0_MCP_PEX_AVDD
MAKE_BASE=TRUE

=PP1V05_S0_MCP_PEX_AVDD0 =PP1V05_S0_MCP_PEX_AVDD1 =PP1V05_S0_MCP_PEX_DVDD0 =PP1V05_S0_MCP_PEX_DVDD1

17B3

206 mA (A01)
17A3

206 mA (A01)

17B6

A

24D8 8C7

=PP1V05_S0_MCP_PEX_DVDD 206 mA (A01)

57 mA (A01)
17A6

24D2

PP1V05_S0_MCP_SATA_AVDD
MAKE_BASE=TRUE

=PP1V05_S0_MCP_SATA_AVDD0 =PP1V05_S0_MCP_SATA_AVDD1 =PP1V05_S0_MCP_SATA_DVDD0 =PP1V05_S0_MCP_SATA_DVDD1

20B6 20B6

127 mA (A01)

=PP3V3_S5_MCP_GPIO =PP3V3_S5_ROM =PP3V3_S5_LCD =PP3V3_S5_MCP =PP3V3_S5_MCPPWRGD =PP3V3_S5_SMBUS_MCP_1 =PP3V3_S5_MCP_A01 =PP3V3_S5_PWRCTL =PP3V3_S5_P1V05ENETFET =PP3V3_S5_P3V3S3FET =PP3V3_S5_P3V3S0FET =PP3V3_S5_P1V05S5 =PP3V3_S5_P1V05FET =PP3V3_S5_MEMRESET =PP3V3_S5_P3V3ENETFET =PP3V3_S5_DP_PORT_PWR

18C7 20C1 41B5 41C7 50C6 66C8 22B3 24B8 26B8 42C7 23C4 41B4 64B3 64D4 34C5 65D8 65C8 63B7 65A8 30C6 34D5 68D8

Power Aliases
SYNC_MASTER=BEN

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

A

127 mA (A01)
24D6 8B7

=PP1V05_S0_MCP_SATA_DVDD 127 mA (A01)

20B6 20B6

43 mA (A01)

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

REV.
C

D
APPLE INC.
SCALE NONE

SHT
8

OF
109

8

7

6

5

4

3

2

1

8
Z0902
1

7
HEATSINK STANDOFFS
Z0901
1

6
17D6 17C6

5
PCI-E ALIASES
UNUSED GPU LANES =PEG_D2R_N<15:0> NC_PEG_D2R_N<15:0>
NO_TEST=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
17C3 18C6

4
DACS ALIASES
UNUSED CRT & TV-OUT INTERFACE MCP_TV_DAC_RSET NC_MCP_TV_DAC_RSET
NO_TEST=TRUE
18C6

3
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
34C5 34B5

2
SO-DIMM ALIASES
UNUSED ADDRESS PINS
28D5 29D5

1
TP_MEM_A_A15 TP_MEM_B_A15

17D6 17C6

=PEG_D2R_P<15:0> =PEG_R2D_C_N<15:0> =PEG_R2D_C_P<15:0> PEG_PRSNT_L PEG_CLK100M_P PEG_CLK100M_N

NC_PEG_D2R_P<15:0>
NO_TEST=TRUE

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH
17D3 17C3 17D3 17C3

MCP_TV_DAC_VREF MCP_CLK27M_XTALIN MCP_CLK27M_XTALOUT CRT_IG_R_C_PR CRT_IG_G_Y_Y CRT_IG_B_COMP_PB CRT_IG_HSYNC CRT_IG_VSYNC

NC_MCP_TV_DAC_VREF
NO_TEST=TRUE

MEM_A_A<15> MEM_B_A<15>

MAKE_BASE=TRUE MAKE_BASE=TRUE

NC_PEG_R2D_C_N<15:0>
NO_TEST=TRUE NO_TEST=TRUE
18C6

NC_MCP_CLK27M_XTALIN
NO_TEST=TRUE

NC_PEG_R2D_C_P<15:0>
18C6

NC_MCP_CLK27M_XTALOUT
NO_TEST=TRUE

LEFT OF CPU

ABOVE CPU
STDOFF-4.5OD.98H-1.1-3.48-TH
1

17C6

TP_PEG_PRSNT_L
18C3

NC_CRT_IG_R_C_PR
NO_TEST=TRUE

ETHERNET ALIASES
=P3V3ENET_EN =P1V05ENET_EN =PP3V3_ENET_PHY_VDDREG =RTL8211_REGOUT =RTL8211_ENSWREG PM_SLP_RMGT_L
21C3

TP_PEG_CLK100M_P
MAKE_BASE=TRUE
18C3

D

STDOFF-4.5OD.98H-1.1-3.48-TH
1

Z0903

Z0904

NC_CRT_IG_G_Y_Y
NO_TEST=TRUE

17C3

TP_PEG_CLK100M_N
MAKE_BASE=TRUE
18C3

NC_CRT_IG_B_COMP_PB
NO_TEST=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

D

UNUSED FW LANE
17B6

18C3

NC_CRT_IG_HSYNC
NO_TEST=TRUE

33C2 33C2 33C6

PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_PRSNT_L FW_CLKREQ_L PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N

TP_PCIE_FW_D2R_P
MAKE_BASE=TRUE

18C3

NC_CRT_IG_VSYNC
NO_TEST=TRUE

TP_PP3V3_ENET_PHY_VDDREG MAKE_BASE=TRUE NC_RTL8211_REGOUT
MAKE_BASE=TRUE MAKE_BASE=TRUE

BELOW MCP

BELOW CPU
17B6 17B3 17B3

TP_PCIE_FW_D2R_N
MAKE_BASE=TRUE

TP_PCIE_FW_R2D_C_P
MAKE_BASE=TRUE

LVDS ALIASES
18B3

TP_PCIE_FW_R2D_C_N
MAKE_BASE=TRUE

FAN STANDOFF
STDOFF-4.5OD.98H-1.1-3.48-TH
1

17C6

TP_PCIE_FW_PRSNT_L
MAKE_BASE=TRUE

UNUSED LVDS SIGNALS LVDS_IG_A_DATA_P<3> NC_LVDS_IG_A_DATA_P3
NO_TEST=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
71C3 10B4

17C6

TP_FW_CLKREQ_L
MAKE_BASE=TRUE

18B3

LVDS_IG_A_DATA_N<3> LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N LVDS_IG_B_DATA_P<3:0> LVDS_IG_B_DATA_N<3:0>

NC_LVDS_IG_A_DATA_N3
NO_TEST=TRUE

Z0905

CPU FSB FREQUENCY STRAPS
BSEL<2..0> 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 FSB MHZ 266 133 200 (166) 333 100 (400) (RSVD)
IN

17C3

TP_PCIE_CLK100M_FW_P
MAKE_BASE=TRUE

18B3

NC_LVDS_IG_B_CLK_P
NO_TEST=TRUE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

17C3

TP_PCIE_CLK100M_FW_N
MAKE_BASE=TRUE

18B3

NC_LVDS_IG_B_CLK_N
NO_TEST=TRUE

18B3

NC_LVDS_IG_B_DATA_P<3:0>
NO_TEST=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE

CPU_BSEL<0:2> MAKE_BASE=TRUE

=MCP_BSEL<0:2>

OUT

14A7

UNUSED EXPRESS CARD LANE
17B6

18B3

NC_LVDS_IG_B_DATA_N<3:0>
NO_TEST=TRUE

PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N PCIE_EXCARD_R2D_C_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_PRSNT_L EXCARD_CLKREQ_L
PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N

TP_PCIE_EXCARD_D2R_P
MAKE_BASE=TRUE

17B6

TP_PCIE_EXCARD_D2R_N
MAKE_BASE=TRUE

AUDIO CHASSIS GND
GND_CHASSIS_AUDIO
MAKE_BASE=TRUE
54C8 54A8

17B3

TP_PCIE_EXCARD_R2D_C_P
MAKE_BASE=TRUE

MISC MCP79 ALIASES
14B6 19B7 17B6 17B6 19D4 19D4

Z0906 TH
1 SL-3.10X2.70

OMIT

17B3

TP_PCIE_EXCARD_R2D_C_N
MAKE_BASE=TRUE

17C6

TP_PCIE_EXCARD_PRSNT_L
MAKE_BASE=TRUE

CPU_PECI_MCP FW_PME_L
GMUX_JTAG_TCK_L GMUX_JTAG_TDO GMUX_JTAG_TDI GMUX_JTAG_TMS

TP_CPU_PECI_MCP TP_FW_PME_L

Extra FSB Pull-ups
Exist in MRB but not Intel designs. Here for CYA. If found to be necessary, will move to page14.csa
24C8 22D3 14B7 14A2 8D7

MAKE_BASE=TRUE MAKE_BASE=TRUE

C

55A4 54A3

=GND_CHASSIS_AUDIO_JACK =GND_CHASSIS_AUDIO_MIC

17C6

TP_EXCARD_CLKREQ_L
MAKE_BASE=TRUE

TP_GMUX_JTAG_TCK_L MAKE_BASE=TRUE TP_GMUX_JTAG_TDO TP_GMUX_JTAG_TDI TP_GMUX_JTAG_TMS
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

17C3

TP_PCIE_CLK100M_EXCARD_P
MAKE_BASE=TRUE

=PP1V05_S0_MCP_FSB MCP_A01&MCP_A01P&MCP_A01Q NO STUFF NO STUFF

C
R0950 1
220

17C3

TP_PCIE_CLK100M_EXCARD_N
MAKE_BASE=TRUE

R0970 1
200
5% 1/16W MF-LF 402 2

R0990 1
150
5% 1/16W MF-LF 402 2

AIRPORT CARD PRESENT SIGNAL (WRONG ALAIS, REMOVE AT NEXT BOARD SPIN)

MLB MOUNTING SCREW HOLES
OMIT Z0908 3R2P5
1

31D7 17C6

PCIE_MINI_PRSNT_L
MAKE_BASE=TRUE
18D6 18D6 32C5

LAN ALIASES
18D6

5% 1/16W MF-LF 402 2

OMIT Z0909 3R2P5
1

OMIT Z0910 3R2P5
1

FOR VENICE CARD
17C6

TP_PE4_CLKREQ_L TP_PE4_PRSNT_L TP_PCIE_CLK100M_PE4P TP_PCIE_CLK100M_PE4N TP_PCIE_PE4_D2RP TP_PCIE_PE4_D2RN TP_PCIE_PE4_R2D_CP TP_PCIE_PE4_R2D_CN

FC_CLKREQ_L FC_PRSNT_L PCIE_CLK100M_FC_P PCIE_CLK100M_FC_N PCIE_FC_D2R_P PCIE_FC_D2R_N PCIE_FC_R2D_C_P PCIE_FC_R2D_C_N

MAKE_BASE=TRUE
17C6 32C3

=MCP_MII_RXER =MCP_MII_COL =MCP_MII_CRS

MCP_MII_PD
MAKE_BASE=TRUE

NO STUFF
1

NO STUFF
1

R0930
47K
71B3 60C7 14A3 10B2 71C3 14B6 10D6 71C3 14A3 13C2 10D6

1

R0960
62

R0980
150

MAKE_BASE=TRUE
17C3 32C5 73D3

MAKE_BASE=TRUE

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 2 402

OMIT Z0911 3R2P5
1

OMIT Z0912 3R2P5
1

OMIT Z0913 3R2P5
1

17C3

32C5 73D3

MAKE_BASE=TRUE
17B6 32C5 73D3

DP HOTPLUG PULL-DOWN
18B6

OUT OUT OUT OUT OUT

MAKE_BASE=TRUE
17B6 32C5 73D3

=DVI_HPD_GMUX_INT

HPLUG_DET2
MAKE_BASE=TRUE

71C3 14A3 10C8

MAKE_BASE=TRUE
17B3 32C6 73D3

1

MAKE_BASE=TRUE
17B3 32C6 73D3

MAKE_BASE=TRUE

5% 1/16W MF-LF 2 402

R0940 20K

71C3 14A3 10B8

CPU_DPRSTP_L FSB_BREQ0_L FSB_CPURST_L CPU_INTR CPU_NMI

VENICE BOARD STANDOFFS

B

STDOFF-4.0OD3.0H-TH
1

Z0914

VENICE

STDOFF-4.0OD3.0H-TH
1

Z0915

VENICE

STDOFF-4.0OD3.0H-TH
1
20C3 20C3 20D3 20D3 20C3 20C3 20D3 20D3

Z0916

VENICE

USB ALIASES
UNUSED USB PORTS

USB_EXTC_P USB_EXTC_N USB_EXTD_P USB_EXTD_N USB_EXCARD_P USB_EXCARD_N
USB_MINI_P USB_MINI_N

TP_USB_EXTC_P TP_USB_EXTC_N TP_USB_EXTD_P TP_USB_EXTD_N TP_USB_EXCARD_P TP_USB_EXCARD_N
TP_USB_MINI_P TP_USB_MINI_N
MAKE_BASE=TRUE MAKE_BASE=TRUE

B
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

EMI IO POGO PINS
ZS0900
1.4DIA-SHORT-EMI-MLB-M97-M98
SM
1 1

ZS0901
1.4DIA-SHORT-EMI-MLB-M97-M98
SM

ZS0902
1.4DIA-SHORT-EMI-MLB-M97-M98
SM
1

ZS0903
1.4DIA-SHORT-EMI-MLB-M97-M98
SM
1

EMI POGO PINS

SIGNAL ALIAS
ZS0906
2.0DIA-TALL-EMI-MLB-M97-M98
SM
1 1

A

ZS0904
2.0DIA-TALL-EMI-MLB-M97-M98
SM
1

ZS0905
2.0DIA-TALL-EMI-MLB-M97-M98
SM
1

ZS0907
2.0DIA-TALL-EMI-MLB-M97-M98
SM

SYNC_MASTER=M97_MLB

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
SCALE NONE

SHT
9

OF
109

8

7

6

5

4

3

2

1

8
71D3 14D6 71D3 14D6 71D3 14D6 71D3 14D6 71D3 14D6 71D3 14D6 71D3 14C6 71D3 14C6 71D3 14C6 71D3 14C6

7
OMIT
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

6
ADS* BNR* BPRI* DEFER* DRDY* DBSY*
H1 E2 G5

5
14B6 71C3 14B6 71C3 14B3 71C3

4

3

2

1

D

71D3 14C6 71D3 14C6 71D3 14C6 71D3 14C6 71D3 14B6

FSB_A_L<3> FSB_A_L<4> FSB_A_L<5> FSB_A_L<6> FSB_A_L<7> FSB_A_L<8> FSB_A_L<9> FSB_A_L<10> FSB_A_L<11> FSB_A_L<12> FSB_A_L<13> FSB_A_L<14> FSB_A_L<15> FSB_A_L<16> FSB_ADSTB_L<0>

J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1

A3* A4* A5* A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0*

U1000
PENRYN
FCBGA

FSB_ADS_L FSB_BNR_L FSB_BPRI_L FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L FSB_BREQ0_L
71B3

BI BI BI

1 OF 4

=PP1V05_S0_CPU

6D8 8D7 11C6 12B6 13D6

H5 F21 E1

BI BI BI

14B3 71C3 14B6 71C3 14B6 71C3

R1000 1
54.9
1% 1/16W MF-LF 402

ADDR GROUP0

BR0* CONTROL IERR* INIT* LOCK*

F1

BI

9B2 14B6 71C3

2

D20 B3

CPU_IERR_L CPU_INIT_L FSB_LOCK_L

D
IN
14A3 71C3

H4

BI

14B6 71C3

71D3 14B6 71D3 14B6 71D3 14B6 71D3 14B6 71D3 14B6

BI BI BI BI BI

FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>

K3 H2 K2 J3 L1

REQ0* REQ1* REQ2* REQ3* REQ4*

RESET* RS0* RS1* RS2* TRDY*

C1 F3 F4 G3 G2

FSB_CPURST_L FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2> FSB_TRDY_L

IN IN IN IN IN

9B2 13C2 14A3 71C3 14A6 71C3 14A6 71C3 14A6 71C3 14B6 71C3

71C3 14C6 71C3 14C6 71C3 14C6 71C3 14C6 71C3 14C6 71C3 14C6 71C3 14C6 71C3 14C6 71C3 14C6 71C3 14C6 71C3 14C6 71C3 14C6 71C3 14C6

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

C

71C3 14C6 71C3 14C6 71C3 14C6 71C3 14C6 71C3 14C6 71C3 14C6 71C3 14B6

FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<1>

Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1

A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1* A20M* FERR* IGNNE*

HIT* HITM* BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR*

G6 E4

FSB_HIT_L FSB_HITM_L XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L

BI BI

14B6 71C3 14B6 71C3 71D3 14D3

OMIT
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20

BI BI BI BI BI

13C6 71A3 13C6 71A3 13C6 71A3 13C6 71A3 13C6 71A3

R1001 1
54.9
1% 1/16W MF-LF 402

71D3 14D3 71D3 14D3 71D3 14D3 71D3 14D3

2

71D3 14D3

BI IN IN OUT IN IN OUT
6C7 6D6 10A6 13B6 71A3 6C6 10B6 13B3 71A3 6C4 10B6 71A3 6C6 6C7 10B6 13B3 71A3 6C6 6C7 10A6 13B3 71A3 13B3 26A3

13C6 71A3

71D3 14D3 71D3 14D3 71D3 14D3 71D3 14D3 71D3 14D3 71D3 14D3

R1002 1
68
5% 1/16W MF-LF 402

71D3 14D3 71D3 14D3 71D3 14D3 71D3 14D3

THERMAL PROCHOT* THERMDA THERMDC THERMTRIP* ICH
D21 A24 B25

2

71D3 14D6

CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N PM_THRMTRIP_L

OUT OUT OUT
45D5 77D3 45D5 77D3

14B6 40D4 60C8 71C3

71D3 14D6 71D3 14D6

FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_DSTB_L_N<0> FSB_DSTB_L_P<0> FSB_DINV_L<0>

E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25

D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0*

U1000
PENRYN
FCBGA

ADDR GROUP1

2 OF 4

D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2*

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_DSTB_L_N<2> FSB_DSTB_L_P<2> FSB_DINV_L<2>

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

14C3 71D3 14C3 71D3 14C3 71D3 14C3 71D3 14C3 71D3 14C3 71D3 14C3 71D3 14C3 71D3 14C3 71D3 14C3 71D3 14C3 71D3 14C3 71D3 14C3 71D3 14C3 71D3 14C3 71D3 14B3 71D3 14D6 71D3 14D6 71D3 14D6 71D3

XDP/ITP SIGNALS

DATA GRP 0

DATA GRP 2

C

71C3 14A3 71C3 14B7 71C3 14A3

IN CPU_A20M_L OUT CPU_FERR_L IN CPU_IGNNE_L

A6 A5 C4

C7

OUT

14B7 40C4 71B3

71D3 14D3 71D3 14D3

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

71B3 14A3 71C3 14A3 9B2 71C3 14A3 9B2 71B3 14A3

IN IN IN IN

CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L TP_CPU_RSVD_M4 TP_CPU_RSVD_N5 TP_CPU_RSVD_T2 TP_CPU_RSVD_V3 TP_CPU_RSVD_B2 TP_CPU_RSVD_F6 TP_CPU_RSVD_D2 TP_CPU_RSVD_D22 TP_CPU_RSVD_D3

D5 C6 B4 A3

STPCLK* LINT0 LINT1 SMI* RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8

H CLK

71D3 14D3 71D3 14D3 71D3 14D3

BCLK0 BCLK1

A22 A21

FSB_CLK_CPU_P FSB_CLK_CPU_N

IN IN

14B3 71B3 14B3 71B3

71D3 14C3 71D3 14C3 71D3 14C3

M4 N5 T2 V3 B2 F6 D2 D22 D3

71D3 14C3 71D3 14C3 71D3 14C3

RESERVED

71D3 14C3 71D3 14C3 71D3 14C3 71D3 14C3

1

71D3 14C3

R1005
1K
1% 1/16W MF-LF 402

71D3 14D6 71D3 14D6 71D3 14D6

CPU JTAG Support

B
71A3 13B3 10C6 6C7 6C6

FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_DSTB_L_N<1> FSB_DSTB_L_P<1> FSB_DINV_L<1>

N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24

D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1* GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL0 BSEL1 BSEL2

D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* COMP0 COMP1 COMP2 COMP3 DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI*

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63> FSB_DSTB_L_N<3> FSB_DSTB_L_P<3> FSB_DINV_L<3>

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

14B3 71D3 14B3 71D3 14B3 71D3 14B3 71D3 14B3 71D3 14B3 71D3 14B3 71D3 14B3 71D3 14B3 71D3 14B3 71D3 14B3 71D3 14B3 71D3 14B3 71D3 14B3 71D3 14B3 71D3 14B3 71D3 14D6 71D3 14D6 71D3 14D6 71D3

DATA GRP 1

DATA GRP 3

R1090
XDP_TMS
1

2

B

54.9
1% 1/16W MF-LF 402

2

71B3 27B1

R1091
71A3 13B3 10C6 6C6

1

XDP_TDI

1

54.9
1% 1/16W MF-LF 402

R1006
2.0K NO STUFF

2

R1092
54.9
1 1% 1/16W MF-LF 402 2

1% 1/16W MF-LF 2 402

71A3 10C6 6C4

XDP_TDO

C1014
NO STUFF
0.1uF
10% 16V X5R 402

1

PLACEMENT_NOTE=Place R1092 near ITP connector (if present)

R1010
1

2

71C3 9C2 71C3 9C2 71C3 9C2

0
5% 1/16W MF-LF 402

2

NO STUFF

NO STUFF
1

CPU_GTLREF CPU_TEST1 CPU_TEST2 TP_CPU_TEST3 CPU_TEST4 TP_CPU_TEST5 TP_CPU_TEST6 TP_CPU_TEST7 OUT CPU_BSEL<0> OUT CPU_BSEL<1> OUT CPU_BSEL<2>

AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21

MISC

R26 71A3 CPU_COMP<0> U26 71B3 CPU_COMP<1> AA1 71B3 CPU_COMP<2> Y1
71B3

CPU_COMP<3> CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L CPU_PSI_L

E5 B5 D24 D6 D7 AE6

IN IN IN IN IN OUT

9C2 14A3 60C7 71B3 14A3 71B3 14A3 71B3 13C7 14A3 71C3 14A3 71B3 60C7

R1023 1
54.9
1% 1/16W MF-LF 402

R1021 1
54.9
1% 1/16W MF-LF 402

2

2

1

R1022
27.4
1% 1/16W MF-LF 402

1

R1020
27.4
1% 1/16W MF-LF 402

R1093
71A3 13B6 10C6 6D6 6C7

R1011 1
1K
5% 1/16W MF-LF 402 2

R1012
1K PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU. PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU. PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.
2

XDP_TCK

1

54.9
1% 1/16W MF-LF 402

2

R1094
71A3 13B3 10C6 6C7 6C6

5% 1/16W MF-LF 2 402

2

XDP_TRST_L

1

649
1% 1/16W MF-LF 402

2

PLACEMENT_NOTE (all 4 resistors): Place within 12.7mm of CPU

CPU FSB

A
SYNC FROM T18 CHANGE CPU FROM SOCKET TO BGA SYMBOL

SYNC_MASTER=T18_MLB

SYNC_DATE=12/12/2007

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
SCALE NONE

SHT
10

OF
109

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

A4

P6 P21

(CPU CORE POWER) =PPVCORE_S0_CPU
8D7 11B5 12D6

A8 A11 A14

OMIT

U1000
PENRYN
FCBGA

P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4

D

A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9

AB20

OMIT

AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18

44 41 30.4 23

A A A A

(SV (SV (SV (LV

Design Target) HFM) LFM) Design Target)

A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11

4 OF 4

D

U1000
PENRYN
FCBGA

3 OF 4

VCC

AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14

C

D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9

C

VCC

AF15 AF17 AF18 AF20

(CPU IO POWER 1.05V) =PP1V05_S0_CPU
6D8 8D7 10D5 12B6 13D6

E14 E16 E19

VSS

VSS

AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25

G21 V6 J6 K6 M6 J21 K21

4500 mA (before VCC stable) 2500 mA (after VCC stable)

E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23

VCCP

M21 N21 N6 R21 R6 T21 T6 V21 W21

(CPU INTERNAL PLL POWER 1.5V) =PP1V5_S0_CPU
8B7 12B6

G26 H3 H6

(BR1#)
B26

B

AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18

VCCA VID0 VID1 VID2 VID3 VID4 VID5 VID6

C26

130 mA

H21 H24

B

AD6 AF5 AE5 AF4 AE3 AF3 AE2

CPU_VID<0> CPU_VID<1> CPU_VID<2> CPU_VID<3> CPU_VID<4> CPU_VID<5> CPU_VID<6>

OUT OUT OUT OUT OUT OUT OUT

60C7 71A3 60C7 71A3 60C7 71A3 60C7 71A3 60C7 71A3 60C7 71A3 60C7 71A3

J2 J5 J22

=PPVCORE_S0_CPU
1

8D7 11D6 12D6

J25 K1

R1100
100
1% 1/16W MF-LF 402

K4 K23 K26 L3

2

VCCSENSE

AF7

CPU_VCCSENSE_P

OUT

60A5 71A3

L6 L21

PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs. PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.

L24 M2 M5

VSSSENSE

AE7

CPU_VCCSENSE_N
1

OUT

60A5 71A3

R1101
100
1% 1/16W MF-LF 402

M22 M25 N1 N4 N23 N26 P3 B1

2

(Socket-P KEY)

AF25

CPU Power & Ground

A
SYNC FROM T18 CHANGE CPU FROM SOCKET TO BGA SYMBOL

SYNC_MASTER=T18_MLB

SYNC_DATE=12/12/2007

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
Current numbers from Merom for Santa Rosa EMTS, doc #20905.
SCALE NONE

SHT
11

OF
109

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

CPU VCore HF and Bulk Decoupling
4X 330UF. 20X 22UF 0805
PLACEMENT_NOTE (C1200-C1219):
11D6 11B5 8D7

=PPVCORE_S0_CPU Place inside socket cavity on secondary side. CRITICAL
1

D
2

CRITICAL
1

CRITICAL
1

CRITICAL
1

CRITICAL
1

CRITICAL
1

CRITICAL
1

CRITICAL
1

CRITICAL
1

CRITICAL
1

D

C1200
22UF
20% 6.3V CERM-X5R 805

C1201
22UF
20% 6.3V CERM-X5R 805

C1202
22UF
20% 6.3V CERM-X5R 805

C1203
22UF
20% 6.3V CERM-X5R 805

C1204
22UF
20% 6.3V CERM-X5R 805

C1205
22UF
20% 6.3V CERM-X5R 805

C1206
22UF
20% 6.3V CERM-X5R 805

C1207
22UF
20% 6.3V CERM-X5R 805

C1208
22UF
20% 6.3V CERM-X5R 805

C1209
22UF
20% 6.3V CERM-X5R 805

2

2

2

2

2

2

2

2

2

CRITICAL
1

CRITICAL
1

CRITICAL
1

CRITICAL
1

CRITICAL
1

CRITICAL
1

CRITICAL
1

CRITICAL
1

CRITICAL
1

CRITICAL
1

C1210
22UF
20% 6.3V CERM-X5R 805

C1211
22UF
20% 6.3V CERM-X5R 805

C1212
22UF
20% 6.3V CERM-X5R 805

C1213
22UF
20% 6.3V CERM-X5R 805

C1214
22UF
20% 6.3V CERM-X5R 805

C1215
22UF
20% 6.3V CERM-X5R 805

C1216
22UF
20% 6.3V CERM-X5R 805

C1217
22UF
20% 6.3V CERM-X5R 805

C1218
22UF
20% 6.3V CERM-X5R 805

C1219
22UF
20% 6.3V CERM-X5R 805

2

2

2

2

2

2

2

2

2

2

C
PLACEMENT_NOTE (C1240-C1243): Place on secondary side. CRITICAL
1

C

CRITICAL
1

CRITICAL
1

CRITICAL
1

C1240
330UF
20% 2.0V POLY-TANT D2T-SM2 3

C1241
330UF
20% 2.0V POLY-TANT D2T-SM2 3

C1242
330UF
20% 2.0V POLY-TANT D2T-SM2 3

C1243
330UF
20% 2.0V POLY-TANT D2T-SM2

3

2

2

2

2

VCCA (CPU AVdd) DECOUPLING
1x 10uF, 1x 0.01uF
11B6 8B7

=PP1V5_S0_CPU PLACEMENT_NOTE=Place C1281 near CPU pin B26.

C1250
10uF
20% 6.3V X5R 603

1

1

C1251
0.01UF
10% 16V CERM 402

2

2

B
VCCP (CPU I/O) DECOUPLING
1x 330uF, 6x 0.1uF 0402
13D6 11C6 10D5 8D7 6D8

B

=PP1V05_S0_CPU PLACEMENT_NOTE=Place C1260 between CPU & NB. CRITICAL

C1260
330UF
20% 2.0V POLY-TANT D2T-SM2

1

1

C1261
0.1UF
20% 10V CERM 402

1

C1262
0.1UF
20% 10V CERM 402

1

C1263
0.1UF
20% 10V CERM 402

1

C1264
0.1UF
20% 10V CERM 402

1

C1265
0.1UF
20% 10V CERM 402

1

C1266
0.1UF
20% 10V CERM 402

2

3

2

2

2

2

2

2

CPU Decoupling

A
SYNC FROM T18 REMOVE NO STUFF CAPS C1220 TO C1231 REMOVE C1244 & C1245 CHANGE C1240-C1243 AND C1260 FROM 128S0241(9 MILLI-OHM) TO 128S0231(6 MILLI-OHM)

SYNC_MASTER=RAYMOND

SYNC_DATE=03/31/2008

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
SCALE NONE

SHT
12

OF
109

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

D

MCP79-specific pinout
8C5 6D8 12B6 11C6 10D5 8D7 6D8

=PP3V3_S0_XDP =PP1V05_S0_CPU XDP

XDP_CONN CRITICAL

J1300
6-1747769-0
F-ST-SM
64 62

R1315 1
54.9
1% 1/16W MF-LF 402 2

1
71A3 10C5 71A3 10C6

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

BI BI

XDP_BPM_L<5> XDP_BPM_L<4> XDP_BPM_L<3> XDP_BPM_L<2> XDP_BPM_L<1> XDP_BPM_L<0> TP_XDP_OBSFN_B0 TP_XDP_OBSFN_B1 TP_XDP_OBSDATA_B0 TP_XDP_OBSDATA_B1 TP_XDP_OBSDATA_B2 TP_XDP_OBSDATA_B3

OBSFN_A0 OBSFN_A1 OBSDATA_A0 OBSDATA_A1 OBSDATA_A2 OBSDATA_A3 OBSFN_B0 OBSFN_B1 OBSDATA_B0 OBSDATA_B1 OBSDATA_B2 OBSDATA_B3 PWRGD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 SDA SCL TCK1 TCK0 XDP

3 5 7

OBSFN_C0 OBSFN_C1 OBSDATA_C0 OBSDATA_C1 OBSDATA_C2 OBSDATA_C3 OBSFN_D0 OBSFN_D1 OBSDATA_D0 OBSDATA_D1 OBSDATA_D2 OBSDATA_D3

JTAG_MCP_TDO_CONN JTAG_MCP_TRST_L MCP_DEBUG<0> MCP_DEBUG<1> MCP_DEBUG<2> MCP_DEBUG<3> JTAG_MCP_TDI JTAG_MCP_TMS MCP_DEBUG<4> MCP_DEBUG<5> MCP_DEBUG<6> MCP_DEBUG<7>

IN OUT

6C3 6C5 21B7

71A3 10C6 71A3 10C6

BI IN

9 11 13

BI BI

19D7 74D3 19D7 74D3

71A3 10C6 71A3 10C6

IN IN

15 17 19 21 23 25 27 29 31 33 35 37

BI BI

19D7 74D3 19D7 74D3

C

OUT OUT

6C5 21B7 23C5 6C5 21B7 23C5

C

BI BI

19D7 74D3 19D7 74D3

XDP

BI BI

19D7 74D3 19D7 74D3

R1399
71C3 14A3 10B2

IN

CPU_PWRGD

1

1K
5% 1/16W MF-LF 402

2

XDP_PWRGD XDP_OBS20 PM_LATRIGGER_L JTAG_MCP_TCK SMBUS_MCP_0_DATA SMBUS_MCP_0_CLK XDP_TCK

39 41 43 45 47 49

23C5 19C4 21B7 6C5

IN OUT

74B3 42D8 21C3 74B3 42D8 21C3

BI BI

51 53

NC

55 57 59

71A3 10C6 10A6 6D6 6C7

OUT

FSB_CLK_ITP_P ITPCLK/HOOK4 FSB_CLK_ITP_N ITPCLK#/HOOK5 VCC_OBS_CD 71A3 XDP_CPURST_L RESET#/HOOK6 XDP_DBRESET_L DBR#/HOOK7 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V. XDP_TDO_CONN TDO XDP_TRST_L TRSTn XDP_TDI TDI XDP_TMS TMS XDP_PRESENT# XDP
1

IN IN

14B3 71B3 14B3 71B3

XDP

R1303
1

1K
5% 1/16W MF-LF 402

2

FSB_CPURST_L

IN

9B2 10D6 14A3 71C3

OUT

10C6 26A3

PLACEMENT_NOTE=Place close to CPU to minimize stub.

IN OUT OUT OUT

6C3 6C6 6C7 10A6 10C6 71A3 6C6 10B6 10C6 71A3 6C6 6C7 10B6 10C6 71A3

C1300
0.1uF
10% 16V X5R 402

1

61 63
2 2

C1301
0.1uF
10% 16V X5R 402

516S0625

B

B

eXtended Debug Port (XDP)

A
SYNC FROM T18 CHANGE STANDARD XDP CONNECTOR TO SMALLER ONE 516S0625 RENAME JTAG_MCP_TDO TO JTAG_MCP_TDO_CONN RENAME XDP_TDO TO XDP_TDO_CONN

SYNC_MASTER=T18_MLB

SYNC_DATE=12/12/2007

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
SCALE NONE

SHT
13

OF
109

8

7

6

5

4

3

2

1

8

7

6

5
OMIT

4
U1400
MCP79-TOPO-B
BGA (1 OF 11)

3

2

1

71D3 10C4 71D3 10C4 71D3 10C4

BI BI BI BI BI BI BI BI BI BI BI BI

FSB_DSTB_L_P<0> FSB_DSTB_L_N<0> FSB_DINV_L<0> FSB_DSTB_L_P<1> FSB_DSTB_L_N<1> FSB_DINV_L<1> FSB_DSTB_L_P<2> FSB_DSTB_L_N<2> FSB_DINV_L<2> FSB_DSTB_L_P<3> FSB_DSTB_L_N<3> FSB_DINV_L<3> FSB_A_L<3> FSB_A_L<4> FSB_A_L<5> FSB_A_L<6> FSB_A_L<7> FSB_A_L<8> FSB_A_L<9> FSB_A_L<10> FSB_A_L<11> FSB_A_L<12> FSB_A_L<13> FSB_A_L<14> FSB_A_L<15> FSB_A_L<16> FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<0> FSB_ADSTB_L<1> FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>

T40 U40 V41 W39 W37 V35 N37 L36 N35 M39 M41 J41

CPU_DSTBP0# CPU_DSTBN0# CPU_DBI0# CPU_DSTBP1# CPU_DSTBN1# CPU_DBI1# CPU_DSTBP2# CPU_DSTBN2# CPU_DBI2# CPU_DSTBP3# CPU_DSTBN3# CPU_DBI3# CPU_A3# CPU_A4# CPU_A5# CPU_A6# CPU_A7# CPU_A8# CPU_A9# CPU_A10# CPU_A11# CPU_A12# CPU_A13# CPU_A14# CPU_A15# CPU_A16# CPU_A17# CPU_A18# CPU_A19# CPU_A20# CPU_A21# CPU_A22# CPU_A23# CPU_A24# CPU_A25# CPU_A26# CPU_A27# CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32# CPU_A33# CPU_A34# CPU_A35# CPU_ADSTB0# CPU_ADSTB1# CPU_REQ0# CPU_REQ1# CPU_REQ2# CPU_REQ3# CPU_REQ4# CPU_ADS# CPU_BNR# CPU_BR0# CPU_BR1# CPU_DBSY# CPU_DRDY# CPU_HIT# CPU_HITM# CPU_LOCK# CPU_TRDY# CPU_PECI CPU_PROCHOT# CPU_THERMTRIP# CPU_FERR# CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 CPU_RS0# CPU_RS1# CPU_RS2#

71D3 10B4 71D3 10B4 71D3 10B4

D

71D3 10C2 71D3 10C2 71D3 10C2

71D3 10B2 71D3 10B2 71D3 10B2

71D3 10D8 71D3 10D8 71D3 10D8 71D3 10D8 71D3 10D8 71D3 10D8 71D3 10D8 71D3 10D8 71D3 10D8 71D3 10D8 71D3 10D8 71D3 10D8 71D3 10D8 71D3 10D8 71C3 10D8 71C3 10C8 71C3 10C8 71C3 10C8 71C3 10C8

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

AC34 AE38 AE34 AC37 AE37 AE35 AB35 AF35 AG35 AG39 AE33 AG37 AG38 AG34 AN38 AL39 AG33 AL33 AJ33 AN36 AJ35 AJ37 AJ36 AJ38 AL37 AL34 AN37 AJ34 AL38 AL35 AN34 AR39 AN35 AE36 AK35

C

71C3 10C8 71C3 10C8 71C3 10C8 71C3 10C8 71C3 10C8 71C3 10C8 71C3 10C8 71C3 10C8 71C3 10C8 71C3 10C8 71C3 10C8 71C3 10C8 71C3 10C8 71C3 10C8

71D3 10D8 71C3 10C8

71D3 10D8

BI BI BI BI BI

AC38 AA33 AC39 AC33 AC35

24C8 22D3 14A2 9C2 8D7

=PP1V05_S0_MCP_FSB

71D3 10D8 71D3 10D8 71D3 10D8

R1410 1
54.9
1% 1/16W MF-LF 402

R1415 1
62
5% 1/16W MF-LF 402

1

71D3 10D8

R1416
62
5% 1/16W MF-LF 402
71C3 10D6 71C3 10D6 71C3 10D6 9B2

2

2

2

B
71B3 40C4 10C6 71C3 10C8

IN IN

PM_THRMTRIP_L CPU_FERR_L

71C3 10D6 71C3 10D6 71C3 10D6 71C3 10D6 71C3 10D6 71C3 10D6

FSB_ADS_L FSB_BNR_L BI FSB_BREQ0_L BI 71C3 FSB_BREQ1_L FSB_DBSY_L BI FSB_DRDY_L BI FSB_HIT_L BI FSB_HITM_L BI FSB_LOCK_L IN FSB_TRDY_L OUT
BI OUT OUT

AD42 AD43 AE40 AL32 AD39 AD41 AB42 AD40 AC43 AE41

CPU_D0# CPU_D1# CPU_D2# CPU_D3# CPU_D4# CPU_D5# CPU_D6# CPU_D7# CPU_D8# CPU_D9# CPU_D10# CPU_D11# CPU_D12# CPU_D13# CPU_D14# CPU_D15# CPU_D16# CPU_D17# CPU_D18# CPU_D19# CPU_D20# CPU_D21# CPU_D22# CPU_D23# CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36# CPU_D37# CPU_D38# CPU_D39# CPU_D40# CPU_D41# CPU_D42# CPU_D43# CPU_D44# CPU_D45# CPU_D46# CPU_D47# CPU_D48# CPU_D49# CPU_D50# CPU_D51# CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59# CPU_D60# CPU_D61# CPU_D62# CPU_D63# CPU_BPRI# CPU_DEFER#

Y43 W42 Y40 W41 Y39 V42 Y41 Y42 P42 U41 R42 T39 T42 T41 R41 T43 W35 AA37 W33 W34 AA36 AA34 AA38 AA35 U38 U36 U35 U33 U34 W38 R33 U37 N34 N33 R34 R35 P35 R39 R37 R38 L37 L39 L38 N36 N38 J39 J38 J37 L42 M42 P41 N41 N40 M40 H40 K42 H41 L41 H43 H42 K41 J40 H39 M43

FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63> FSB_BPRI_L FSB_DEFER_L

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

10C4 71D3 10C4 71D3 10C4 71D3 10C4 71D3 10C4 71D3 10C4 71D3 10C4 71D3 10C4 71D3 10C4 71D3 10C4 71D3 10C4 71D3 10C4 71D3 10C4 71D3 10C4 71D3 10C4 71D3 10C4 71D3 10C4 71D3 10C4 71D3 10C4 71D3 10C4 71D3 10C4 71D3 10B4 71D3 10B4 71D3 10B4 71D3 10B4 71D3 10B4 71D3 10B4 71D3 10B4 71D3 10B4 71D3 10B4 71D3 10B4 71D3 10B4 71D3 10C2 71D3 10C2 71D3 10C2 71D3 10C2 71D3 10C2 71D3 10C2 71D3 10C2 71D3 10C2 71D3 10C2 71D3 10C2 71D3 10C2 71D3 10C2 71D3 10C2 71D3 10C2 71D3 10C2 71D3 10C2 71D3 10C2 71D3 10C2 71D3 10C2 71D3 10C2 71D3 10C2 71D3 10B2 71D3 10B2 71D3 10B2 71D3 10B2 71D3 10B2 71D3 10B2 71D3 10B2 71D3 10B2 71D3 10B2 71D3 10B2 71D3 10B2 71D3

D

C

FSB

B

AA41 AA40

OUT OUT

10D6 71C3 10D6 71C3

NO STUFF

NO STUFF

NO STUFF
1
9C4

R1420
1K
5% 1/16W MF-LF 402

1

R1421
1K
5% 1/16W MF-LF 402

1

R1422
1K
5% 1/16W MF-LF 402

71C3 60C8 40D4 10C5

CPU_PECI_MCP CPU_PROCHOT_L

E41 AJ41 AG43 AH40

BCLK_OUT_CPU_P BCLK_OUT_CPU_N BCLK_OUT_ITP_P BCLK_OUT_ITP_N BCLK_OUT_NB_P BCLK_OUT_NB_N

G42 G41 AL43 AL42 AL41 AK42

FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_ITP_P FSB_CLK_ITP_N FSB_CLK_MCP_P 71B3 FSB_CLK_MCP_N
71B3

OUT OUT OUT OUT

10B6 71B3 10B6 71B3

13C3 71B3 13C3 71B3

2

2

2

9C1 9C1 9C1

IN IN IN

=MCP_BSEL<2> =MCP_BSEL<1> =MCP_BSEL<0>
71C3 10D6 71C3 10D6 71C3 10D6

(MCP_BSEL<2>) (MCP_BSEL<1>) (MCP_BSEL<0>)
OUT OUT OUT
24C2

F42 D42 F41

Loop-back clock for delay matching. FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2> PP1V05_S0_MCP_PLL_FSB 206 20 29 15 mA mA mA mA
AG27 AH27 AG28 AH28 AC41 AB41 AC42

BCLK_IN_N BCLK_IN_P

AK41 AJ40

R1430
49.9
1% 1/16W MF-LF 402

1

1

R1435
49.9
1% 1/16W MF-LF 402

270 mA (A01)

2

2

+V_DLL_DLCELL_AVDD +V_PLL_MCLK +V_PLL_FSB +V_PLL_CPU BCLK_VML_COMP_VDD BCLK_VML_COMP_GND CPU_COMP_VCC CPU_COMP_GND

A
R1431 1
49.9
1% 1/16W MF-LF 402 1

CPU_A20M# CPU_IGNNE# CPU_INIT# CPU_INTR CPU_NMI CPU_SMI# CPU_PWRGD CPU_RESET# CPU_SLP# CPU_DPSLP# CPU_DPWR# CPU_STPCLK# CPU_DPRSTP#

AF41 AH39 AH42 AF42 AG41 AH41 AH43 H38 AM33 AN33 AM32 AG42 AN32

CPU_A20M_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_SMI_L CPU_PWRGD FSB_CPURST_L FSB_CPUSLP_L CPU_DPSLP_L FSB_DPWR_L CPU_STPCLK_L CPU_DPRSTP_L

OUT OUT OUT OUT OUT OUT

10C8 71C3 10C8 71C3 10D6 71C3 9B2 10C8 71C3 9B2 10B8 71C3 10B8 71B3

=PP1V05_S0_MCP_FSB NO STUFF
1

8D7 9C2 14B7 22D3 24C8

R1440
150
5% 1/16W MF-LF 402

MCP CPU Interface
SYNC_MASTER=T18_MLB
10B2 13C7 71C3

2

SYNC_DATE=04/04/2008

71B3 71B3

MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND MCP_CPU_COMP_VCC MCP_CPU_COMP_GND

AM39 AM40

OUT OUT OUT OUT OUT OUT OUT
9B2 10D6 13C2 71C3

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

71B3 71B3

AM43 AM42

10B2 71B3 10B2 71B3 10B2 71B3 10C8 71B3 9C2 10B2 60C7 71B3

R1436
49.9
1% 1/16W MF-LF 402

2

2

REV.
C

D
APPLE INC.
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
SCALE NONE

SHT
14

OF
109

8

7

6

5

4

3

2

1

8

7
OMIT

6

5

4

3
OMIT

2

1

U1400
MCP79-TOPO-B
BGA (2 OF 11)
72D3 28A5 72D3 28A5 72D3 28B7 72D3 28A7

U1400
MCP79-TOPO-B
BGA (3 OF 11) AL10 AL11 AR8 AR9 AW7 AW8 AP13 AR13 AV25 AW25 AU30 AU29 AT35 AU35 AU39 AT39

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT OUT OUT

D

72D3 28A7 72D3 28A7 72D3 28B5 72D3 28B5 72D3 28B5 72D3 28B7 72D3 28B5 72D3 28B7 72D3 28B7 72D3 28B5 72D3 28B7 72D3 28B5 72D3 28B7 72D3 28B7 72D3 28B7 72D3 28B7 72D3 28B5 72D3 28B5 72D3 28B5 72D3 28B5 72D3 28B5 72D3 28B7 72D3 28C5 72D3 28B5 72D3 28B5 72D3 28B7

C

72D3 28B7 72D3 28C7 72D3 28C2 72D3 28C4 72D3 28C2 72D3 28C2 72D3 28C2 72D3 28C4 72D3 28C4 72D3 28C4 72D3 28B4 72D3 28B2 72D3 28C4 72D3 28C4 72D3 28B2 72D3 28C2 72D3 28C2 72D3 28B4 72D3 28C4 72D3 28C2 72D3 28C2 72D3 28C4 72D3 28C2 72D3 28C4 72D3 28C2 72D3 28C4 72D3 28C4

B

72D3 28C4 72D3 28D2 72D3 28D2 72D3 28C2 72D3 28C2 72D3 28D4 72D3 28D4

MEM_A_DQ<63> MEM_A_DQ<62> MEM_A_DQ<61> MEM_A_DQ<60> MEM_A_DQ<59> MEM_A_DQ<58> MEM_A_DQ<57> MEM_A_DQ<56> MEM_A_DQ<55> MEM_A_DQ<54> MEM_A_DQ<53> MEM_A_DQ<52> MEM_A_DQ<51> MEM_A_DQ<50> MEM_A_DQ<49> MEM_A_DQ<48> MEM_A_DQ<47> MEM_A_DQ<46> MEM_A_DQ<45> MEM_A_DQ<44> MEM_A_DQ<43> MEM_A_DQ<42> MEM_A_DQ<41> MEM_A_DQ<40> MEM_A_DQ<39> MEM_A_DQ<38> MEM_A_DQ<37> MEM_A_DQ<36> MEM_A_DQ<35> MEM_A_DQ<34> MEM_A_DQ<33> MEM_A_DQ<32> MEM_A_DQ<31> MEM_A_DQ<30> MEM_A_DQ<29> MEM_A_DQ<28> MEM_A_DQ<27> MEM_A_DQ<26> MEM_A_DQ<25> MEM_A_DQ<24> MEM_A_DQ<23> MEM_A_DQ<22> MEM_A_DQ<21> MEM_A_DQ<20> MEM_A_DQ<19> MEM_A_DQ<18> MEM_A_DQ<17> MEM_A_DQ<16> MEM_A_DQ<15> MEM_A_DQ<14> MEM_A_DQ<13> MEM_A_DQ<12> MEM_A_DQ<11> MEM_A_DQ<10> MEM_A_DQ<9> MEM_A_DQ<8> MEM_A_DQ<7> MEM_A_DQ<6> MEM_A_DQ<5> MEM_A_DQ<4> MEM_A_DQ<3> MEM_A_DQ<2> MEM_A_DQ<1> MEM_A_DQ<0> MEM_A_DM<7> MEM_A_DM<6> MEM_A_DM<5> MEM_A_DM<4> MEM_A_DM<3> MEM_A_DM<2> MEM_A_DM<1> MEM_A_DM<0>

AL8 AL9 AP9 AN9 AL6 AL7 AN6 AN7 AR6 AR7 AV6 AW5 AN10 AR5 AU6 AV5 AU7 AU8 AW9 AP11 AW6 AY5 AU9 AV9 AU11 AV11 AV13 AW13 AR11 AT11 AR14 AU13 AR26 AU25 AT27 AU27 AP25 AR25 AP27 AR27 AP29 AR29 AP31 AR31 AV27 AN29 AV29 AN31 AU31 AR33 AV37 AW37 AT31 AV31 AT37 AU37 AW39 AV39 AR37 AR38 AV38 AW38 AR35 AP35 AN5 AU5 AR10 AN13 AN27 AW29 AV35 AR34

MDQ0_63 MDQ0_62 MDQ0_61 MDQ0_60 MDQ0_59 MDQ0_58 MDQ0_57 MDQ0_56 MDQ0_55 MDQ0_54 MDQ0_53 MDQ0_52 MDQ0_51 MDQ0_50 MDQ0_49 MDQ0_48 MDQ0_47 MDQ0_46 MDQ0_45 MDQ0_44 MDQ0_43 MDQ0_42 MDQ0_41 MDQ0_40 MDQ0_39 MDQ0_38 MDQ0_37 MDQ0_36 MDQ0_35 MDQ0_34 MDQ0_33 MDQ0_32 MDQ0_31 MDQ0_30 MDQ0_29 MDQ0_28 MDQ0_27 MDQ0_26 MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22 MDQ0_21 MDQ0_20 MDQ0_19 MDQ0_18 MDQ0_17 MDQ0_16 MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12 MDQ0_11 MDQ0_10 MDQ0_9 MDQ0_8 MDQ0_7 MDQ0_6 MDQ0_5 MDQ0_4 MDQ0_3 MDQ0_2 MDQ0_1 MDQ0_0 MDQM0_7 MDQM0_6 MDQM0_5 MDQM0_4 MDQM0_3 MDQM0_2 MDQM0_1 MDQM0_0

MDQS0_7_P MDQS0_7_N MDQS0_6_P MDQS0_6_N MDQS0_5_P MDQS0_5_N MDQS0_4_P MDQS0_4_N MDQS0_3_P MDQS0_3_N MDQS0_2_P MDQS0_2_N MDQS0_1_P MDQS0_1_N MDQS0_0_P MDQS0_0_N

MEM_A_DQS_P<7> MEM_A_DQS_N<7> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<0> MEM_A_DQS_N<0>

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

28A5 72C3 28A5 72C3 28B7 72C3 28B7 72C3 28B5 72C3 28B5 72C3 28B7 72C3 28B7 72C3 28C4 72C3 28C4 72C3 28B2 72C3 28C2 72C3 28C4 72C3 28C4 72C3 28C2 72C3 28D2 72C3

72B3 29B5 72B3 29A5 72B3 29A7 72B3 29A7 72B3 29B5 72B3 29A7 72B3 29A5 72B3 29B7 72B3 29B7 72B3 29B7 72B3 29B7 72B3 29B5 72B3 29B5 72B3 29B5 72B3 29B7 72B3 29B5 72B3 29B7

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT OUT OUT

MEMORY PARTITION 0

72B3 29B7 72B3 29B5 72B3 29B5

BA8 BC8 BB4 BC4 BA7 AY8 BA9 BB10 BB12 AW12 BB8 BB9 AY12 BA12 BC32 AW32 BA35 AY36 BA32 BB32 BA34 AY35 BC36 AW36 BA39 AY40 BA36 BB36 BA38 AY39 BB40 AW40 AV42 AV41 BA40 BC40 AW42 AW41 AT40 AT41 AP41 AN40 AU40 AU41 AR41 AP42 AT5 BA2 AY7 BA11 BB34 BB38 AY43 AR42

MRAS0# MCAS0# MWE0#

AV17 AP17 AR17

MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L

MEMORY PARTITION 1

72B3 29B7

OUT OUT OUT

28C5 72D3 28C7 72D3 28C7 72D3

72B3 29B5 72B3 29B7 72B3 29B5 72B3 29B7 72B3 29B5 72B3 29C7 72B3 29C5 72B3 29B7

MBA0_2 MBA0_1 MBA0_0

AP23 AP19 AW17

MEM_A_BA<2> MEM_A_BA<1> MEM_A_BA<0>

OUT OUT OUT

28C7 72D3 28C5 72D3 28C7 72D3

72B3 29B5 72B3 29B5 72B3 29B7 72B3 29B4 72B3 29B2 72B3 29C2 72B3 29C4

MA0_14 MA0_13 MA0_12 MA0_11 MA0_10 MA0_9 MA0_8 MA0_7 MA0_6 MA0_5 MA0_4 MA0_3 MA0_2 MA0_1 MA0_0

AR23 AU15 AN23 AW21 AN19 AV21 AR22 AU21 AP21 AR21 AN21 AV19 AU19 AT19 AR19

MEM_A_A<14> MEM_A_A<13> MEM_A_A<12> MEM_A_A<11> MEM_A_A<10> MEM_A_A<9> MEM_A_A<8> MEM_A_A<7> MEM_A_A<6> MEM_A_A<5> MEM_A_A<4> MEM_A_A<3> MEM_A_A<2> MEM_A_A<1> MEM_A_A<0>

72B3 29B2

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

28C5 72D3 72B3 29B4 28C7 72D3 72B3 29C2 28C7 72D3 72B3 29C4 28C5 72D3 72B3 29C2 28C7 72D3 72B3 29C4 28C7 72D3 72B3 29C2 28C7 72D3 72B3 29C4 28C5 72D3 72B3 29C4 28C5 72D3 72B3 29C2 28C7 72D3 72B3 29C4 28C5 72D3 72B3 29C2 28C7 72D3 72B3 29C4 28C5 72D3 72B3 29C4 28C7 72D3 72B3 29C4 28C5 72D3 72B3 29C2 72B3 29C2

MEMORY CONTROL 0A
MCLK0A_2_P MCLK0A_2_N MCLK0A_1_P MCLK0A_1_N MCLK0A_0_P MCLK0A_0_N MCS0A_1# MCS0A_0# MODT0A_1 MODT0A_0 MCKE0A_1 MCKE0A_0
AW33 AV33 BA24 AY24 BB20 BC20

72B3 29C4 72B3 29C2 72B3 29C2

TP_MEM_A_CLK2P TP_MEM_A_CLK2N MEM_A_CLK_P<1> MEM_A_CLK_N<1> MEM_A_CLK_P<0> MEM_A_CLK_N<0> MEM_A_CS_L<1> MEM_A_CS_L<0> MEM_A_ODT<1> MEM_A_ODT<0> MEM_A_CKE<1> MEM_A_CKE<0>
OUT OUT OUT OUT
28C5 72D3 28C5 72D3

72B3 29C2 72B3 29C4 72B3 29D2 72B3 29D2 72B3 29C4 72B3 29C2 28C7 72D3 72B3 29D4 28C7 72D3 72B3 29D4

MEM_B_DQ<63> MEM_B_DQ<62> MEM_B_DQ<61> MEM_B_DQ<60> MEM_B_DQ<59> MEM_B_DQ<58> MEM_B_DQ<57> MEM_B_DQ<56> MEM_B_DQ<55> MEM_B_DQ<54> MEM_B_DQ<53> MEM_B_DQ<52> MEM_B_DQ<51> MEM_B_DQ<50> MEM_B_DQ<49> MEM_B_DQ<48> MEM_B_DQ<47> MEM_B_DQ<46> MEM_B_DQ<45> MEM_B_DQ<44> MEM_B_DQ<43> MEM_B_DQ<42> MEM_B_DQ<41> MEM_B_DQ<40> MEM_B_DQ<39> MEM_B_DQ<38> MEM_B_DQ<37> MEM_B_DQ<36> MEM_B_DQ<35> MEM_B_DQ<34> MEM_B_DQ<33> MEM_B_DQ<32> MEM_B_DQ<31> MEM_B_DQ<30> MEM_B_DQ<29> MEM_B_DQ<28> MEM_B_DQ<27> MEM_B_DQ<26> MEM_B_DQ<25> MEM_B_DQ<24> MEM_B_DQ<23> MEM_B_DQ<22> MEM_B_DQ<21> MEM_B_DQ<20> MEM_B_DQ<19> MEM_B_DQ<18> MEM_B_DQ<17> MEM_B_DQ<16> MEM_B_DQ<15> MEM_B_DQ<14> MEM_B_DQ<13> MEM_B_DQ<12> MEM_B_DQ<11> MEM_B_DQ<10> MEM_B_DQ<9> MEM_B_DQ<8> MEM_B_DQ<7> MEM_B_DQ<6> MEM_B_DQ<5> MEM_B_DQ<4> MEM_B_DQ<3> MEM_B_DQ<2> MEM_B_DQ<1> MEM_B_DQ<0> MEM_B_DM<7> MEM_B_DM<6> MEM_B_DM<5> MEM_B_DM<4> MEM_B_DM<3> MEM_B_DM<2> MEM_B_DM<1> MEM_B_DM<0>

AT4 AT3 AV2 AV3 AR4 AR3 AU2 AU3 AY4 AY3 BB3 BC3 AW4 AW3 BA3 BB2 BB5 BA5

MDQ1_63 MDQ1_62 MDQ1_61 MDQ1_60 MDQ1_59 MDQ1_58 MDQ1_57 MDQ1_56 MDQ1_55 MDQ1_54 MDQ1_53 MDQ1_52 MDQ1_51 MDQ1_50 MDQ1_49 MDQ1_48 MDQ1_47 MDQ1_46 MDQ1_45 MDQ1_44 MDQ1_43 MDQ1_42 MDQ1_41 MDQ1_40 MDQ1_39 MDQ1_38 MDQ1_37 MDQ1_36 MDQ1_35 MDQ1_34 MDQ1_33 MDQ1_32 MDQ1_31 MDQ1_30 MDQ1_29 MDQ1_28 MDQ1_27 MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23 MDQ1_22 MDQ1_21 MDQ1_20 MDQ1_19 MDQ1_18 MDQ1_17 MDQ1_16 MDQ1_15 MDQ1_14 MDQ1_13 MDQ1_12 MDQ1_11 MDQ1_10 MDQ1_9 MDQ1_8 MDQ1_7 MDQ1_6 MDQ1_5 MDQ1_4 MDQ1_3 MDQ1_2 MDQ1_1 MDQ1_0 MDQM1_7 MDQM1_6 MDQM1_5 MDQM1_4 MDQM1_3 MDQM1_2 MDQM1_1 MDQM1_0

MDQS1_7_P MDQS1_7_N MDQS1_6_P MDQS1_6_N MDQS1_5_P MDQS1_5_N MDQS1_4_P MDQS1_4_N MDQS1_3_P MDQS1_3_N MDQS1_2_P MDQS1_2_N MDQS1_1_P MDQS1_1_N MDQS1_0_P MDQS1_0_N

AT2 AT1 AY2 AY1 BB6 BA6 BA10 AY11 BB33 BA33 BB37 BA37 BA43 AY42 AT42 AT43

MEM_B_DQS_P<7> MEM_B_DQS_N<7> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<0> MEM_B_DQS_N<0>

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

29A5 72A3 29A5 72A3 29B7 72A3 29B7 72A3 29B5 72A3 29B5 72A3 29B7 72A3 29B7 72A3 29B2 72A3 29C2 72A3 29C4 72A3 29C4 72A3 29C4 72A3 29C4 72A3 29C2 72A3 29D2 72A3

D

MRAS1# MCAS1# MWE1#

AW16 BA15 BA16

MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L

OUT OUT OUT

29C5 72B3 29C7 72B3 29C7 72B3

MBA1_2 MBA1_1 MBA1_0

BB29 BB18 BB17

MEM_B_BA<2> MEM_B_BA<1> MEM_B_BA<0>

OUT OUT OUT

29C7 72B3 29C5 72B3 29C7 72B3

C

MA1_14 MA1_13 MA1_12 MA1_11 MA1_10 MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0

BA29 BA14 AW28 BC28 BA17 BB28 AY28 BA28 AY27 BA27 BA26 BB26 BA25 BB25 BA18

MEM_B_A<14> MEM_B_A<13> MEM_B_A<12> MEM_B_A<11> MEM_B_A<10> MEM_B_A<9> MEM_B_A<8> MEM_B_A<7> MEM_B_A<6> MEM_B_A<5> MEM_B_A<4> MEM_B_A<3> MEM_B_A<2> MEM_B_A<1> MEM_B_A<0>

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

29C5 72B3 29C7 72B3 29C7 72B3 29C5 72B3 29C7 72B3 29C7 72B3 29C7 72B3 29C5 72B3 29C5 72B3 29C7 72B3 29C5 72B3 29C7 72B3 29C5 72B3 29C7 72B3 29C5 72B3

MEMORY CONTROL 1A
MCLK1A_2_P MCLK1A_2_N MCLK1A_1_P MCLK1A_1_N MCLK1A_0_P MCLK1A_0_N MCS1A_1# MCS1A_0# MODT1A_1 MODT1A_0 MCKE1A_1 MCKE1A_0
BA42 BB42 BB22 BA22 BA19 AY19

TP_MEM_B_CLK2P TP_MEM_B_CLK2N MEM_B_CLK_P<1> MEM_B_CLK_N<1> MEM_B_CLK_P<0> MEM_B_CLK_N<0> MEM_B_CS_L<1> MEM_B_CS_L<0> MEM_B_ODT<1> MEM_B_ODT<0> MEM_B_CKE<1> MEM_B_CKE<0>
OUT OUT OUT OUT
29C5 72C3 29C5 72C3

B
29C7 72C3 29C7 72C3

72C3 28A7 72C3 28B5 72C3 28B7 72C3 28B5 72C3 28C2 72C3 28B4 72C3 28C2 72D3 28C4

AT15 AR18

OUT OUT

28C7 72D3 28C5 72D3

72B3 29A7 72B3 29B5 72B3 29B7

BB14 BB16

OUT OUT

29C7 72B3 29C5 72B3

AP15 AV15

OUT OUT

28C5 72D3 28C5 72D3

72B3 29B5 72B3 29B4 72B3 29C2

BB13 AY15

OUT OUT

29C5 72B3 29C5 72B3

AU23 AT23

OUT OUT

28D5 72D3 28D7 72D3

72B3 29C2 72B3 29C4

AY31 BB30

OUT OUT

29D5 72B3 29D7 72B3

MCP Memory Interface

A

SYNC_MASTER=T18_MLB

SYNC_DATE=04/04/2008

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
SCALE NONE

SHT
15

OF
109

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

OMIT

U1400
MCP79-TOPO-B
BGA (4 OF 11)

MEMORY CONTROL 0B

D

AU34 BB24 BC24 BA21 BB21

MEMORY CONTROL 1B

TP_MEM_A_CLK5P TP_MEM_A_CLK5N TP_MEM_A_CLK4P TP_MEM_A_CLK4N TP_MEM_A_CLK3P TP_MEM_A_CLK3N TP_MEM_A_CS_L<2> TP_MEM_A_CS_L<3> TP_MEM_A_ODT<2> TP_MEM_A_ODT<3> TP_MEM_A_CKE<2> TP_MEM_A_CKE<3> PP1V05_S0_MCP_PLL_CORE 17 12 19 39 mA mA mA mA

AU33

MCLK0B_2_P MCLK0B_2_N MCLK0B_1_P MCLK0B_1_N MCLK0B_0_P MCLK0B_0_N MCS0B_0# MCS0B_1# MODT0B_0 MODT0B_1 MCKE0B_0 MCKE0B_1

MCLK1B_2_P MCLK1B_2_N MCLK1B_1_P MCLK1B_1_N MCLK1B_0_P MCLK1B_0_N MCS1B_0# MCS1B_1# MODT1B_0 MODT1B_1 MCKE1B_0 MCKE1B_1

BA41 BB41 AY23 BA23 BA20 AY20

TP_MEM_B_CLK5P TP_MEM_B_CLK5N TP_MEM_B_CLK4P TP_MEM_B_CLK4N TP_MEM_B_CLK3P TP_MEM_B_CLK3N TP_MEM_B_CS_L<2> TP_MEM_B_CS_L<3> TP_MEM_B_ODT<2> TP_MEM_B_ODT<3> TP_MEM_B_CKE<2> TP_MEM_B_CKE<3>

D

AU17 AR15

BC16 BA13

AN17 AN15

AY16 BC13

AV23 AN25

BA30 BA31

24C8 16C3 8B7

=PP1V8R1V5_S0_MCP_MEM

24B2

87 mA (A01)

T27 U28 U27 T28

R1610 1
40.2
1% 1/16W MF-LF 402

+V_PLL_XREF_XS +V_PLL_DP +V_PLL_CORE +V_VPLL

MRESET0#

AY32

MCP_MEM_RESET_L TP or NC for DDR2.

OUT

30B6

2
72A3 72A3

MCP_MEM_COMP_VDD MCP_MEM_COMP_GND

AN41 AM41

MEM_COMP_VDD MEM_COMP_GND +VDD_MEM1 +VDD_MEM2 +VDD_MEM3 +VDD_MEM4 +VDD_MEM5 +VDD_MEM6 +VDD_MEM7 +VDD_MEM8 +VDD_MEM9 +VDD_MEM10 +VDD_MEM11 +VDD_MEM12 +VDD_MEM13 +VDD_MEM14 +VDD_MEM15 +VDD_MEM16 +VDD_MEM17 +VDD_MEM18 +VDD_MEM19 +VDD_MEM20 +VDD_MEM21 +VDD_MEM22 +VDD_MEM23 +VDD_MEM24 +VDD_MEM25 +VDD_MEM26 +VDD_MEM27 +VDD_MEM28 +VDD_MEM29 +VDD_MEM30 +VDD_MEM31 +VDD_MEM32 +VDD_MEM33 +VDD_MEM34 +VDD_MEM35 +VDD_MEM36 +VDD_MEM37 +VDD_MEM38 +VDD_MEM39 +VDD_MEM40 +VDD_MEM41 +VDD_MEM42 +VDD_MEM43 +VDD_MEM44 +VDD_MEM45 GND55 GND56 GND57 GND58 GND59 GND60 GND61 GND62 GND63 GND64
AM17 AM19 AM21 AM23 AM25 AM27 AM29 AN16 BC29 AN20 AN24 AT17 AP16 AN22 AP20 AP24 AV16 AR16 AR20 AR24 AW15 AP22 AP18 AU16 AN18 AU24 AT21 AY29 AV24 AU20 AU22 AW27 BC17 AV20 AY17 AY18 AM15 AU18 AY25 AY26 AW19 AW24 BC25 AL30 AM31

=PP1V8R1V5_S0_MCP_MEM 4771 mA (A01, DDR3)

8B7 16C7 24C8

R1611 1

C

40.2
1% 1/16W MF-LF 402

AA22 AP12
2

G30 P10 T10 T6 V10 V34 W5 AA39 AB22 AB7 AD22 AE20 AF24 AG24 AH35 AK7 AM28 AT25 AP30 AR36 AU10 F28 BC21 AY9

B

BC9 D34 F24 G32 H31 K7 M38 M5 M6 M7 M9 N39 N8 P33 P34 P37 P4 P40 P7 R36 R40 R43 R5 T18 T20 AK11

A

T24 T26

GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 GND49 GND50 GND51 GND52 GND53 GND54

C

B

T33 T34 T35 T37 T38 T7 T9 U18 U20 U22

MCP Memory Misc
SYNC_MASTER=T18_MLB SYNC_DATE=04/04/2008

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
SCALE NONE

SHT
16

OF
109

8

7

6

5

4

3

2

1

8

7

6

5
OMIT

4
U1400
MCP79-TOPO-B
BGA (5 OF 11)

3

2

1

9D6 9D6 9D6 9D6 9D6 9D6 9D6

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN

D

9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6

J6 J5 J4 L11 L10 L9 L8 L7 L6 N11 N10 N9 P9 N7 N6 N5 N4

PCI EXPRESS

=PEG_D2R_P<0> =PEG_D2R_N<0> =PEG_D2R_P<1> =PEG_D2R_N<1> =PEG_D2R_P<2> =PEG_D2R_N<2> =PEG_D2R_P<3> =PEG_D2R_N<3> =PEG_D2R_P<4> =PEG_D2R_N<4> =PEG_D2R_P<5> =PEG_D2R_N<5> =PEG_D2R_P<6> =PEG_D2R_N<6> =PEG_D2R_P<7> =PEG_D2R_N<7> =PEG_D2R_P<8> =PEG_D2R_N<8> =PEG_D2R_P<9> =PEG_D2R_N<9> =PEG_D2R_P<10> =PEG_D2R_N<10> =PEG_D2R_P<11> =PEG_D2R_N<11> =PEG_D2R_P<12> =PEG_D2R_N<12> =PEG_D2R_P<13> =PEG_D2R_N<13> =PEG_D2R_P<14> =PEG_D2R_N<14> =PEG_D2R_P<15> =PEG_D2R_N<15>

F7 E7 D7 C7 E6 F6 E5 F5 E4 E3 C3 D3 G5 H5 J7

PE0_RX0_P PE0_RX0_N PE0_RX1_P PE0_RX1_N PE0_RX2_P PE0_RX2_N PE0_RX3_P PE0_RX3_N PE0_RX4_P PE0_RX4_N PE0_RX5_P PE0_RX5_N PE0_RX6_P PE0_RX6_N PE0_RX7_P PE0_RX7_N PE0_RX8_P PE0_RX8_N PE0_RX9_P PE0_RX9_N PE0_RX10_P PE0_RX10_N PE0_RX11_P PE0_RX11_N PE0_RX12_P PE0_RX12_N PE0_RX13_P PE0_RX13_N PE0_RX14_P PE0_RX14_N PE0_RX15_P PE0_RX15_N

PE0_TX0_P PE0_TX0_N PE0_TX1_P PE0_TX1_N PE0_TX2_P PE0_TX2_N PE0_TX3_P PE0_TX3_N PE0_TX4_P PE0_TX4_N PE0_TX5_P PE0_TX5_N PE0_TX6_P PE0_TX6_N PE0_TX7_P PE0_TX7_N PE0_TX8_P PE0_TX8_N PE0_TX9_P PE0_TX9_N PE0_TX10_P PE0_TX10_N PE0_TX11_P PE0_TX11_N PE0_TX12_P PE0_TX12_N PE0_TX13_P PE0_TX13_N PE0_TX14_P PE0_TX14_N PE0_TX15_P PE0_TX15_N PE0_REFCLK_P PE0_REFCLK_N PE1_REFCLK_P PE1_REFCLK_N PE2_REFCLK_P PE2_REFCLK_N PE3_REFCLK_P PE3_REFCLK_N PE4_REFCLK_P PE4_REFCLK_N PE5_REFCLK_P PE5_REFCLK_N PE6_REFCLK_P PE6_REFCLK_N PEX_RST0# PE1_TX0_P PE1_TX0_N PE1_TX1_P PE1_TX1_N PE1_TX2_P PE1_TX2_N PE1_TX3_P PE1_TX3_N

C5 D4 C4 B4 A4 A3 B3 B2 C1 D1 D2 E1 E2 F2 F3 F4 G3 H4 H3 H2 H1 J1 J2 J3 K2 K3 L4 L3 M4 M3 M2 M1

=PEG_R2D_C_P<0> =PEG_R2D_C_N<0> =PEG_R2D_C_P<1> =PEG_R2D_C_N<1> =PEG_R2D_C_P<2> =PEG_R2D_C_N<2> =PEG_R2D_C_P<3> =PEG_R2D_C_N<3> =PEG_R2D_C_P<4> =PEG_R2D_C_N<4> =PEG_R2D_C_P<5> =PEG_R2D_C_N<5> =PEG_R2D_C_P<6> =PEG_R2D_C_N<6> =PEG_R2D_C_P<7> =PEG_R2D_C_N<7> =PEG_R2D_C_P<8> =PEG_R2D_C_N<8> =PEG_R2D_C_P<9> =PEG_R2D_C_N<9> =PEG_R2D_C_P<10> =PEG_R2D_C_N<10> =PEG_R2D_C_P<11> =PEG_R2D_C_N<11> =PEG_R2D_C_P<12> =PEG_R2D_C_N<12> =PEG_R2D_C_P<13> =PEG_R2D_C_N<13> =PEG_R2D_C_P<14> =PEG_R2D_C_N<14> =PEG_R2D_C_P<15> =PEG_R2D_C_N<15> PEG_CLK100M_P PEG_CLK100M_N PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N TP_PCIE_CLK100M_PE4P TP_PCIE_CLK100M_PE4N TP_PCIE_CLK100M_PE5P TP_PCIE_CLK100M_PE5N TP_PCIE_CLK100M_PE6P TP_PCIE_CLK100M_PE6N PCIE_RESET_L PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_EXCARD_R2D_C_P PCIE_EXCARD_R2D_C_N TP_PCIE_PE4_R2D_CP TP_PCIE_PE4_R2D_CN =PP1V05_S0_MCP_PEX_AVDD0

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6 9D6

D

C

E11 D11

9D6

IN

PEG_PRSNT_L MINI_CLKREQ_L PCIE_MINI_PRSNT_L FW_CLKREQ_L PCIE_FW_PRSNT_L EXCARD_CLKREQ_L PCIE_EXCARD_PRSNT_L TP_PE4_CLKREQ_L TP_PE4_PRSNT_L TP_MCP_GPIO_17 GMUX_JTAG_TCK_L TP_MCP_GPIO_18 GMUX_JTAG_TDO PCIE_WAKE_L PCIE_MINI_D2R_P PCIE_MINI_D2R_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N TP_PCIE_PE4_D2RP TP_PCIE_PE4_D2RN =PP1V05_S0_MCP_PEX_DVDD0 57 mA (A01, DVDD0 & 1)

C9

Int PU PE0_PRSNT_16#
PEB_CLKREQ#/GPIO_49

OUT OUT

9D6 9D6

C

31D7 31D7 9C6

IN IN

D5 D9

Int PU

G11 F11

OUT OUT

31C5 73D3 31C5 73D3

PEB_PRSNT# Int PU
PEC_CLKREQ#/GPIO_50

9D6 9D6

IN IN

E8 C10

Int PU

J11 J10

OUT OUT

9D6 9C6

PEC_PRSNT# Int PU
PED_CLKREQ#/GPIO_51

9C6 9C6

IN IN

M15 B10

Int PU

G13 F13

OUT OUT

9C6 9C6

PED_PRSNT# Int PU
PEE_CLKREQ#/GPIO_16 PEE_PRSNT#/GPIO_46 PEF_CLKREQ#/GPIO_17 PEF_PRSNT#/GPIO_47 PEG_CLKREQ#/GPIO_18 PEG_PRSNT#/GPIO_48

9C6 9C6

L16 L18

Int PU

J13 H13

9C6 9C6

M16 M18

Int PU

Int PU
L14 K14

9C4

OUT

M17 M19

Int PU

Int PU
N14 M14

9C4

IN

31C7 23C5 7D5

IN

F17

Int PU PE_WAKE# Int PU (S5) PE1_RX0_P PE1_RX0_N PE1_RX1_P PE1_RX1_N PE1_RX2_P PE1_RX2_N PE1_RX3_P PE1_RX3_N

K11

OUT

26C4

73D3 31C7 7D5 73D3 31C7 7D5

IN IN IN IN IN IN
9B6 9B6

K9 J9 H9 G9 F9 E9 H7 G7

D8 C8 B8 A8 A7 B7 B6 C6

OUT OUT OUT OUT OUT OUT
9B6 9B6

31C5 73D3 31C5 73D3

9D6

9D6 9D6

B

9D6

B

9C6 9C6

9C6 9C6

8A6

8A6

T17 W19 U17 V19 W16 W17 W18 U16

+DVDD0_PEX1 +DVDD0_PEX2 +DVDD0_PEX3 +DVDD0_PEX4 +DVDD0_PEX5 +DVDD0_PEX6 +DVDD0_PEX7 +DVDD0_PEX8 +DVDD1_PEX1 +DVDD1_PEX2

8A6

=PP1V05_S0_MCP_PEX_DVDD1
T19 U19

+AVDD0_PEX1 +AVDD0_PEX2 +AVDD0_PEX3 +AVDD0_PEX4 +AVDD0_PEX5 +AVDD0_PEX6 +AVDD0_PEX7 +AVDD0_PEX8 +AVDD0_PEX9 +AVDD0_PEX10 +AVDD0_PEX11 +AVDD0_PEX12 +AVDD0_PEX13 +AVDD1_PEX1 +AVDD1_PEX2 +AVDD1_PEX3

Y12 AA12 AB12 M12 P12 R12 N12 T12 U12 AC12 AD12 V12 W12

206 mA (A01, AVDD0 & 1)

24C2

PP1V05_S0_MCP_PLL_PEX 84 mA (A01)

T16

+V_PLL_PEX
M13 N13 P13

=PP1V05_S0_MCP_PEX_AVDD1

8A6

73C3

MCP_PEX_CLK_COMP

A11

PEX_CLK_COMP

MCP PCIe Interfaces
SYNC_MASTER=T18_MLB SYNC_DATE=04/04/2008

A

NO STUFF
1

R1710
2.37K
1% 1/16W MF-LF 402

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX. If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

2

PLACEMENT_NOTE=Place within 12.7mm of U1400

REV.
C

D
APPLE INC.
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
SCALE NONE

SHT
17

OF
109

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

OMIT

U1400
MCP79-TOPO-B
BGA (6 OF 11)

=PP3V3_ENET_MCP_RMGT
+3.3V_DUAL_RMGT1
J24 K24

8B1 18D7 24A5 24B6

83 mA (A01) =PP1V05_ENET_MCP_RMGT
8B1 24D6

D
75D3 33C1 75D3 33C1 75D3 33C1 75D3 33C1

LAN

+3.3V_DUAL_RMGT2

D
Network Interface Select
Interface ENET_TXD<0> 1 0

+V_DUAL_RMGT1 +V_DUAL_RMGT2 MII_VREF RGMII_TXD0 RGMII_TXD1 RGMII_TXD2 RGMII_TXD3
RGMII_TXC/MII_TXCLK RGMII_TXCTL/MII_TXEN

U23 V23

131 mA (A01)

IN IN IN IN IN IN IN IN IN

ENET_RXD<0> ENET_RXD<1> ENET_RXD<2> ENET_RXD<3> ENET_CLK125M_RXCLK ENET_RX_CTRL =MCP_MII_RXER =MCP_MII_COL =MCP_MII_CRS TP_ENET_INTR_L

C23 B23 E24 A24 A23 C22 F23 B26 B22 J22

RGMII_RXD0 RGMII_RXD1 RGMII_RXD2 RGMII_RXD3
RGMII_RXC/MII_RXCLK RGMII_RXCTL/MII_RXDV

E28 B24 C24 C25 D25 D24 C26 D21 C21 G23

MCP_MII_VREF ENET_TXD<0> ENET_TXD<1> ENET_TXD<2> ENET_TXD<3> ENET_CLK125M_TXCLK ENET_TX_CTRL ENET_MDC ENET_MDIO TP_ENET_PWRDWN_L MCP_CLK25M_BUF0_R ENET_RESET_L PP3V3_S0_MCP_DAC

IN OUT OUT OUT OUT OUT OUT OUT BI

24A4

33C6 75D3 33C6 75D3 33C6 75D3 33C6 75D3

RGMII MII

75D3 33C1 75D3 33B1

9C4

24B6 24A5 18D3 8B1

=PP3V3_ENET_MCP_RMGT

9C4 9C4

MII_RXER/GPIO_36 MII_COL/GPIO_20/MSMB_DATA MII_CRS/GPIO_21/MSMB_CLK
RGMII_INTR/GPIO_35

33C8 75D3 33B6 75C3

R1810 1
49.9
1% 1/16W MF-LF 402
24A6

RGMII_MDC RGMII_MDIO
RGMII_PWRDWN/GPIO_37

33B6 75D3 33B6 75D3

PP1V05_ENET_MCP_PLL_MAC 5 mA (A01)
T23

NOTE: All Apple products set strap to MII, RGMII products will enable feature via software. This avoids a leakage issue since MCP79 requires a S5 pull-up. =PP3V3_S0_MCP_GPIO
8C5 19D1 21A4

+V_DUAL_MACPLL BUF_25MHZ
E23

2

OUT

34A5 75D3

MCP_MII_COMP_VDD 75D3 MCP_MII_COMP_GND
75D3

C27 B27

MII_COMP_VDD MII_COMP_GND

MII_RESET#

J23

OUT
25D2

33B7 75C3

R1860 1
100K
5% 1/16W MF-LF 402

1

R1861
100K
5% 1/16W MF-LF 402

R1811
49.9
1% 1/16W MF-LF 402

1

2

TP_MCP_RGB_DAC_RSET TP_MCP_RGB_DAC_VREF

C39 B38

RGB_DAC_RSET RGB_DAC_VREF

+V_RGB_DAC +V_TV_DAC DDC_CLK0 DDC_DATA0 RGB_DAC_RED RGB_DAC_GREEN RGB_DAC_BLUE

J32 K32

103 mA 103 mA MCP_DDC_CLK0 MCP_DDC_DATA0 TP_MCP_RGB_RED TP_MCP_RGB_GREEN TP_MCP_RGB_BLUE TP_MCP_RGB_HSYNC TP_MCP_RGB_VSYNC CRT_IG_R_C_PR CRT_IG_G_Y_Y CRT_IG_B_COMP_PB CRT_IG_HSYNC CRT_IG_VSYNC LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_N<0> LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_P<2> LVDS_IG_A_DATA_N<2> LVDS_IG_A_DATA_P<3> LVDS_IG_A_DATA_N<3>

206 mA (A01)

2

2

B31 A31

DACS

C
9D4 9D4

B39 A39 B40 A40 A41

RGB DAC Disable: Okay to float all RGB_DAC signals. DDC_CLK0/DDC_DATA0 pull-ups still required.

C

OUT OUT

MCP_TV_DAC_RSET MCP_TV_DAC_VREF

E36 A35

TV_DAC_RSET TV_DAC_VREF

20C1 8A3

=PP3V3_S5_MCP_GPIO

R1820
47K
5% 1/16W MF-LF 402
41C3

1

9D4 9D4

IN OUT

MCP_CLK27M_XTALIN MCP_CLK27M_XTALOUT

C38 D38

XTALIN_TV XTALOUT_TV

TV C Y Comp

/ / / /

RGB_DAC_HSYNC RGB_DAC_VSYNC Component Pr TV_DAC_RED Y TV_DAC_GREEN Pb TV_DAC_BLUE

RGB ONLY

A36 B36 C36 D36 C37

TV DAC Disable:
OUT OUT OUT OUT OUT
9D4 9D4 9D4

TV_DAC_HSYNC/GPIO_44 TV_DAC_VSYNC/GPIO_45
2

Okay to float all TV_DAC signals. Okay to float XTALIN_TV and XTALOUT_TV. DDC_CLK0/DDC_DATA0 pull-ups still required.

9D4 9D4

BI
67A5

IN

LPCPLUS_GPIO DP_IG_CA_DET LVDS_IG_BKL_PWM LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR =MCP_HDMI_TXC_P =MCP_HDMI_TXC_N =MCP_HDMI_TXD_P<0> =MCP_HDMI_TXD_N<0> =MCP_HDMI_TXD_P<1> =MCP_HDMI_TXD_N<1> =MCP_HDMI_TXD_P<2> =MCP_HDMI_TXD_N<2> DP_IG_AUX_CH_P DP_IG_AUX_CH_N =DVI_HPD_GMUX_INT =MCP_HDMI_HPD (See below) (See below)

E16 B15

GPIO_6/FERR*/IGPU_GPIO_6 GPIO_7/NFERR*/IGPU_GPIO_7

IFPA_TXC_P IFPA_TXC_N IFPA_TXD0_P IFPA_TXD0_N IFPA_TXD1_P IFPA_TXD1_N IFPA_TXD2_P IFPA_TXD2_N IFPA_TXD3_P IFPA_TXD3_N

B35 C35 B32 A32 D32 C32 D33 C33 B34 C34

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

66B3 73B3 66B3 73B3

70B7 69A8

OUT OUT OUT

G39 E37 F40

Interface Mode MCP Signal =MCP_HDMI_TXC_P/N =MCP_HDMI_TXD_P/N<0> =MCP_HDMI_TXD_P/N<1> =MCP_HDMI_TXD_P/N<2> =MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA =MCP_HDMI_HPD DP_IG_AUX_CH_P/N TMDS/HDMI TMDS_IG_TXC_P/N TMDS_IG_TXD_P/N<0> TMDS_IG_TXD_P/N<1> TMDS_IG_TXD_P/N<2> TMDS_IG_DDC_CLK TMDS_IG_DDC_DATA TMDS_IG_HPD TP_DP_IG_AUX_CHP/N DisplayPort DP_IG_ML_P/N<3> DP_IG_ML_P/N<2> DP_IG_ML_P/N<1> DP_IG_ML_P/N<0> DP_IG_DDC_CLK DP_IG_DDC_DATA DP_IG_HPD DP_IG_AUX_CH_P/N

70C8 70B7 66B8

FLAT PANEL

LCD_BKL_CTL/GPIO_57 LCD_BKL_ON/GPIO_59 LCD_PANEL_PWR/GPIO_58 HDMI_TXC_P/ML0_LANE3_P HDMI_TXC_N/ML0_LANE3_N HDMI_TXD0_P/ML0_LANE2_P HDMI_TXD0_N/ML0_LANE2_N HDMI_TXD1_P/ML0_LANE1_P HDMI_TXD1_N/ML0_LANE1_N HDMI_TXD2_P/ML0_LANE0_P HDMI_TXD2_N/ML0_LANE0_N DP_AUX_CH0_P DP_AUX_CH0_N HPLUG_DET2/GPIO_22 HPLUG_DET3

7C7 66C2 73B3 7C7 66C2 73B3 7C7 66C2 73B3 7C7 66C2 73B3 7C7 66C2 73B3 7C7 66C2 73B3 9D4 9D4

67D3 67D3

OUT OUT OUT OUT OUT OUT OUT OUT

D35 E35 G35 F35 F33 G33 J33 H33

67D3 67D3 67D3 67D3 67D3 67D3

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases IFPB_TXC_P IFPB_TXC_N IFPB_TXD4_P IFPB_TXD4_N IFPB_TXD5_P IFPB_TXD5_N IFPB_TXD6_P IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N
L31 K31 J29 H29 L29 K29 L30 K30 N30 M30

B

LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N LVDS_IG_B_DATA_P<0> LVDS_IG_B_DATA_N<0> LVDS_IG_B_DATA_P<1> LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_P<2> LVDS_IG_B_DATA_N<2> LVDS_IG_B_DATA_P<3> LVDS_IG_B_DATA_N<3>

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

9D4 9D4

B

9C4 9C4 9C4 9C4 9C4 9C4 9C4 9C4

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used. NOTE: 20K pull-down required on DP_HPD_DET. NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used. NOTE: HDMI port requires level-shifting. IFP interface can be used to provide HDMI or dual-channel TMDS without level-shifters. LVDS: Power +VDD_IFPx at 1.8V Dual-channel TMDS: Power +VDD_IFPx at 3.3V

73B3 67C7 73B3 67C7

OUT OUT

D43 C43

9B4 67D3

IN IN

C31 F31

25D7 8A7

=PP3V3R1V8_S0_MCP_IFP_VDD 190 mA (A01, 1.8V)
M27 M26

25C5

PP3V3_S0_MCP_VPLL 16 mA (A01) 8 mA 8 mA
M28 M29 T25

+VDD_IFPA +VDD_IFPB +V_PLL_IFPAB +V_PLL_HDMI +VDD_HDMI HDMI_RSET HDMI_VPROBE

DDC_CLK2/GPIO_23 DDC_DATA2/GPIO_24 DDC_CLK3 DDC_DATA3 IFPAB_RSET IFPAB_VPROBE

C30 B30

LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA =MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA MCP_IFPAB_RSET MCP_IFPAB_VPROBE
1

OUT BI

7C7 66C5 7C7 66C5

D31 E31

OUT BI

67D3 67D3

25D7 8B7

=PP1V05_S0_MCP_HDMI_VDD

73B3 25C7 73B3 25C7

95 mA (A01) MCP_HDMI_RSET OUT MCP_HDMI_VPROBE OUT

J31 J30

E32 G31

OUT OUT

25C6 73B3 25C6 73B3

R1850
10K
5% 1/16W MF-LF 402

GPIOs 57-59 (if LCD panel is used): In MCP79 these pins have undocumented internal pull-ups (~10K to 3.3V S0). To ensure pins are low by default, pull-downs (1K or stronger) must be used.
2

MCP Ethernet & Graphics
SYNC_MASTER=T18_MLB SYNC_DATE=04/04/2008

A

NOTICE OF PROPRIETARY PROPERTY
=DVI_HPD_GMUX_INT: Alias to DVI_HPD for systems using IFP for DVI. Alias to GMUX_INT for systems with GMUX. Alias to HPLUG_DET2 for other systems. Pull-down (20k) required in all cases.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
SCALE NONE

SHT
18

OF
109

8

7

6

5

4

3

2

1

8

7

6
OMIT

5

4

3

2

1
=PP3V3_S0_MCP_GPIO
2 5% 1/16W MF-LF 402

U1400
MCP79-TOPO-B
BGA (7 OF 11)
74D3 19D2 74D3 19D2 19D2 52C7 19D2 19D4

21A4 18C1 8C5

MCP_RS232_SOUT_L PCI_REQ0_L PCI_REQ1_L CRTMUX_SEL_TV_L MCP_RS232_SIN_L

R1989 R1990 R1991 R1992 R1994

8.2K 8.2K 8.2K 8.2K 8.2K

1

OUT OUT IN

PCI_REQ0_L PCI_REQ1_L CRTMUX_SEL_TV_L AUD_IPHS_SWITCH_EN MCP_RS232_SIN_L MCP_DEBUG<0> MCP_DEBUG<1> MCP_DEBUG<2> MCP_DEBUG<3> MCP_DEBUG<4> MCP_DEBUG<5> MCP_DEBUG<6> MCP_DEBUG<7> TP_PCI_AD<8> TP_PCI_AD<9> TP_PCI_AD<10> TP_PCI_AD<11> TP_PCI_AD<12> TP_PCI_AD<13> TP_PCI_AD<14> TP_PCI_AD<15> TP_PCI_AD<16> TP_PCI_AD<17> TP_PCI_AD<18> TP_PCI_AD<19> TP_PCI_AD<20> TP_PCI_AD<21> TP_PCI_AD<22> TP_PCI_AD<23> TP_PCI_AD<24> TP_PCI_AD<25> TP_PCI_AD<26> TP_PCI_AD<27> TP_PCI_AD<28> TP_PCI_AD<29> TP_PCI_AD<30> TP_PCI_AD<31> TP_PCI_INTW_L TP_PCI_INTX_L TP_PCI_INTY_L TP_PCI_INTZ_L TP_PCI_TRDY_L

T2 V9 T3 U9 T4

PCI_REQ0# PCI_REQ1#/FANRPM2 PCI_REQ2#/GPIO_40/RS232_DSR# PCI_REQ3#/GPIO_38/RS232_CTS# PCI_REQ4#/GPIO_52/RS232_SIN# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_INTW# PCI_INTX# PCI_INTY# PCI_INTZ# PCI_TRDY# PCI_CLKRUN#/GPIO_42 LPC_DRQ1#/GPIO_19 Int PU Int PU LPC_DRQ0# LPC_SERIRQ Int PU

PCI_GNT0# PCI_GNT1#/FANCTL2 PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS# PCI_GNT4#/GPIO_53/RS232_SOUT# PCI_CBE0# PCI_CBE1# PCI_CBE2# PCI_CBE3# PCI_DEVSEL# PCI_FRAME# PCI_IRDY# PCI_PAR PCI_PERR#/GPIO_43/RS232_DCD# PCI_SERR# PCI_STOP#

R3 U10 R4 U11 P3

TP_PCI_GNT0_L TP_PCI_GNT1_L GMUX_JTAG_TMS GMUX_JTAG_TDI MCP_RS232_SOUT_L TP_PCI_C_BE_L<0> TP_PCI_C_BE_L<1> TP_PCI_C_BE_L<2> TP_PCI_C_BE_L<3> TP_PCI_DEVSEL_L TP_PCI_FRAME_L TP_PCI_IRDY_L TP_PCI_PAR TP_PCI_PERR_L TP_PCI_SERR_L TP_PCI_STOP_L PM_LATRIGGER_L

74D3 19D7 74D3 19D7

1 1 1 1

2 2 2 2 5% 5% 5% 5% 1/16W 1/16W 1/16W 1/16W MF-LF MF-LF MF-LF MF-LF 402 402 402 402

OUT OUT OUT

9C4 19D7 9C4 19D7 19D2

D

74D3 13C3 74D3 13C3 74D3 13C3 74D3 13C3 74D3 13C3 74D3 13C3 74D3 13C3 74D3 13C3

BI BI BI BI BI BI BI BI

AC3 AE10 AC4 AE11 AB3 AC6 AB2 AC7 AC8 AA2 AC9 AC10 AC11 AA1 AA5 Y5 W3 W6 W4 W7 V3 W8 V2 W9 U3 W11 U2 U5 U1 U6 T5 U7

AA3 AA6 AA11 W10

D

AA9 Y4 AA10 Y1 AB9 AA7 Y2 T1

PCI

PCI_PME#/GPIO_30 Int PU (S5)

OUT

13C6 23C5

PCI_RESET0# PCI_RESET1#

R10 R11

MEM_VTT_EN_R TP_PCI_RESET1_L

OUT

26C4

PCI_CLK0 PCI_CLK1 PCI_CLK2

R6 R7 R8
74C3

TP_PCI_CLK0 TP_PCI_CLK1 PCI_CLK33M_MCP_R
1

R1910
22
5% 1/16W MF-LF 402

C

C

2

PCI_CLKIN

R9

74C3

PCI_CLK33M_MCP

PLACEMENT_NOTE=Place close to pin R8

P2 N3 N2 N1

LPC_FRAME# LPC_PWRDWN#/GPIO_54/EXT_NMI#

AD4 AE12 AE5

41C1

LPC_FRAME_R_L LPC_PWRDWN_L LPC_RESET_L LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3> LPC_CLK33M_SMC_R

R1960

22

1

2 5% 1/16W MF-LF 402

LPC_FRAME_L

OUT OUT OUT

39C8 41D5 74C3 39C5 41D3

Y3

LPC

LPC_RESET0# LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_CLK0

26D4 74C3

AD3 AD2 AD1 AD5

41D5 39C5

IN

PM_CLKRUN_L FW_PME_L TP_LPC_DRQ0_L LPC_SERIRQ

AD11

9C4

IN

AE2 AE1 AE6

R1950 R1951 R1952 R1953

22 22 22 22

1 1 1 1

2 2 2 2 5% 5% 5% 5% 1/16W 1/16W 1/16W 1/16W MF-LF MF-LF MF-LF MF-LF 402 402 402 402

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3>

BI BI BI BI

39C8 41D5 74C3 39C8 41D5 74C3 39C8 41D3 74C3 39C8 41D3 74C3

41D3 39C8

BI

AE9

OUT

26C4 74C3

1

U24 U26 U39 U4 U8

B

V16 V17 V18 V20 V22 V24 V26 V27 V28 V33 V37 V4 V40 V7 W20 W22 W24 W36 W40 W43 Y16 Y17 Y18 Y19 Y20 Y22

A

Y24 Y25

GND65 GND66 GND67 GND68 GND69 GND70 GND71 GND72 GND73 GND74 GND75 GND76 GND77 GND78 GND79 GND80 GND81 GND82 GND83 GND84 GND85 GND86 GND87 GND88 GND89 GND90 GND91 GND92 GND93 GND94 GND95 GND96 GND97

GND98 GND99 GND100 GND101 GND102 GND103 GND104 GND105 GND106 GND107 GND108 GND109 GND110 GND111 GND112 GND113 GND114 GND115 GND116 GND117 GND118 GND119 GND120 GND121 GND122 GND123 GND124 GND125 GND126 GND127 GND128 GND129 GND130

Y26 Y27 AB18 H34 AB20 AB21 AB23 AB24 AB25 AB26 AB27 AB28 AB34 AB37 AB4 AB40 AC22 AC36 AC40 AB33 AC5 AD16 AD17 AD18 AD19 AD20 AD24 AD25 AD26 AD27 AD28 AD33 AD34
2

R1961
10K
5% 1/16W MF-LF 402

Strap for Boot ROM Selection (See HDA_SDOUT)

B

GND

MCP PCI & LPC
SYNC_MASTER=T18_MLB SYNC_DATE=04/04/2008

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
SCALE NONE

SHT
19

OF
109

8

7

6

5

4

3

2

1

8

7

6

5
OMIT

4
U1400
MCP79-TOPO-B
BGA (8 OF 11)

3

2

1

73A3 36A3 73A3 36A3

OUT OUT

SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_D2R_N SATA_HDD_D2R_P

AJ7 AJ6

SATA_A0_TX_P SATA_A0_TX_N SATA_A0_RX_N SATA_A0_RX_P

USB0_P USB0_N USB1_P USB1_N USB2_P USB2_N

C29 D29

External A USB_EXTA_P USB_EXTA_N AirPort (PCIe Mini-Card) USB_MINI_P USB_MINI_N External D USB_EXTD_P USB_EXTD_N Camera USB_CAMERA_P USB_CAMERA_N IR USB_IR_P USB_IR_N Geyser Trackpad/Keyboard USB_TPAD_P USB_TPAD_N Bluetooth USB_BT_P USB_BT_N External B USB_EXTB_P USB_EXTB_N ExpressCard USB_EXCARD_P USB_EXCARD_N External C USB_EXTC_P USB_EXTC_N TP_USB_10P TP_USB_10N TP_USB_11P TP_USB_11N

BI BI

37A8 74C3 37A8 74C3

73A3 36A3 73A3 36A3

IN IN

AJ5 AJ4

C28 D28

BI BI

9B6 9B6

D
73A3 36C2 73A3 36C2

A28 B28

BI BI

9B6 9B6

D

OUT OUT

SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_D2R_N SATA_ODD_D2R_P

AJ11 AJ10

SATA_A1_TX_P SATA_A1_TX_N SATA_A1_RX_N SATA_A1_RX_P

USB3_P USB3_N USB4_P USB4_N USB5_P USB5_N USB6_P USB6_N

F29 G29

BI BI

31B5 74C3 31B5 74C3

73A3 36B2 73A3 36B2

IN IN

AJ9 AK9

K27 L27

BI BI

38C7 74B3 38C7 74B3

J26 J27

BI BI

47B8 74B3 47B8 74B3

TP_SATA_C_R2D_CP TP_SATA_C_R2D_CN TP_SATA_C_D2RN TP_SATA_C_D2RP

AK2 AJ3

SATA_B0_TX_P SATA_B0_TX_N SATA_B0_RX_N SATA_B0_RX_P

F27 G27

BI BI

31B5 74C3 31B5 74C3

AJ2 AJ1

SATA USB

USB7_P USB7_N USB8_P USB8_N USB9_P USB9_N USB10_P USB10_N

D27 E27

BI BI

37A4 74B3 37B4 74B3

TP_SATA_D_R2D_CP TP_SATA_D_R2D_CN TP_SATA_D_D2RN TP_SATA_D_D2RP

AM4 AL3

SATA_B1_TX_P SATA_B1_TX_N SATA_B1_RX_N SATA_B1_RX_P

K25 L25

BI BI

9B6 9B6

=PP3V3_S5_MCP_GPIO

8A3 18C7

AL4 AK3

H25 J25

BI BI

9B6 9B6

1

R2051
8.2K
5% 1/16W MF-LF 402

1

R2053
8.2K
5% 1/16W MF-LF 402

F25 G25

2

2

C

TP_SATA_E_R2D_CP TP_SATA_E_R2D_CN TP_SATA_E_D2RN TP_SATA_E_D2RP

AN1 AM1

SATA_C0_TX_P SATA_C0_TX_N SATA_C0_RX_N SATA_C0_RX_P

USB11_P USB11_N

K23 L23

R2050
8.2K
5% 1/16W MF-LF 402

1

R2052
8.2K
5% 1/16W MF-LF 402

1

C
USB_EXTA_OC_L USB_EXTB_OC_L USB_EXTC_OC_L EXCARD_OC_L
IN IN IN IN
40C4 37C7 37C7

AM2 AM3

2

2

TP_SATA_F_R2D_CP TP_SATA_F_R2D_CN TP_SATA_F_D2RN TP_SATA_F_D2RP

AP3 AP2

SATA_C1_TX_P SATA_C1_TX_N SATA_C1_RX_N SATA_C1_RX_P

USB_OC0#/GPIO_25 USB_OC1#/GPIO_26 USB_OC2#/GPIO_27/MGPIO USB_OC3#/GPIO_28/MGPIO

L21 K21 J21 H21

AN3 AN2

+V_PLL_USB

L28

PP3V3_S0_MCP_PLL_USB 19 mA (A01)

24B4

USB_RBIAS_GND

A27

74B3

MCP_USB_RBIAS_GND

R2060 1
TP_MCP_SATALED_L
E12

SATA_LED#

24B2

PP1V05_S0_MCP_PLL_SATA

AE16

+V_PLL_SATA

84 mA (A01) 8A6 =PP1V05_S0_MCP_SATA_DVDD0 43 mA (A01, DVDD0 & 1)
AF19 AG16 AG17 AG19
8A6

+DVDD0_SATA1 +DVDD0_SATA2 +DVDD0_SATA3 +DVDD0_SATA4 +DVDD1_SATA1 +DVDD1_SATA2

=PP1V05_S0_MCP_SATA_DVDD1
AH17 AH19

B
8A6

=PP1V05_S0_MCP_SATA_AVDD0 127 mA (A01, AVDD0 & 1)
AJ12 AN11 AK12 AK13 AL12 AM11 AM12 AN12 AL13

+AVDD0_SATA1 +AVDD0_SATA2 +AVDD0_SATA3 +AVDD0_SATA4 +AVDD0_SATA5 +AVDD0_SATA6 +AVDD0_SATA7 +AVDD0_SATA8 +AVDD0_SATA9 +AVDD1_SATA1 +AVDD1_SATA2 +AVDD1_SATA3 +AVDD1_SATA4 SATA_TERMP

8A6

=PP1V05_S0_MCP_SATA_AVDD1
AN14 AL14 AM13 AM14

73A3

MCP_SATA_TERMP

AE3

GND131 GND132 GND133 GND134 GND135 GND136 GND137 GND138 GND139 GND140 GND141 GND142 GND143 GND144 GND145 GND146 GND147 GND148 GND149 GND150 GND151 GND152 GND153 GND154 GND155 GND156 GND157 GND158 GND159 GND160

AD35 AD37 AD38 AE22 AE24 AE39 AE4 AD6 AF16 AF17 AF18 AF20 AF22 AF26 AF27 AF28 AF33 AF34 AF37 AF40 AG18 AG20 AG22 AG26 AG36 AG40 AH18 AH20 AH22 AH24

806
1% 1/16W MF-LF 402

2

B

1

R2010
2.49K
1% 1/16W MF-LF 402

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA. If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

2

MCP SATA & USB
SYNC_MASTER=T18_MLB SYNC_DATE=04/04/2008

A

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
SCALE NONE

SHT
20

OF
109

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

OMIT

U1400
MCP79-TOPO-B
BGA (9 OF 11)

=PP3V3R1V5_S0_MCP_HDA

8B5 21D8 24A8

7 mA (A01) +V_DUAL_HDA1 +V_DUAL_HDA2
J16 K16
1

R2160
8.2K
5% 1/16W MF-LF 402

D
74A3 51C7

HDA

2

R2170
HDA_SDOUT_R
1

D
HDA_SDOUT
OUT
51C7 74A3

IN

HDA_SDIN0

G15

HDA_SDATA_IN0 Int PD

HDA_SDATA_OUT

F15

22
5% 1/16W MF-LF 402

74A3 21A7

2

R2171
HDA_BITCLK
E15
74B3 21A7

BIOS Boot Select
HDA_BIT_CLK
OUT
51D7 74B3

TP_MLB_RAM_SIZE

J14

HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK Int PD

HDA_BIT_CLK_R

22
1 5% 1/16W MF-LF 402 2

I/F LPC

HDA_SDOUT 0 0 1 1

LPC_FRAME# 0 1 0 1

R2172
22
1 5% 1/16W MF-LF 402 2

24A8 21D3 8B5

=PP3V3R1V5_S0_MCP_HDA
1

TP_MLB_RAM_VENDOR (MXM_OK for MXM systems)

J15

HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA Int PD

HDA_RESET*

K15

74A3 21A7

HDA_RST_R_L

HDA_RST_L

OUT

51C7 74A3

PCI SPI0

R2110
49.9
1% 1/16W MF-LF 402
74A3

R2173
HDA_SYNC
L15
74B3 21A7

HDA_SYNC_R

1

22
5% 1/16W MF-LF 402

2

HDA_SYNC

OUT

51C7 74B3

SPI1
21A4

2

MCP_HDA_PULLDN_COMP PP1V05_S0_MCP_PLL_NV

A15

HDA_PULLDN_COMP

HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA SLP_S3* SLP_RMGT* SLP_S5*

K17 L17

MCP_GPIO_4 AUD_I2C_INT_L PM_SLP_S3_L PM_SLP_RMGT_L PM_SLP_S4_L

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L
IN
21A4 52C7

24A2

37 mA (A01)

20 mA 17 mA

AE18 AE17

+V_PLL_NV_H +V_PLL_SP_SPREF

G17 J17 H17

OUT OUT OUT

7C3 34B7 39C5 41A5 64D5 68D8 9D1 7C3 39C5 40A2 64C8

R1961 and R2160 selects SPI0 ROM by default, LPC+ debug card pulls LPC_FRAME# high for SPI1 ROM override. NOTE: MCP79 does not support FWH, only LPC ROMs. So Apple designs will not use LPC for BootROM override. NOTE: MCP79 rev A01 does not support SPI1 option. Rev B01 will.

26D4 22A5 7C3

PP3V3_G3_RTC
41B1 40B2 39D5 34B7

OUT IN

=SPI_CS1_R_L_USE_MLB SMC_ADAPTER_EN TP_SB_A20GATE TP_MCP_KBDRSTIN_L SMC_WAKE_SCI_L SMC_RUNTIME_SCI_L SM_INTRUDER_L

L24 L26

GPIO_1/PWRDN_OK/SPI_CS1
GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L

THERM_DIODE_P THERM_DIODE_N

B11 C11

MCP_THMDIODE_P MCP_THMDIODE_N

OUT OUT

45C5 77D3 45C5 77D3

R2120 1

1

=PP3V3_S0_MCP BOOT_MODE_SAFE
1

8C5 22B3 24B8

R2121
49.9K
1% 1/16W MF-LF 402
39C5 23C5 39B8 23C5

K13 L13 C19 C18

C

49.9K
1% 1/16W MF-LF 402

IN IN

2

2

Int PU A20GATE KBRDRSTIN* Int PU SIO_PME* Int PU (S5) EXT_SMI/GPIO_32* Int PU (S5) INTRUDER* LID* Int PU (S5) LLB* Int PU (S5)

MCP_VID0/GPIO_13 MCP_VID1/GPIO_14 MCP_VID2/GPIO_15

L20 M20 M21

MCP_VID<0> MCP_VID<1> MCP_VID<2>

OUT OUT OUT

21A3 61B8 21A3 61A8 21A3 61A8

R2180
10K
5% 1/16W MF-LF 402

BUF_SIO_CLK Frequency
Frequency HDA_SYNC 1 0

C

2

B20

SPKR

C13

MCP_SPKR
1

OUT

23B5

23C5 39B8 23C5

IN

TP_MCP_LID_L PM_BATLOW_L PM_DPRSLPVR PM_PWRBTN_L PM_SYSRST_DEBOUNCE_L RTC_RST_L

M25 M24

BOOT_MODE_USER SMB_CLK0 SMB_DATA0 SMB_CLK1/MSMB_CLK SMB_DATA1/MSMB_DATA SMB_ALERT*/GPIO_64
L19 K19 G21 F21 M23

24 MHz 14.31818 MHz

71B3 60D8

IN

M22

CPU_DPRSLPVR PWRBTN* Int PU (S5) RSTBTN* Int PU RTC_RST* PWRGD_SB PS_PWRGD CPU_VLD JTAG_TDI Int PU JTAG_TDO JTAG_TMS Int PU JTAG_TRST* JTAG_TCK XTALIN XTALOUT XTALIN_RTC XTALOUT_RTC

MISC

39C8 23C5 26A1 23C5

IN IN

C16 D16

SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA AP_PWR_EN

OUT BI OUT BI OUT

13B6 42D8 74B3 13B6 42D8 74B3 42C8 74B3 42C8 74B3 21A3 31D5 34C7

R2181
10K
5% 1/16W MF-LF 402

2

USER mode: Normal SAFE mode: For ROMSIP recovery Connects to SMC for automatic recovery.

SPI Frequency Select
Frequency 31 MHz 42 MHz SPI_DO 0 0 1 1 SPI_CLK 0 1 0 1

C20

(MGPIO2) (MGPIO3)

39D8 26A5

IN IN

PM_RSMRST_L MCP_PS_PWRGD MCP_CPU_VLD JTAG_MCP_TDI JTAG_MCP_TDO JTAG_MCP_TMS JTAG_MCP_TRST_L JTAG_MCP_TCK MCP_CLK25M_XTALIN MCP_CLK25M_XTALOUT RTC_CLK32K_XTALIN RTC_CLK32K_XTALOUT

D20 E20

FANRPM0/GPIO_60 FANCTL0/GPIO_61 FANRPM1/GPIO_63 FANCTL1/GPIO_62

B12 A12 D12 C12

MEM_EVENT_L ODD_PWR_EN_L SMC_IG_THROTTLE_L ARB_DETECT

IN OUT IN
21A4

21A4 28A5 29A5 39B8 36C6 21A4 40D4

26A5

IN

C17

CPUVDD_EN

D17

MCP_CPUVDD_EN

OUT

26A8

25 MHz 1 MHz

23C5 13C3 6C5 6C4 23C5 13C3 6C5 13C3 6C5 13B6 6C5

IN OUT IN IN IN

E19 F19 J19 J18 G19

SPI_CS0/GPIO_10 SPI_CLK/GPIO_11 SPI_DI/GPIO_8 SPI_DO/GPIO_9

C14 D13 C15 B14

SPI_CS0_R_L SPI_CLK_R SPI_MISO SPI_MOSI_R

OUT OUT IN OUT

41B7 74A3 41A5 41C8 74A3 41A5 41B7 74A3 41A5 41C7 74A3

NOTE: Straps not provided on this page.

B
26B7 26C7

IN OUT

A16 B16

SUS_CLK/GPIO_34 BUF_SIO_CLK TEST_MODE_EN PKG_TEST

B18 AE7

PM_CLK32K_SUSCLK_R TP_MCP_BUF_SIO_CLK MCP_TEST_MODE_EN
1

B
OUT
26B4 74A3

26C7 26C7

IN OUT

A19 B19

K22 L22

R2163
10K
5% 1/16W MF-LF 402

1

R2190
1K
1% 1/16W MF-LF 402

R2150 1
10K
5% 1/16W MF-LF 402

1

R2151
100K
5% 1/16W MF-LF 402 2

2

2

2

=PP3V3_S0_MCP_GPIO

8C5 18C1 19D1

HDA Output Caps
1

=PP3V3_S3_MCP_GPIO

8D3

For EMI Reduction on HDA interface

R2140
10K
5% 1/16W MF-LF 402

1

R2141
10K
5% 1/16W MF-LF 402

1

R2142
10K
5% 1/16W MF-LF 402

1

R2143
10K
5% 1/16W MF-LF 402

2

R2154
100K
5% 1/16W MF-LF 402

HDA_SDOUT_R HDA_BIT_CLK_R HDA_RST_R_L HDA_SYNC_R

21D4 74A3 21D4 74B3

2

2

2

2

1
21C3 21C3 52C7 21B3 28A5 29A5 39B8 21B3 40D4

21D4 74A3 21D4 74B3

MCP_GPIO_4 AUD_I2C_INT_L MEM_EVENT_L SMC_IG_THROTTLE_L ARB_DETECT

AP_PWR_EN

21C3 31D5 34C7

MCP HDA & MISC
MCP_VID<0> MCP_VID<1> MCP_VID<2>
1
21C3 61B8

A

C2170
10PF
5% 50V CERM 402

1

C2172
10PF
5% 50V CERM 402

1
21B3

SYNC_MASTER=T18_MLB
21C3 61A8 21C3 61A8

SYNC_DATE=06/26/2008

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

2

2 1

R2147
100K
5% 1/16W MF-LF 402

R2155
22K
5% 1/16W MF-LF 402

1

R2156
22K
5% 1/16W MF-LF 402

1

R2157
22K
5% 1/16W MF-LF 402

1

C2171
10PF
5% 50V CERM 402

1

C2173
10PF
5% 50V CERM 402 2

2

2

2

2

2

REV.
C

D
APPLE INC.
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
SCALE NONE

SHT
21

OF
109

8

7

6

5

4

3

2

1

8
OMIT

7
U1400
MCP79-TOPO-B
BGA (11 OF 11) AH26 AH33 AH34 AH37 AH38 AJ39

6

5
OMIT

4
U1400
MCP79-TOPO-B

3

2

1

61B1 44D7 24D8 8C8

=PPVCORE_S0_MCP
AA25 AC23 U25 AH12 AG10 AG5 Y21 Y23 AA16 AA26 AA27 AA28 AC16 AC17 AC18 AC19 AC20 AC21 AA17 AC24 AC25 AC26 AC27 AC28 AD21 AD23 W27 V25 AA18 AE19 AE21 AE23 AE25 AE26 AE27 AE28 AF10 AF11 AA19 AF2 AF21 AF23 AF25 AF3 AF4 AF7 AH23 AF9 AA20 AG11 AG12 AG21 AG23 AG25 AG3 AG4 AA21 AG6 AG7 AG8 AG9 AH1 AH10 AH11 W26 AH2 AA23 W28 AH25 AH21 AH3 AH4 AH5 AH6 AH7 AH9 AA24 W21 W23 W25 AF12

BGA (10 OF 11)

=PP1V05_S0_MCP_FSB +VTT_CPU1 +VTT_CPU2 +VTT_CPU3 +VTT_CPU4 +VTT_CPU5 +VTT_CPU6 +VTT_CPU7 +VTT_CPU8 +VTT_CPU9 +VTT_CPU10 +VTT_CPU11 +VTT_CPU12 +VTT_CPU13 +VTT_CPU14 +VTT_CPU15 +VTT_CPU16 +VTT_CPU17 +VTT_CPU18 +VTT_CPU19 +VTT_CPU20 +VTT_CPU21 +VTT_CPU22 +VTT_CPU23 +VTT_CPU24 +VTT_CPU25 +VTT_CPU26 +VTT_CPU27 +VTT_CPU28 +VTT_CPU29 +VTT_CPU30 +VTT_CPU31 +VTT_CPU32 +VTT_CPU33 +VTT_CPU34 +VTT_CPU35 +VTT_CPU36 +VTT_CPU37 +VTT_CPU38 +VTT_CPU39 +VTT_CPU40 +VTT_CPU41 +VTT_CPU42 +VTT_CPU43 +VTT_CPU44 +VTT_CPU45 +VTT_CPU46 +VTT_CPU47 +VTT_CPU48 +VTT_CPU49 +VTT_CPU50 +VTT_CPU51 +VTT_CPU52
R32 AC32 E40 J36 N32 T32 U32 V32 W32 P31 AF32 AE32 AH32 AJ32 AK31 AK32 AD32 AL31 AB32 B41 B42 C40 C41 C42 D39 D40 D41 E38 E39 F37 F38 F39 G36 G37 G38 H35 H37 J34 J35 K33 K34 K35 L32 L33 L34 M31 M32 M33 N31 P32 Y32 AA32

8D7 9C2 14A2 14B7 24C8

D

AJ8 AK10 AK33 AK34 AK37 AK4 AK40 AL36 AL40 AL5 AM10 AM16 AM18 AM20 AM22 AM24 AM26 AM30 AM34 AM35 AM37 AM38 AM5 AM6 AM7 AM9

C

AP26 AN28 AN30 AN39 AN4 Y7 AP10 AU26 AP14 AU14 AP28 AP32 AP34 AP36 AP37 AP4 AP40 AP7 AW23 AR28 AR32 AR40 AT10 AR12 AT13 AT29

B

AT33 AT6 AT7 AT9 AY21 AY22 L12 AU12 AU28 AP33 AU32 AR30 AU36 AU38 AU4 G28 F20 AV28 AV32 AV36 AV4 AV7 AW11 G20 AR43 AW43

A

AY10 AV12 AY30 AY33 AY34 AY37 AY38 AY41

GND161 GND162 GND163 GND164 GND165 GND166 GND167 GND168 GND169 GND170 GND171 GND172 GND173 GND174 GND175 GND176 GND177 GND178 GND179 GND180 GND181 GND182 GND183 GND184 GND185 GND186 GND187 GND188 GND189 GND190 GND191 GND192 GND193 GND194 GND195 GND196 GND197 GND198 GND199 GND200 GND201 GND202 GND203 GND204 GND205 GND206 GND207 GND208 GND209 GND210 GND211 GND212 GND213 GND214 GND215 GND216 GND217 GND218 GND219 GND220 GND221 GND222 GND223 GND224 GND225 GND226 GND227 GND228 GND229 GND230 GND231 GND232 GND233 GND234 GND235 GND236 GND237 GND238 GND239 GND240 GND241 GND242 GND243 GND244 GND245 GND246 GND247 GND248 GND249 GND250 GND251 GND252

GND253 GND254 GND255 GND256 GND257 GND258 GND259 GND260 GND261 GND262 GND263 GND264 GND265 GND266 GND267 GND268 GND269 GND270 GND271 GND272 GND273 GND274 GND275 GND276 GND277 GND278 GND279 GND280 GND281 GND282 GND283 GND284 GND285 GND286 GND287 GND288 GND289 GND290 GND291 GND292 GND293 GND294 GND295 GND296 GND297 GND298 GND299 GND300 GND301 GND302 GND303 GND304 GND305 GND306 GND307 GND308 GND309 GND310 GND311 GND312 GND313 GND314 GND315 GND316 GND317 GND318 GND319 GND320 GND321 GND322 GND323 GND324 GND325 GND326 GND327 GND328 GND329 GND330 GND331 GND332 GND333 GND334 GND335 GND336 GND337 GND338 GND339 GND340 GND341 GND342 GND343

AV40 BA1 BA4 AW31 AY6 L35 BC33 BC37 BC41 AY14 BC5 C2 D10 D14 D15 D18 D19 D22 D23 D26 D30 D37 D6 E13 E17 E21 E25 E29 E33 F12 F16 F32 F8 G10 G12 G14 G16 BC12 G22 G24 AW20 G34 G4 G43 G6 G8 H11 H15 AW35 H23 AN8 G40 J12 J8 K10 K12 K18 K26 K37 K4 K40 K8 AU1 L40 L43 L5 M10 M34 M35 M37 Y28 Y33 Y34 Y35 Y37 Y38 AB17 AB16 AN26 AD7 M11 AA4 AB19 AY13 P11 Y6 T11 V11 Y11 AH16 T22

23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)

+VDD_CORE1 +VDD_CORE2 +VDD_CORE3 +VDD_CORE4 +VDD_CORE5 +VDD_CORE6 +VDD_CORE7 +VDD_CORE8 +VDD_CORE9 +VDD_CORE10 +VDD_CORE11 +VDD_CORE12 +VDD_CORE13 +VDD_CORE14 +VDD_CORE15 +VDD_CORE16 +VDD_CORE17 +VDD_CORE18 +VDD_CORE19 +VDD_CORE20 +VDD_CORE21 +VDD_CORE22 +VDD_CORE23 +VDD_CORE24 +VDD_CORE25 +VDD_CORE26 +VDD_CORE27 +VDD_CORE28 +VDD_CORE29 +VDD_CORE30 +VDD_CORE31 +VDD_CORE32 +VDD_CORE33 +VDD_CORE34 +VDD_CORE35 +VDD_CORE36 +VDD_CORE37 +VDD_CORE38 +VDD_CORE39 +VDD_CORE40 +VDD_CORE41 +VDD_CORE42 +VDD_CORE43 +VDD_CORE44 +VDD_CORE45 +VDD_CORE46 +VDD_CORE47 +VDD_CORE48 +VDD_CORE49 +VDD_CORE50 +VDD_CORE51 +VDD_CORE52 +VDD_CORE53 +VDD_CORE54 +VDD_CORE55 +VDD_CORE56 +VDD_CORE57 +VDD_CORE58 +VDD_CORE59 +VDD_CORE60 +VDD_CORE61 +VDD_CORE62 +VDD_CORE63 +VDD_CORE64 +VDD_CORE65 +VDD_CORE66 +VDD_CORE67 +VDD_CORE68 +VDD_CORE69 +VDD_CORE70 +VDD_CORE71 +VDD_CORE72 +VDD_CORE73 +VDD_CORE74 +VDD_CORE75 +VDD_CORE76 +VDD_CORE77 +VDD_CORE78 +VDD_CORE79 +VDD_CORE80 +VDD_CORE81

1139 mA

1182 mA (A01)

D

POWER

C

GND

+VTT_CPUCLK

AG32

43 mA

=PP3V3_S0_MCP +3.3V_1 +3.3V_2 +3.3V_3 +3.3V_4 +3.3V_5 +3.3V_6 +3.3V_7 +3.3V_8
AD10 AE8 AB10 AD9 Y10 AB11 AA8 Y9

8C5 21C2 24B8

450 mA (A01)

B

=PP3V3_S5_MCP +3.3V_DUAL1 +3.3V_DUAL2 +3.3V_DUAL3 +3.3V_DUAL4 +3.3V_DUAL_USB1 +3.3V_DUAL_USB2 +3.3V_DUAL_USB3 +3.3V_DUAL_USB4
G18 H19 J20 K20

8A3 24B8

16 mA

266 mA (A01)

G26 H27 J28 K28

250 mA

=PP1V05_S5_MCP_VDD_AUXC +VDD_AUXC1 +VDD_AUXC2 +VDD_AUXC3
T21 U21 V21

8B3 24D8

26D4 21C8 7C3

PP3V3_G3_RTC 10 uA (G3) 80 uA (S0)
A20

105 mA (A01)

MCP Power & Ground
SYNC_MASTER=T18_MLB SYNC_DATE=04/04/2008

+VBAT

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
SCALE NONE

SHT
22

OF
109

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

D

3.3V Interface Pull-ups
These internal pull-ups are missing in Revs A01 & A01P.
41B4 8A3

=PP3V3_S5_MCP_A01

19C4 13C6

OUT

PM_LATRIGGER_L PCIE_WAKE_L JTAG_MCP_TDI JTAG_MCP_TMS PM_SYSRST_DEBOUNCE_L TP_MCP_LID_L MCP_LID_L
MAKE_BASE=TRUE

MCP_A01&MCP_A01P&MCP_A01Q 10K R2400 1 2

31C7 17B6 7D5

OUT

R2401 R2402 R2403 R2404 R2405

MCP_A01&MCP_A01P&MCP_A01Q 10K 1 2 MCP_A01&MCP_A01P&MCP_A01Q 10K 1 2
5% 5%

5%

1/16W

MF-LF

402

1/16W

MF-LF

402

21B7 13C3 6C5

OUT

1/16W

MF-LF

402

21B7 13C3 6C5

OUT

MCP_A01&MCP_A01P&MCP_A01Q 10K 1 2 MCP_A01&MCP_A01P&MCP_A01Q 10K 1 2 MCP_A01&MCP_A01P&MCP_A01Q 10K 1 2
5% 5% 5% 1/16W MF-LF 402

C

26A1 21C7

OUT

1/16W

MF-LF

402

C

21C7

OUT

1/16W

MF-LF

402

39C5 21C7

OUT

SMC_WAKE_SCI_L SMC_RUNTIME_SCI_L PM_PWRBTN_L PM_BATLOW_L

MCP_A01&MCP_A01P&MCP_A01Q 10K R2410 1 2

39B8 21C7

OUT

R2411 R2412 R2413

MCP_A01&MCP_A01P&MCP_A01Q 10K 1 2
5%

5%

1/16W

MF-LF

402

1/16W

MF-LF

402

39C8 21C7

OUT

MCP_A01&MCP_A01P&MCP_A01Q 10K 1 2 MCP_A01&MCP_A01P&MCP_A01Q 10K 1 2
5% 5% 1/16W MF-LF 402

39B8 21C7

OUT

1/16W

MF-LF

402

MCP_SAFE_MODE SIGNAL TO SUPPORT ROM FAILURE OVERRIDE
RADAR 5925345

R2430

B

21C3

MCP_SPKR

1

0

2

SMC_MCP_SAFE_MODE

IN

39B5

5% 1/16W MF-LF 402

B

MCP79 A01 Silicon Support

A

SYNC_MASTER=T18_MLB

SYNC_DATE=03/08/2008

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
SCALE NONE

SHT
24

OF
109

8

7

6

5

4

3

2

1

8
MCP Core Power
61B1 44D7 22D5 8C8

7

6

5

4

3

2

1

=PPVCORE_S0_MCP 23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF) Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)

(No IG vs. EG data)

C2500
4.7UF
20% 4V X5R 402

1

C2501
4.7UF
20% 4V X5R 402

1

C2502
4.7UF
20% 4V X5R 402

1

C2503
4.7UF
20% 4V X5R 402

1

1

C2504
1UF
10% 10V X5R 402-1

1

C2505
1UF
10% 10V X5R 402-1

1

C2506
1UF
10% 10V X5R 402-1

1

C2507
1UF
10% 10V X5R 402-1

1

C2508
0.1UF
20% 10V CERM 402

1

C2509
0.1UF
20% 10V CERM 402

1

C2510
0.1UF
20% 10V CERM 402

1

C2511
0.1UF
20% 10V CERM 402

1

C2512
0.1UF
20% 10V CERM 402

1

C2513
0.1UF
20% 10V CERM 402

2

2

2

2

2

2

2

2

2

2

2

2

2

2

D
8C7 8A8

MCP PCIE (DVDD) Power =PP1V05_S0_MCP_PEX_DVDD 57 mA (A01)
8B7 8A8

MCP SATA (DVDD) Power =PP1V05_S0_MCP_SATA_DVDD 43 mA (A01)
8B7

L2570
=PP1V05_S0_MCP_AVDD_UF 333 mA (A01)
1 0603

30-OHM-5A
2

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF) Apple: 5x 2.2uF 0402 (11 uF) PP1V05_S0_MCP_PEX_AVDD
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V 1

D
8A8

206 mA (A01)

C2515
4.7UF
20% 4V X5R 402

1

1

C2516
1UF
10% 10V X5R 402-1

1

C2517
1UF
10% 10V X5R 402-1

1

C2518
0.1uF
20% 10V CERM 402

1

C2519
0.1uF
20% 10V CERM 402

C2520
4.7UF
20% 4V X5R 402

1

1

C2521
0.1uF
20% 10V CERM 402

C2570
2.2UF
20% 6.3V CERM 402-LF

1

C2571
2.2UF
20% 6.3V CERM 402-LF

1

C2572
2.2UF
20% 6.3V CERM 402-LF

1

C2573
2.2UF
20% 6.3V CERM 402-LF

1

C2574
2.2UF
20% 6.3V CERM 402-LF

2

2

2

2

2

2

2

2

2

2

2

2

MCP 1.05V AUX Power
22A3 8B3

MCP 1.05V RMGT Power
18D3 8B1

L2575
30-OHM-5A
1 0603 2

=PP1V05_S5_MCP_VDD_AUXC 105 mA (A01)
1

=PP1V05_ENET_MCP_RMGT 131 mA (A01)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) Apple: 2x 2.2uF 0402 (4.4 uF) PP1V05_S0_MCP_SATA_AVDD 8A8
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V 1

127 mA (A01)

C2525
0.1uF
20% 10V CERM 402

1

C2526
0.1uF
20% 10V CERM 402

C2528
4.7uF
20% 4V X5R 402

1

1

C2529
0.1uF
20% 10V CERM 402

C2575
2.2UF
20% 6.3V CERM 402-LF

1

C2576
2.2UF
20% 6.3V CERM 402-LF

2

2

2

2

2

2

MCP FSB (VTT) Power
14B7 14A2 9C2 8D7 22D3

=PP1V05_S0_MCP_FSB

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) Apple: 7x 2.2uF 0402 (15.4 uF)
8B7

L2580
=PP1V05_S0_MCP_PLL_UF 562 mA (A01)
1 0402

30-OHM-1.7A
2

PP1V05_S0_MCP_PLL_FSB
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V 1 1

14A6

1182 mA (A01)

270 mA (A01)

C

1

C2530
2.2UF
20% 6.3V CERM 402-LF

1

C2531
2.2UF
20% 6.3V CERM 402-LF

1

C2532
2.2UF
20% 6.3V CERM 402-LF

1

C2533
2.2UF
20% 6.3V CERM 402-LF

1

C2534
2.2UF
20% 6.3V CERM 402-LF

1

C2535
2.2UF
20% 6.3V CERM 402-LF

1

C2536
2.2UF
20% 6.3V CERM 402-LF

C2580
4.7UF
20% 4V X5R 402

C2581
0.1UF
20% 10V CERM 402

C

2

2

2

2

2

2

2

2

2

MCP Memory Power
16C7 16C3 8B7

L2582
30-OHM-1.7A
1 0402 2

=PP1V8R1V5_S0_MCP_MEM 4771 mA (A01, DDR3)

PP1V05_S0_MCP_PLL_PEX
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V 1 1

17A6

84 mA (A01)

C2540
4.7UF
20% 4V X5R 402

1

1

C2541
0.1UF
20% 10V CERM 402

1

C2542
0.1UF
20% 10V CERM 402

1

C2543
0.1UF
20% 10V CERM 402

1

C2544
0.1UF
20% 10V CERM 402

1

C2545
0.1UF
20% 10V CERM 402

1

C2546
0.1UF
20% 10V CERM 402

1

C2547
0.1UF
20% 10V CERM 402

1

C2548
0.1UF
20% 10V CERM 402

1

C2549
0.1UF
20% 10V CERM 402

C2582
4.7UF
20% 4V X5R 402

C2583
0.1UF
20% 10V CERM 402

2

2

2

2

2

2

2

2

2

2

2

2

MCP 3.3V Power
22B3 21C2 8C5

=PP3V3_S0_MCP 450 mA (A01)

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF) Apple: 4x 2.2uF 0402 (8.8 uF)
8C5

L2555
=PP3V3_S0_MCP_PLL_UF 19 mA (A01)
1 0402

30-OHM-1.7A
2

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF) PP3V3_S0_MCP_PLL_USB 20C3
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V 1

L2584
30-OHM-1.7A
1 0402 2

PP1V05_S0_MCP_PLL_SATA
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V 1 1

20B6

19 mA (A01)

84 mA (A01)

1

C2550
2.2UF
20% 6.3V CERM 402-LF

1

C2551
2.2UF
20% 6.3V CERM 402-LF

1

C2552
2.2UF
20% 6.3V CERM 402-LF

1

C2553
2.2UF
20% 6.3V CERM 402-LF

C2555
2.2UF
20% 6.3V CERM 402-LF

C2584
4.7UF
20% 4V X5R 402

C2585
0.1UF
20% 10V CERM 402

2

2

2

2

2

2

2

B
MCP 3.3V AUX/USB Power
22B3 8A3

B
L2586
30-OHM-1.7A
1 0402 2

=PP3V3_S5_MCP 266 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)
24A5 18D7 18D3 8B1

MCP 3.3V Ethernet Power =PP3V3_ENET_MCP_RMGT 83 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)

PP1V05_S0_MCP_PLL_CORE
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V 1 1

16C6

87 mA (A01)

1

C2560
2.2UF
20% 6.3V CERM 402-LF

1

C2564
2.2UF
20% 6.3V CERM 402-LF

C2586
4.7UF
20% 4V X5R 402

C2587
0.1UF
20% 10V CERM 402

2

2

2

2

MCP 3.3V/1.5V HDA Power
21D8 21D3 8B5

=PP3V3R1V5_S0_MCP_HDA 7 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)

L2588
30-OHM-1.7A
1 0402 2

PP1V05_S0_MCP_PLL_NV
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V 1 1

21C7

37 mA (A01)

1

C2562
2.2UF
20% 6.3V CERM 402-LF
24B6 18D7 18D3 8B1

C2588

C2589
0.1UF
20% 10V CERM 402

1

C2590
0.1UF
20% 10V CERM 402

2

MCP79 Ethernet VRef
=PP3V3_ENET_MCP_RMGT

4.7UF
20% 4V X5R 402 2 2

2

R2591 1
1.47K

MCP Standard Decoupling
SYNC_MASTER=T18_MLB SYNC_DATE=04/04/2008

A
8B1

L2595
=PP1V05_ENET_MCP_PLL_MAC 5 mA (A01)
1 0402

1% 1/16W MF-LF 402

2

NOTICE OF PROPRIETARY PROPERTY
MCP_MII_VREF
OUT
18D3

A

30-OHM-1.7A
2

PP1V05_ENET_MCP_PLL_MAC
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V 1 1

18C6

5 mA (A01)

R2590 1
1.47K
1% 1/16W MF-LF 402 2

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

1

C2595
4.7UF
20% 4V X5R 402

C2596
0.1UF
20% 10V CERM 402

C2591
0.1UF
20% 10V CERM 402

2

2

2

REV.
C

D
APPLE INC.
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
SCALE NONE

SHT
25

OF
109

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

WF: Checklist says 0-ohm resistor placeholder for ferrite bead. NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)
18B6 8A7

NO STUFF

L2650
8C5

=PP3V3R1V8_S0_MCP_IFP_VDD 190 mA (A01, 1.8V)
1

=PP3V3_S0_MCP_DAC_UF 206 mA (A01)
1

30-OHM-1.7A
2 0402

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF) Apple: 2x 2.2uF 0402 (4.4 uF) PP3V3_S0_MCP_DAC NO STUFF
1 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

18C3

206 mA (A01)

C2610
2.2UF
20% 6.3V CERM 402-LF

1

C2650
2.2UF
20% 6.3V CERM 402-LF

R2651
0
5% 1/16W MF-LF

2

D

2

2 402

D

18A6 8B7

=PP1V05_S0_MCP_HDMI_VDD 95 mA (A01)

C2615
4.7UF
20% 4V X5R 402

1

1

C2616
0.1UF
20% 10V CERM 402

2

2

73B3 18A6 73B3 18A6

MCP_HDMI_RSET MCP_HDMI_VPROBE NO STUFF
1

73B3 18A3 73B3 18A3

MCP_IFPAB_RSET MCP_IFPAB_VPROBE NO STUFF

NO STUFF
1

C

R2620
1K
1% 1/16W MF-LF 402

R2630
1K
1% 1/16W MF-LF 402

C2620
0.1UF
20% 10V CERM 402

1

C2630
0.1UF
20% 10V CERM 402

1

C

2

2

2

2

8C5

=PP3V3_S0_MCP_VPLL_UF 16 mA (A01)

WF: Checklist says 0-ohm resistor placeholder for ferrite bead. NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) L2640 Apple: ??? 30-OHM-1.7A PP3V3_S0_MCP_VPLL 18B6
1 0402 2

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V 1 1

16 mA (A01)

C2640
4.7UF
20% 6.3V CERM 603

C2641
0.1uF
20% 10V CERM 402

2

2

B

B

HDCP ROM
WF: Open question on which packge option(s) nVidia can support.
8C5

=PP3V3_S0_HDCPROM

C2690
0.1UF
20% 10V CERM 402

1 8 2

R2690 1
NOSTUFF 10K
5% 1/16W MF-LF 402

VCC U2695
AT24C08

2

A0 2 A1 3 A2
1

SOIC

SDA SCL WP GND
4

5 6

=I2C_HDCPROM_SDA =I2C_HDCPROM_SCL
25A8

BI IN

42C6 42C6

7

HDCPROM_WP

4

NOSTUFF

MCP Graphics Support
SYNC_MASTER=T18_MLB SYNC_DATE=12/12/2007

A
25A7

VCC

U2690
AT24C01B
SOT23

NOTICE OF PROPRIETARY PROPERTY
3 1

A

HDCPROM_WP

5

WP GND
2

SDA SCL

SYNC FROM T18 REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672 NOSTUFF PP3V3_S0_MCP_DAC RAIL COMPONENTS (L2650 AND C2650) CHANGE C2651 TO R2651 TO GND PP3V3_S0_MCP_DAC

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

REV.
C

D
APPLE INC.
SCALE NONE

SHT
26

OF
109

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

RTC Power Sources
1 VIN

Platform Reset Connections
LPC Reset (Unbuffered)
5
1

U2801
MIC5232-2.8YD5
TSOT-23-5 3
8D1

EN

CRITICAL VOUT

PP3V3_G3_RTC

7C3 21C8 22A5

=PP3V42_G3H_RTC_D
NC

D

0.47UF
2 10% 10V X5R 402

R2819
100
402

2

4

C2871

C2819
10%

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
74C3 19C3

R2881
IN

LPC_RESET_L

PLACEMENT_NOTE=Place close to U1400

1

33
5% 1/16W MF-LF 402

2

DEBUG_RESET_L

1 2

OUT

41D5

1

C2870
1UF
10% 10V X5R 402

GND 2

1UF 6.3V
1 MF-LF

R2883
1

D
39C8

33
5% 1/16W MF-LF 402

2

CERM 402

2

SMC_LRESET_L

OUT

PLACEMENT_NOTE=Place close to U1400

PP3V3_G3_SUPERCAP
1

C2800
0.08F PLACEMENT_NOTE=PLACE C2819 CLOSE TO MCP79

2% 2 3.3V XHHG SM

PLACE C2819 CLOSE TO MCP79 PLACE C2800 AT COOLEST SPOT ON MLB
17B3

PCIE Reset (Unbuffered)
R2892
0
5% 1/16W MF-LF 402

RTC Crystal
21B7

C2810
12pF
1 2 5% 50V CERM 402

IN

RTC_CLK32K_XTALOUT

IN

PCIE_RESET_L

1

2

BKLT_PLT_RST_L

OUT

70C8

R2810
0

1

R2891
1

0
5% 1/16W MF-LF 402

5% 1/16W MF-LF 402 2

2

MINI_RESET_L

OUT

31A6

R2871
1

NO STUFF

RTC_CLK32K_XTALOUT_R CRITICAL

0
5% 1/16W MF-LF 402

2

R2811
10M

1

PCA9557D_RESET_L

OUT

27A5

1

5% 1/16W MF-LF 402 2

Y2810
32.768K

4

R2872 C2811
12pF
1 5% 50V CERM 402 2 5% 1/16W MF-LF 402

0
1 2

FC_RESET_L

7X1.5X1.4-SM

OUT

32B3

C

21B7

OUT

RTC_CLK32K_XTALIN

C
=DDRVTT_EN
OUT
59C8 65A3

R2870
19C4

IN

MEM_VTT_EN_R

33
1 5% 1/16W MF-LF 402 2

MEM_VTT_EN MAKE_BASE=TRUE

MCP 25MHz Crystal
21B7

C2815
12pF
1 2 5% 50V CERM 402
74C3 19B3

IN

MCP_CLK25M_XTALOUT

R2825
IN

R28151
0
NO STUFF

LPC_CLK33M_SMC_R

PLACEMENT_NOTE=Place close to U1400

33
1 5% 1/16W MF-LF 402 2

LPC_CLK33M_SMC

OUT

39C8 74C3

R2816 1
1M
5% 1/16W MF-LF 402 2

5% 1/16W MF-LF 402 2

R2826
33
1 2 5% 1/16W MF-LF 402

LPC_CLK33M_LPCPLUS

OUT

41D3 74C3

MCP_CLK25M_XTALOUT_R CRITICAL

PLACEMENT_NOTE=Place close to U1400

3

Y2815
25.0000M
1 SM-3.2X2.5MM
21B7

NC NC

R2829 C2816
12pF
1 5% 50V CERM 402 2
74A3 21B3

4

IN

PM_CLK32K_SUSCLK_R

2

1 PLACEMENT_NOTE=Place close to U1400

22
5% 1/16W MF-LF 402

2

PM_CLK32K_SUSCLK

OUT

39C5 74A3

OUT

MCP_CLK25M_XTALIN

B

MCP S0 PWRGD & CPU_VLD
8A3

B

=PP3V3_S5_MCPPWRGD MCPSEQ_SMC
1

C2850
0.1UF
20% 10V CERM 402
39B8

2

Reset Button
IN

PM_SYSRST_L XDP

MCPSEQ_SMC
5 TC7SZ08AFEAPE
64A4 39D8

IN

ALL_SYS_PWRGD VR_PWRGOOD_DELAY

2

A

SOT665
4

R2853
1

R2898
MCP_PS_PWRGD
OUT
21B7 13B3 10C6

R2899
1

10K pull-up to 3.3V S0 inside MCP PM_SYSRST_DEBOUNCE_L NO STUFF
1

60C7

IN

1

U2850Y
B

S0_AND_IMVP_PGOOD

0
5% 1/16W MF-LF 402

2

IN

XDP_DBRESET_L

1

0
5% 1/16W MF-LF 402

2

33
5% 1/16W MF-LF 402

2

OUT

21C7 23C5

R28901
0
5% 1/16W MF-LF 402 2

NO STUFF

3

C2899
1UF
10% 10V X5R 402

MCPSEQ_MIX

SILK_PART=SYS RST

2

R2852
0
1 2

MCPSEQ_MIX

R2851
1

5% 1/16W MF-LF 402

0
5% 1/16W MF-LF 402

2

MCP_CPU_VLD MCPSEQ_SMC

OUT

21B7

R2850
1

SB Misc
SYNC_MASTER=RAYMOND SYNC_DATE=04/05/2008

A

21B3

IN

MCP_CPUVDD_EN

0
5% 1/16W MF-LF 402

2

PLACEMENT_NOTE=Place close to U1400

MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections, but results in MCP79 ROMSIP sequence happening after CPU powers up. MCPSEQ_MIX is cross between MLB and internal power sequencing, which results in earlier ROMSIP and MCP FSB I/O interface initialization. SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion). NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.

SYNC FROM T18 CHANGE RESET BUTTOM TO RESET PADS REMOVE UNUSED PCIE RESET SIGNALS REMOVE R2824 AND NET PCI_CLK33M_SLOT_A CHANGE RTC COIN CELL TO LDO & SUPERCAP ALIAS MEM_VTT_EN TO =DDRVTT_EN CHANGE Y2810 AND U2850 TO SMALLER PARTS

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
SCALE NONE

SHT
28

OF
109

8

7

6

5

4

3

2

1

8

7
MEM A VREF DQ DAC channel Min DAC code Max DAC code Max sink I Max source I Nominal Vref Min Vref Max Vref Vref Stepping (per DAC LSB) A 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV

6
MEM A VREF CA B 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV MEM B VREF DQ A 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV

5
MEM B VREF CA B 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV CPU FSB VREF C 0x00 0x55 -0.91 mA 0.52 mA 0.70 V 0.091 V 1.044 V 11.2 mV

4

3

2

1

Page Notes
Power aliases required by this page: - =PP3V3_S3_VREFMRGN - =PP3V3_S5_VREFMRGN - =PPVTT_S3_DDR_BUF Signal aliases required by this page: - =I2C_VREFDACS_SCL - =I2C_VREFDACS_SDA - =I2C_PCA9557D_SCL - =I2C_PCA9557D_SDA

SO-DIMM A and SO-DIMM B Vref settings should be margined separately (i.e. not simultaneously) due to current limitation of TPS51116 regulator.
=PPVTT_S3_DDR_BUF
59D7 8C4

D

BOM options provided by this page: VREFMRGN NO_VREFMRGN

10mA max load

D
R2903
1 VREFMRGN

200

2

VREFMRGN
1

B1 A2

U2902
MAX4253
VREFMRGN_DQ_SODIMMA_BUF A4

1% 1/16W MF-LF 402

PP0V75_S3_MEM_VREFDQ_A
28D5

C2903
0.1UF

=PP3V3_S3_VREFMRGN
8D3

20% 10V 2 CERM 402

UCSP A1 VREFMRGN A3

V+

R2904
1

VREFMRGN

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

100

2

VB4

27A5 VREFMRGN_DQ_SODIMMA_EN

1% 1/16W MF-LF 402

Place close to J3100.1
VREFMRGN

C2900
2.2UF
20% 6.3V CERM 402-LF

1

C2901
0.1UF
B1 C2

2

VREFMRGN

VREFMRGN
20% 2 10V CERM 402

R2901
100K

R2905
1 VREFMRGN

200

2

U2902
MAX4253
C4

5% 1/16W MF-LF 402

1% 1/16W MF-LF 402

1

PP0V75_S3_MEM_VREFDQ_B
29D5

VREFMRGN
6 SCL 7 SDA 9 A0 8 U2900 VDD 1 MSOP VOUTA
C3 VREFMRGN_DQ_SODIMM VREFMRGN_CA_SODIMM VREFMRGN_CPUFSB

UCSP C1 VREFMRGN

V+

R2906
VREFMRGN_DQ_SODIMMB_BUF 1

VREFMRGN

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

100

2

VB4

27A5 VREFMRGN_DQ_SODIMMB_EN

42B3

IN BI

=I2C_VREFDACS_SCL =I2C_VREFDACS_SDA

1% 1/16W MF-LF 402

Place close to J3200.1
VREFMRGN

DAC5574

42B3

VOUTB 2 VOUTC 4 VOUTD 5

R2902
100K

R2909
VREFMRGN 1

2

200

2

C

ADDR=0x98(WR)/0x99(RD)

10 A1

NC

5% 1/16W MF-LF 402

VREFMRGN
GND 3
1

B1 A2

U2903
MAX4253
VREFMRGN_CA_SODIMMA_BUF A4

1% 1/16W MF-LF 402

1

PP0V75_S3_MEM_VREFCA_A
28B3

C2904
0.1UF

20% 10V 2 CERM 402

UCSP A1 VREFMRGN A3

V+

R2910
1

VREFMRGN

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

C

100

2

VB4

27B5 VREFMRGN_CA_SODIMMA_EN

1% 1/16W MF-LF 402

Place close to J3100.126
VREFMRGN

R2907
100K
B1 C2

R2911
1 VREFMRGN

2

200

2

U2903
MAX4253
C4

5% 1/16W MF-LF 402

1% 1/16W MF-LF 402

1

PP0V75_S3_MEM_VREFCA_B
29B3

UCSP C1 VREFMRGN C3

V+

R2912
VREFMRGN_CA_SODIMMB_BUF 1

VREFMRGN

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

100

2

VB4

27A5 VREFMRGN_CA_SODIMMB_EN

1% 1/16W MF-LF 402

Place close to J3200.126

R2908
100K VREFMRGN
1 B1 A2

2 VREFMRGN 1

U2904
MAX4253
UCSP A1 A4

5% 1/16W MF-LF 402

C2905
0.1UF

V+

20% 10V 2 CERM 402

VREFMRGN A3

NC

VB4

B
B1

B
VREFMRGN
16 1 C2

U2904
MAX4253
UCSP C1 C4 VREFMRGN_CPUFSB_BUF

C2902
0.1UF

VREFMRGN
C3

V+

R2914
1

VREFMRGN

100

VREFMRGN

2

CPU_GTLREF

OUT

10B4 71B3

20% 10V 2 CERM 402

VCC

PCA9557
QFN 3

U2901

VB4

27B5 VREFMRGN_CPUFSB_EN

1% 1/16W MF-LF 402

Place close to U1000.AD26

ADDR=0x30(WR)/0x31(RD)

A0 A1 5 A2
4

42B3 42B3

IN BI

=I2C_PCA9557D_SCL =I2C_PCA9557D_SDA

1 2

SCL SDA
THRM

P0 P1 P2 P3 P4 P5 P6 P7

NC

7 9 10 11 12 13 14

VREFMRGN_CPUFSB_EN
27B3

VREFMRGN_CA_SODIMMA_EN
27C3

100K
5% 1/16W MF-LF 402 1

2 VREFMRGN

6

R2913
27D3

VREFMRGN_DQ_SODIMMA_EN VREFMRGN_CA_SODIMMB_EN
27B3

VREFMRGN_DQ_SODIMMB_EN
27C3

NC NC
PCA9557D_RESET_L IN
26C1

RESET* 15 GND
8

PAD
17

FSB/DDR3 Vref Margining

A
Required zero ohm resistors when no VREF margining circuit stuffed

SYNC_MASTER=BEN

SYNC_DATE=03/31/2008

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

A

PART NUMBER 116S0004 116S0004 116S0004 116S0004

QTY 1 1 1 1

DESCRIPTION
RES,MTL FILM,0,5%,0402,SM,LF RES,MTL FILM,0,5%,0402,SM,LF RES,MTL FILM,0,5%,0402,SM,LF RES,MTL FILM,0,5%,0402,SM,LF

REFERENCE DES R2903 R2905 R2909 R2911

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

BOM OPTION NO_VREFMRGN NO_VREFMRGN NO_VREFMRGN NO_VREFMRGN

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

REV.
C

D
APPLE INC.
SCALE NONE

SHT
29

OF
109

8

7

6

5

4

3

2

1

8
Page Notes
Power aliases required by this page: - =PP1V5_S0_MEM_A - =PP1V5_S3_MEM_A - =PP0V75_S0_MEM_VTT_A - =PPSPD_S0_MEM_A (2.5 - 3.3V) Signal aliases required by this page: - =I2C_SODIMMA_SCL - =I2C_SODIMMA_SDA

7
8D3

6
=PP1V5_S3_MEM_A

5

4

3

2

1

DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)
1

C3100
10UF
20% 6.3V X5R 603

1

C3101
10UF
20% 6.3V X5R 603

1

C3110
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3111
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3112
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3113
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3114
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3115
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3116
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3117
0.1UF
20% 0204-1

2

2

2

2

2

2

2

2

2

2 6.3V X6S-CERM

D

BOM options provided by this page:
27D1

PP0V75_S3_MEM_VREFDQ_A

(NONE)

D
1

C3130
2.2UF
20% 6.3V CERM 402-LF

1

C3131
0.1UF
20% 10V CERM 402

2

2

1

72D3 15A5

IN

MEM_A_CKE<0>

73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

KEY

NC
72D3 15C5

IN

MEM_A_BA<2> MEM_A_A<12> MEM_A_A<9> MEM_A_A<8> MEM_A_A<5> MEM_A_A<3> MEM_A_A<1> MEM_A_CLK_P<0> MEM_A_CLK_N<0> MEM_A_A<10> MEM_A_BA<0> MEM_A_WE_L MEM_A_CAS_L MEM_A_A<13> MEM_A_CS_L<1>

72D3 15C5 72D3 15C5

IN IN

72D3 15C5 72D3 15B5

IN IN

72D3 15B5 72D3 15B5

IN IN

72D3 15B5

IN IN

C

72D3 15B5

72D3 15C5 72D3 15C5

IN IN

72D3 15C5 72D3 15C5

IN IN

72D3 15C5 72D3 15B5

IN IN

NC
72D3 15C7 72D3 15C7

BI BI

MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQS_N<4> MEM_A_DQS_P<4> MEM_A_DQ<34> MEM_A_DQ<38> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DM<5> MEM_A_DQ<47> MEM_A_DQ<46> MEM_A_DQ<49> MEM_A_DQ<52> MEM_A_DQS_N<6> MEM_A_DQS_P<6> MEM_A_DQ<54> MEM_A_DQ<51> MEM_A_DQ<61> MEM_A_DQ<60> MEM_A_DM<7> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_SA<0>

72C3 15D5 72C3 15D5

BI BI

72D3 15C7 72D3 15C7

BI BI

72D3 15C7 72D3 15C7

BI BI

72C3 15B7

IN

B

72D3 15D7 72D3 15D7

BI BI

72D3 15D7 72D3 15D7

BI BI

72C3 15D5 72C3 15D5

BI BI

72D3 15D7 72D3 15D7

BI BI

72D3 15D7 72D3 15D7

BI BI

72C3 15B7

IN

72D3 15D7 72D3 15D7

BI BI

8B5

=PPSPD_S0_MEM_A MEM_A_SA<1>

CKE0 CKE1 VDD VDD NC A15 BA2 A14 F-RT-THB VDD VDD A12/BC* A11 A9 A7 VDD VDD A8 A6 A5 A4 VDD VDD A3 A2 A1 A0 VDD VDD CK1 CK0 CK0* CK1* VDD VDD A10/AP BA1 RAS* BA0 VDD VDD WE* S0* CAS* ODT0 VDD VDD ODT1 A13 S1* NC VDD VDD TEST VREFCA VSS VSS DQ32 DQ36 DQ33 DQ37 VSS VSS DM4 DQS4* DQS4 VSS DQ38 VSS DQ39 DQ34 DQ35 VSS VSS DQ44 DQ45 DQ40 DQ41 VSS VSS DQS5* DM5 DQS5 VSS VSS DQ42 DQ46 DQ43 DQ47 VSS VSS DQ48 DQ52 DQ49 DQ53 VSS VSS DQS6* DM6 VSS DQS6 DQ54 VSS DQ50 DQ55 DQ51 VSS VSS DQ60 DQ56 DQ61 DQ57 VSS VSS DQS7* DM7 DQS7 VSS VSS DQ58 DQ62 DQ59 DQ63 VSS VSS SA0 EVENT* VDDSPD SDA SCL SA1 VTT VTT

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

MEM_A_CKE<1> MEM_A_A<15> MEM_A_A<14> MEM_A_A<11> MEM_A_A<7> MEM_A_A<6> MEM_A_A<4> MEM_A_A<2> MEM_A_A<0> MEM_A_CLK_P<1> MEM_A_CLK_N<1> MEM_A_BA<1> MEM_A_RAS_L MEM_A_CS_L<0> MEM_A_ODT<0> MEM_A_ODT<1>

IN

15A5 72D3

72D3 15B7 72D3 15B7

BI BI

MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DM<0> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<12> MEM_A_DQS_N<1> MEM_A_DQS_P<1> MEM_A_DQ<10> MEM_A_DQ<15> MEM_A_DQ<25> MEM_A_DQ<24> MEM_A_DQS_N<3> MEM_A_DQS_P<3> MEM_A_DQ<26> MEM_A_DQ<30> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DM<2> MEM_A_DQ<23> MEM_A_DQ<16>

3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

J3100
DDR3-SODIMM-DUAL-M97-3
(SYMBOL 2 OF 2)

IN IN

9D2 15C5 72D3 72D3 15A7

IN

IN IN

15C5 72D3 15C5 72D3

72D3 15B7 72D3 15B7

BI BI

IN IN

15B5 72D3 15B5 72D3

72D3 15B7 72D3 15B7

BI BI

IN IN

15B5 72D3 15B5 72D3

72C3 15D5 72C3 15D5

BI BI

IN IN

15B5 72D3 15B5 72D3

72D3 15B7 72D3 15B7

BI BI

IN IN

15C5 72D3 15C5 72D3

72D3 15C7 72D3 15C7

BI BI

IN IN

15B5 72D3 15B5 72D3

72C3 15D5 72C3 15D5

BI BI

IN

15B5 72D3

72D3 15C7 72D3 15C7

BI BI

124

NC

72D3 15C7 72D3 15C7

BI BI

MEM_A_DQ<37> MEM_A_DQ<36> MEM_A_DM<4> MEM_A_DQ<35> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQS_N<5> MEM_A_DQS_P<5> MEM_A_DQ<43> MEM_A_DQ<42> MEM_A_DQ<53> MEM_A_DQ<48> MEM_A_DM<6> MEM_A_DQ<55> MEM_A_DQ<50> MEM_A_DQ<57> MEM_A_DQ<56> MEM_A_DQS_N<7> MEM_A_DQS_P<7> MEM_A_DQ<62> MEM_A_DQ<63> MEM_EVENT_L =I2C_SODIMMA_SDA =I2C_SODIMMA_SCL

BI BI

15C7 72D3 15C7 72D3 72C3 15B7

IN

IN

15B7 72C3

72D3 15C7 72D3 15B7

BI BI

BI BI

15C7 72D3 15C7 72D3

VREFDQ VSS VSS DQ4 DQ5 DQ0 CRITICAL VSS DQ1 VSS DQS0* DQS0 DM0 F-RT-THB VSS VSS DQ2 DQ6 DQ3 DQ7 VSS VSS DQ12 DQ8 DQ13 DQ9 VSS VSS DQS1* DM1 RESET* DQS1 VSS VSS DQ14 DQ10 DQ15 DQ11 VSS VSS DQ20 DQ16 DQ17 DQ21 VSS VSS DQS2* DM2 DQS2 VSS DQ22 VSS DQ18 DQ23 VSS DQ19 DQ28 VSS DQ24 DQ29 VSS DQ25 DQS3* VSS DQS3 DM3 VSS VSS DQ30 DQ26 DQ31 DQ27 VSS VSS

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQS_N<0> MEM_A_DQS_P<0> MEM_A_DQ<3> MEM_A_DQ<2> MEM_A_DQ<9> MEM_A_DQ<13> MEM_A_DM<1> MEM_RESET_L MEM_A_DQ<11> MEM_A_DQ<14> MEM_A_DQ<29> MEM_A_DQ<28> MEM_A_DM<3> MEM_A_DQ<27> MEM_A_DQ<31> MEM_A_DQ<18> MEM_A_DQ<17> MEM_A_DQS_N<2> MEM_A_DQS_P<2> MEM_A_DQ<19> MEM_A_DQ<22>

BI BI

15B7 72D3 15B7 72D3

J3100
DDR3-SODIMM-DUAL-M97-3
(SYMBOL 1 OF 2)

BI BI

15D5 72C3 15D5 72C3

BI BI

15B7 72D3 15B7 72D3

BI BI

15B7 72D3 15B7 72D3

IN IN

15A7 72C3 29C2 30C3

BI BI

15B7 72D3 15B7 72D3

C

BI BI

15C7 72D3 15C7 72D3

IN

15B7 72C3

BI BI

15C7 72D3 15C7 72D3

BI BI

15B7 72D3 15B7 72D3

BI BI

15D5 72C3 15D5 72C3

BI BI

15B7 72D3 15C7 72D3

KEY

BI BI

15C7 72D3 15C7 72D3

516-0201

BI BI

15D5 72C3 15D5 72C3

BI BI

15C7 72D3 15C7 72D3

B

BI BI

15D7 72D3 15D7 72D3

IN

15B7 72C3

BI BI

15D7 72D3 15D7 72D3

PP0V75_S3_MEM_VREFCA_A

27C1

BI BI

15D7 72D3 15D7 72D3

1

C3135
2.2UF
20% 6.3V CERM 402-LF

1

C3136
0.1UF
20% 10V CERM 402

BI BI

15D5 72C3 15D5 72C3

2

2

BI BI

15D7 72D3 15D7 72D3

OUT

21A4 21B3 29A5 39B8

BI IN

42D6 42D6

"Factory" (top) slot
=PP0V75_S0_MEM_VTT_A
8C7

1 1

A
2

C3140
2.2UF
20% 6.3V CERM 402-LF 2

R3140
10K
5% 1/16W MF-LF 402

1

R3141
10K
5% 1/16W MF-LF 402 1

DDR3 SO-DIMM Connector A C3150
2.2UF
2 20% 6.3V CERM 402-LF 2 1

C3151
2.2UF
20% 6.3V CERM 402-LF

SYNC_MASTER=BEN

SYNC_DATE=06/30/2008

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

A

2

516-0201
SPD ADDR=0xA0(WR)/0xA1(RD)

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

REV.
C

D
APPLE INC.
SCALE NONE

SHT
31

OF
109

8

7

6

5

4

3

2

1

8
Page Notes
Power aliases required by this page: - =PP1V5_S0_MEM_B - =PP1V5_S3_MEM_B - =PP0V75_S0_MEM_VTT_B - =PPSPD_S0_MEM_B (2.5 - 3.3V) Signal aliases required by this page: - =I2C_SODIMMB_SCL - =I2C_SODIMMB_SDA

7
8D3

6
=PP1V5_S3_MEM_B

5

4

3

2

1

DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)
1

C3200
10UF
20% 6.3V X5R 603

1

C3201
10UF
20% 6.3V X5R 603

1

C3210
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3211
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3212
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3213
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3214
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3215
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3216
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3217
0.1UF
20% 0204-1

2

2

2

2

2

2

2

2

2

2 6.3V X6S-CERM

D

BOM options provided by this page:
27C1

PP0V75_S3_MEM_VREFDQ_B

(NONE)

D
1

C3230
2.2UF
20% 6.3V CERM 402-LF

1

C3231
0.1UF
20% 10V CERM 402

2

2

1

72B3 15A1

IN

MEM_B_CKE<0>

73 75 77

KEY

72B3 15C1

IN

MEM_B_BA<2> MEM_B_A<12> MEM_B_A<9> MEM_B_A<8> MEM_B_A<5> MEM_B_A<3> MEM_B_A<1> MEM_B_CLK_P<0> MEM_B_CLK_N<0> MEM_B_A<10> MEM_B_BA<0> MEM_B_WE_L MEM_B_CAS_L MEM_B_A<13> MEM_B_CS_L<1>

79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127

72B3 15C1 72B3 15C1

IN IN

72B3 15C1 72B3 15B1

IN IN

72B3 15B1 72B3 15B1

IN IN

72C3 15B1

IN IN

C

72C3 15B1

72B3 15C1 72B3 15C1

IN IN

72B3 15C1 72B3 15C1

IN IN

72B3 15C1 72B3 15B1

IN IN

72B3 15C3 72B3 15C3

BI BI

MEM_B_DQ<37> MEM_B_DQ<32> MEM_B_DQS_N<4> MEM_B_DQS_P<4> MEM_B_DQ<35> MEM_B_DQ<39> MEM_B_DQ<45> MEM_B_DQ<41> MEM_B_DM<5> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<53> MEM_B_DQ<49> MEM_B_DQS_N<6> MEM_B_DQS_P<6> MEM_B_DQ<55> MEM_B_DQ<54> MEM_B_DQ<56> MEM_B_DQ<58> MEM_B_DM<7> MEM_B_DQ<61> MEM_B_DQ<60> MEM_B_SA<0>

129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

72A3 15D1 72A3 15D1

BI BI

72B3 15C3 72B3 15C3

BI BI

72B3 15C3 72B3 15C3

BI BI

72B3 15B3

IN

B

72B3 15D3 72B3 15D3

BI BI

72B3 15D3 72B3 15D3

BI BI

72A3 15D1 72A3 15D1

BI BI

72B3 15D3 72B3 15D3

BI BI

72B3 15D3 72B3 15D3

BI BI

1

R3240
10K
5% 1/16W MF-LF 402

72B3 15B3

IN

72B3 15D3 72B3 15D3

BI BI

2

8B5

=PPSPD_S0_MEM_B MEM_B_SA<1>

CKE0 CKE1 VDD VDD NC A15 A14 BA2 VDD F-RT-BGA3 VDD A11 A12/BC* A9 A7 VDD VDD A8 A6 A5 A4 VDD VDD A3 A2 A1 A0 VDD VDD CK1 CK0 CK0* CK1* VDD VDD A10/AP BA1 RAS* BA0 VDD VDD S0* WE* CAS* ODT0 VDD VDD ODT1 A13 S1* NC VDD VDD TEST VREFCA VSS VSS DQ36 DQ32 DQ37 DQ33 VSS VSS DQS4* DM4 DQS4 VSS VSS DQ38 DQ34 DQ39 DQ35 VSS DQ44 VSS DQ40 DQ45 DQ41 VSS VSS DQS5* DM5 DQS5 VSS VSS DQ42 DQ46 DQ47 DQ43 VSS VSS DQ52 DQ48 DQ53 DQ49 VSS VSS DQS6* DM6 DQS6 VSS VSS DQ54 DQ50 DQ55 DQ51 VSS VSS DQ60 DQ56 DQ61 DQ57 VSS DQS7* VSS DM7 DQS7 VSS VSS DQ58 DQ62 DQ59 DQ63 VSS VSS EVENT* SA0 VDDSPD SDA SA1 SCL VTT VTT

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212

MEM_B_CKE<1> MEM_B_A<15> MEM_B_A<14> MEM_B_A<11> MEM_B_A<7> MEM_B_A<6> MEM_B_A<4> MEM_B_A<2> MEM_B_A<0> MEM_B_CLK_P<1> MEM_B_CLK_N<1> MEM_B_BA<1> MEM_B_RAS_L MEM_B_CS_L<0> MEM_B_ODT<0> MEM_B_ODT<1>

IN

15A1 72B3

72B3 15B3 72B3 15B3

BI BI

MEM_B_DQ<1> MEM_B_DQ<0> MEM_B_DM<0> MEM_B_DQ<3> MEM_B_DQ<6> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQS_N<1> MEM_B_DQS_P<1> MEM_B_DQ<15> MEM_B_DQ<10> MEM_B_DQ<20> MEM_B_DQ<17> MEM_B_DQS_N<2> MEM_B_DQS_P<2> MEM_B_DQ<22> MEM_B_DQ<19> MEM_B_DQ<24> MEM_B_DQ<28> MEM_B_DM<3> MEM_B_DQ<26> MEM_B_DQ<31>

3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

IN IN

9D2 15C1 72B3 72B3 15A3

J3200
DDR3-SODIMM
(2 OF 2)

IN

IN IN

15C1 72B3 15C1 72B3

72B3 15B3 72B3 15B3

BI BI

IN IN

15B1 72B3 15B1 72B3

72B3 15B3 72B3 15B3

BI BI

IN IN

15B1 72B3 15B1 72B3

72A3 15D1 72A3 15D1

BI BI

IN IN

15B1 72C3 15B1 72C3

72B3 15B3 72B3 15B3

BI BI

IN IN

15C1 72B3 15C1 72B3

72B3 15C3 72B3 15B3

BI BI

IN IN

15B1 72B3 15B1 72B3

72A3 15D1 72A3 15D1

BI BI

IN

15B1 72B3

72B3 15C3 72B3 15B3

BI BI

72B3 15C3 72B3 15C3

BI BI

MEM_B_DQ<36> MEM_B_DQ<33> MEM_B_DM<4> MEM_B_DQ<38> MEM_B_DQ<34> MEM_B_DQ<40> MEM_B_DQ<44> MEM_B_DQS_N<5> MEM_B_DQS_P<5> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<52> MEM_B_DQ<48> MEM_B_DM<6> MEM_B_DQ<51> MEM_B_DQ<50> MEM_B_DQ<63> MEM_B_DQ<59> MEM_B_DQS_N<7> MEM_B_DQS_P<7> MEM_B_DQ<62> MEM_B_DQ<57> MEM_EVENT_L =I2C_SODIMMB_SDA =I2C_SODIMMB_SCL

BI BI

15C3 72B3 15C3 72B3 72B3 15B3

IN

IN

15B3 72B3

72B3 15C3 72B3 15C3

BI BI

BI BI

15C3 72B3 15C3 72B3

VREFDQ VSS VSS DQ4 DQ5 DQ0 CRITICAL DQ1 VSS VSS DQS0* DM0 DQS0 F-RT-BGA3 VSS VSS DQ2 DQ6 DQ3 DQ7 VSS VSS DQ8 DQ12 DQ9 DQ13 VSS VSS DQS1* DM1 DQS1 RESET* VSS VSS DQ14 DQ10 DQ11 DQ15 VSS VSS DQ16 DQ20 DQ17 DQ21 VSS VSS DQS2* DM2 DQS2 VSS DQ22 VSS DQ18 DQ23 VSS DQ19 VSS DQ28 DQ29 DQ24 VSS DQ25 DQS3* VSS DM3 DQS3 VSS VSS DQ26 DQ30 DQ27 DQ31 VSS VSS

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQS_N<0> MEM_B_DQS_P<0> MEM_B_DQ<7> MEM_B_DQ<2> MEM_B_DQ<12> MEM_B_DQ<9> MEM_B_DM<1> MEM_RESET_L MEM_B_DQ<8> MEM_B_DQ<11> MEM_B_DQ<16> MEM_B_DQ<21> MEM_B_DM<2> MEM_B_DQ<18> MEM_B_DQ<23> MEM_B_DQ<29> MEM_B_DQ<25> MEM_B_DQS_N<3> MEM_B_DQS_P<3> MEM_B_DQ<30> MEM_B_DQ<27>

BI BI

15B3 72B3 15B3 72B3

J3200
DDR3-SODIMM
(1 OF 2)

BI BI

15D1 72A3 15D1 72A3

BI BI

15B3 72B3 15B3 72B3

BI BI

15B3 72B3 15B3 72B3

IN IN

15A3 72B3 28C2 30C3

BI BI

15B3 72B3 15B3 72B3

C

BI BI

15B3 72B3 15C3 72B3

IN

15B3 72B3

BI BI

15B3 72B3 15C3 72B3

BI BI

15C3 72B3 15C3 72B3

BI BI

15D1 72A3 15D1 72A3

BI BI

15C3 72B3 15C3 72B3

KEY

BI BI

15C3 72B3 15C3 72B3

516S0706

BI BI

15D1 72A3 15D1 72A3

BI BI

15C3 72B3 15C3 72B3

B
DDR3 GROUND RETURN CAPS (MCP SIDE)
8B7

BI BI

15D3 72B3 15D3 72B3

=PP1V5_S0_MEM_MCP

IN

15B3 72B3

1

C3222
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3223
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3224
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3225
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3226
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3227
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3228
0.1UF
20% 6.3V X6S-CERM 0204-1

1

C3229
0.1UF
20% 0204-1

BI BI

15D3 72B3 15D3 72B3

2

2

2

2

2

2

2

2 6.3V X6S-CERM

PP0V75_S3_MEM_VREFCA_B

27C1

BI BI

15D3 72B3 15D3 72B3

1

C3235
2.2UF
20% 6.3V CERM 402-LF

1

C3236
0.1UF
20% 10V CERM 402

BI BI

15D1 72A3 15D1 72A3

2

2

BI BI

15D3 72B3 15D3 72B3

OUT

21A4 21B3 28A5 39B8

BI IN

42D6 42D6

"Expansion" (bottom) slot
=PP0V75_S0_MEM_VTT_B
8C7

1 1

A
2

C3240
2.2UF
20% 6.3V CERM 402-LF 2

R3241
10K
5% 1/16W MF-LF 402

205 207 209 211

MTG PINS

DDR3 SO-DIMM Connector B
1

MTG PIN MTG PIN MTG PIN MTG PIN

MTG PIN
MTG PIN

C3250
2.2UF
20% 6.3V CERM 402-LF

1

C3251
2.2UF
20% 6.3V CERM 402-LF

SYNC_MASTER=BEN

SYNC_DATE=05/09/2008

MTG PIN
MTG PIN

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

A

2

2

516S0706
SIZE DRAWING NUMBER
051-7918

REV.
C

SPD ADDR=0xA2(WR)/0xA3(RD)

D
APPLE INC.
SCALE NONE

SHT
32

OF
109

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

D

DDR3 RESET Support
MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.
8D3

=PP1V5_S3_MEMRESET 3.3V input must be stable before before 1.5V starts to rise to avoid glitch on MEM_RESET_L. MEMRESET_HW
1

1

R3310
1K
5% 1/16W MF-LF 402

8A3

=PP3V3_S5_MEMRESET

C
MEMRESET_HW

R3305
20K
5% 1/16W MF-LF 402

2

C
MEM_RESET_L
OUT
28C2 29C2

MEMRESET_HW
6 2

MEMRESET_MCP
1

R3300 1
10K
5% 1/16W MF-LF 402

2

R3309
0
5% 1/16W MF-LF 402

MEM_RESET MEMRESET_HW
2 3

Q3305
MMDT3904-X-G
SOT-363-LF 1 2

MEM_RESET_RC_L MEMRESET_HW

5

Q3305
MMDT3904-X-G
SOT-363-LF 4

R3301 1
20K
5% 1/16W MF-LF 402

MEMRESET_HW
1

C3300
0.1UF
20% 10V CERM 402

2 2

16C3

IN

MCP_MEM_RESET_L

B

B

DDR3 Support

A

SYNC_MASTER=T18_MLB

SYNC_DATE=04/04/2008

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
SCALE NONE

SHT
33

OF
109

8

7

6

5

4

3

2

1

8
17C6 9C6

7
OUT

6

5

4

3

2

1

PCIE_MINI_PRSNT_L
3

D

Q3401
SSM6N15FEAPE
SOT563

4

S

G

5

AP_PWR_EN

IN

21A3 21C3 34C7

D
17C6

5V S3 WLAN FET
OUT

D

MINI_CLKREQ_L
6

MOSFET CHANNEL

FDC606P P-TYPE 26 mOhm @4.5V 0.8 A (EDP)

D

Q3401
SSM6N15FEAPE
SOT563

RDS(ON) LOADING

1

S

G

2

CRITICAL 518S0610

PLACEMENT_NOTE=Place close to J3401.

D

J3401
20347-325E-12
F-RT-SM
31

1

2

0.1uF

1
10%

2

0.1uF

10%

16V X5R 402

PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N

IN IN

17B3 73D3

C3430
PLACEMENT_NOTE=Place close to J3401.

C3422
0.1uF
20% 10V CERM 402

1

C3421
0.1uF
20% 10V CERM 402

1

1

C3420
10UF
20% 10V X5R 805

G

16V X5R 402

1

17B3 73D3

7D5 7C3

PP5V_WLAN
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

2

1

31A5

PP5V_WLAN_F
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

S

2

4

C3431

1000 mA peak 750 mA nominal max

0402-LF

5 6

FERR-120-OHM-1.5A

L3404

Q3450
FDC606P_G
SOT-6

=PP5V_S3_WLAN
1 MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

8C3

C3451
0.033UF
10% 16V X5R 402

1

R3451
10K
5% 1/16W MF-LF 402

2

2

2

C3450
0.1UF
1 10% 16V X5R 402 2

3

2

1 2 3 4
73D3 7D5 73D3 7D5

PCIE_MINI_D2R_P PCIE_MINI_D2R_N PCIE_MINI_R2D_P PCIE_MINI_R2D_N

OUT OUT

7D5 17B6 73D3 7D5 17B6 73D3

CRITICAL

AIRPORT
PLACEMENT_NOTE=Place close to J3401.

R3450
1

2

P5VWLAN_SS

100K
5% 1/16W MF-LF 402

2

PM_WLAN_EN_L

IN

34C6

L3401 90-OHM-100MA
DLP11S
SYM_VER-1

C

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

4
73D3 7D5 73D3

3

PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N

PLACEMENT_NOTE=Place close to Q3450.

C

IN

PCIE_CLK100M_MINI_CONN_P 7D5 PCIE_CLK100M_MINI_CONN_N
7C5

17C3 73D3

PLACEMENT_NOTE=Place close to Q3450.

1

2

IN

17C3 73D3

MINI_CLKREQ_Q_L PCIE_WAKE_L

PLACEMENT_NOTE=Place close to J3401.

OUT

7D5 17B6 23C5

NC NC
7D5

PP5V_S3_BTCAMERA_F I2C_ALS_SDA I2C_ALS_SCL

275 mA peak 206 mA nominal max
BI IN
42D1 42D1

L3405
2 0402-LF
1

1

=PP5V_S3_BTCAMERA
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

8C3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

FERR-120-OHM-1.5A

74C3 7D5 74C3

USB_CAMERA_CONN_P 7D5 USB_CAMERA_CONN_N

CRITICAL

CONN_USB2_BT_P CONN_USB2_BT_N
4

L3402 90-OHM
DLP0NS
SYM_VER-1

ALS CAMERA
USB_CAMERA_P USB_CAMERA_N
OUT OUT

C3452
0.1uF
20% 10V CERM 402

2

3

20D3 74C3

26 27 1 28 29 2
20D3 74C3

PLACEMENT_NOTE=Place close to J3401.

B

30

CRITICAL
32

L3403 90-OHM
DLP0NS
SYM_VER-1

BLUETOOTH
3

B
20D3 74C3

4

USB_BT_P USB_BT_N

BI

1

2
PLACEMENT_NOTE=Place close to J3401.

BI

20C3 74C3

PP5V_WLAN_F =PP3V3_S3_WLAN
8D3

31C3

1

R3453
33K
5% 1/16W MF-LF 402

74LVC1G17DRL
TC7SZ08AFEAPE 5 SOT665
7C5

U3402
SOT-553 4

5
2

A

2

WLAN_SMIT_BUF

2

MINI_RESET_CONN_L

4

Y

U3401
B

NC
1 3 1

WLAN_SMIT_RC
1

3

NC

C3453

1

R3454
62K
5% 1/16W MF-LF 402

Right Clutch Connector
SYNC_MASTER=YITE SYNC_DATE=04/22/2008

A

MINI_RESET_L

IN

26C1

1UF
10% 6.3V CERM 402 2
2

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
SCALE NONE

SHT
34

OF
109

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

D

CRITICAL

J3501
503219-0221

C
9C5

M-ST-SM 24

VENICE

C

23

OUT FC_CLKREQ_L

1 3

2 4 6 8 10 12 14 16 18 20 22

73D3 9C5

IN IN

73D3 9B5 73D3 9B5

IN IN

PCIE_FC_R2D_C_P PCIE_FC_R2D_C_N

PLACEMENT_NOTE=Place close to J3501. 73D3 C3573 VENICE 1 2 0.1uF 1 2 0.1uF 10% 16V X5R 402
10% 16V X5R 402

9C5

PCIE_CLK100M_FC_P PCIE_CLK100M_FC_N

5 7 9

NC
=PP3V3_FC_CON
8B5

PCIE_FC_R2D_P 73D3 PCIE_FC_R2D_N
73D3

11 13 15

NC NC
=PP1V5_FC_CON
8B7

C3572 VENICE 73D3 PLACEMENT_NOTE=Place close to J3501.

9B5

OUT PCIE_FC_D2R_P OUT PCIE_FC_D2R_N

17 19 21

NC
FC_PRSNT_L FC_RESET_L
OUT OUT
9C5 26C1

73D3 9B5

25 26

Venice Connector

B

B

VENICE CONNECTOR

A

SYNC_MASTER=YITE

SYNC_DATE=03/13/2008

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
SCALE NONE

SHT
35

OF
109

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

=PP1V05_ENET_PHY

8B1

D
8B1

C3710
0.1UF =PP3V3_ENET_PHY
10% 16V X5R 402

1

C3711
0.1UF
10% 16V X5R 402

1

1

(221mA typ - 1000base-T) ( 7mA typ - Energy Detect) WF: Marvell numbers, update for Realtek

D

CRITICAL
2

2

L3715
FERR-120-OHM-1.5A
0402-LF

(43mA typ - 1000base-T) (19mA typ - Energy Detect) WF: Marvell numbers, update for Realtek

1

1

C3700
0.1UF
10% 16V X5R 402

1

C3701
0.1UF
10% 16V X5R 402

1

C3702
0.1UF
10% 16V X5R 402

2

CRITICAL

L3705
FERR-120-OHM-1.5A
0402-LF

PP1V05_ENET_PHYAVDD

2

2

2

C3714
0.1UF
10% 16V X5R 402

1

C3715
0.1UF
10% 16V X5R 402

1

C3716
0.1UF
10% 16V X5R 402

1

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

2

2

2

2

PP3V3_ENET_PHYAVDD
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V 1

C3705
0.1UF
10% 16V X5R 402

1

C3706
0.1UF
10% 16V X5R 402

=PP3V3_ENET_PHY_VDDREG

9D2

2

2

If internal switcher is used, must place 1x 22uF & 1x 0.1uF caps within 5mm of U3700 pins 44 & 45. NOTE: VDDREG rise time must be >1ms to avoid damage to switcher. 6 41 15 21 37 44 45 28 36 10 40

R3750 1
4.7K
5% 1/16W MF-LF 402

1

R3751
4.7K
5% 1/16W MF-LF 402

R3752 1
4.7K
5% 1/16W MF-LF 402

NO STUFF

3

=RTL8211_REGOUT

9D2

AVDD33

DVDD33

VDDREG

DVDD10

R3725
4.7K
5% 1/16W MF-LF 402

AVDD10

FB10

R3720 1

1

C
R3796
75D3 18D3

10K Alias to =PP3V3_ENET_PHY for internal switcher. Alias to GND for external 1.05V supply.
9D2

2

2

2

If internal switcher is used, must place inductor within 5mm of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor. If internal switcher is not used, VDDREG and REGOUT can float.

5% 1/16W MF-LF 402 2

C

2

CRITICAL 39 ENSWREG

IN

=RTL8211_ENSWREG

U3700
RTL8251CA-VB-GR
TQFP

REGOUT

48

IN

ENET_CLK125M_TXCLK

1

0

2

75D3

ENET_CLK125M_TXCLK_R

22

TXC

RXC

19

75D3

ENET_CLK125M_RXCLK_R

R3790 R3791 R3792 R3793 R3794 R3795

22

1

2 5% 1/16W MF-LF 402

ENET_CLK125M_RXCLK

OUT

18D6 75D3

5% 1/16W 402 MF-LF

75D3 18D3 75D3 18D3 75D3 18D3 75D3 18D3

IN IN IN IN

PLACE R3796 CLOSE TO U1400, PIN D24

ENET_TXD<0> ENET_TXD<1> ENET_TXD<2> ENET_TXD<3>

23 24 25 26

TXD[0] TXD[1] TXD[2] TXD[3]

RGMII/MII

RXD[0] RXD[1]/TXDLY RXD[2]/AN0 RXD[3]/AN1

14 16 17 18

75D3 75D3 75D3 75D3

ENET_RXD_R<0> ENET_RXD_R<1> ENET_RXD_R<2> ENET_RXD_R<3>

22 22 22 22

1 1 1 1

2 2 2 2 5% 5% 5% 5% 1/16W 1/16W 1/16W 1/16W MF-LF MF-LF MF-LF MF-LF 402 402 402 402

ENET_RXD<0> ENET_RXD<1> ENET_RXD<2> ENET_RXD<3>

OUT OUT OUT OUT

18D6 75D3 18D6 75D3 18D6 75D3 18D6 75D3

75C3 18D3

IN

ENET_TX_CTRL

27

TXCTL

RXCTL

13

75D3

ENET_RXCTL_R

22

1

2 5% 1/16W MF-LF 402

ENET_RX_CTRL

OUT

18D6 75D3

75D3 18D3 75D3 18C3

IN BI

ENET_MDC ENET_MDIO

30 31

MDC MDIO

MANAGEMENT

MDI+[0] MDI-[0] MDI+[1] MDI-[1] MDI+[2] MDI-[2]

1 2 4 5 8 9 11 12

ENET_MDI_P<0> ENET_MDI_N<0> ENET_MDI_P<1> ENET_MDI_N<1> ENET_MDI_P<2> ENET_MDI_N<2> ENET_MDI_P<3> ENET_MDI_N<3>

BI BI BI BI BI BI BI BI

35B7 75C3 35B7 75C3

R3724
75C3 18C3

35C7 75C3 35C7 75C3

IN

ENET_RESET_L

1

0
5% 1/16W MF-LF 402

2

RTL8211_PHYRST_L
1

29

PHYRSTB*

RESET MEDIA DEPENDENT

35C7 75C3 35C7 75C3

C3725
0.1UF
20% 10V CERM 402

RTL8211_RSET

46

ENET_RESET_L IS NOT ASSERTED WHEN WOL IS ACTIVE. HENCE, RC (C3725 AND R3725) ARE NOT STUFFED.

RSET

REFERENCE

NO STUFF

2

MDI+[3] MDI-[3]

35C7 75C3 35C7 75C3

B
R3730 1
2.49K
1% 1/16W MF-LF 402
75D3 34A3

TP_RTL8211_CLK125

32

CLK125 CLOCK LED0/PHYAD0 LED1/PHYAD1 LED2/RXDLY 34 35 38 NO STUFF RTL8211_PHYAD0 RTL8211_PHYAD1 RTL8211_RXDLY

B

IN

RTL8211_CLK25M_CKXTAL1 TP_RTL8211_CKXTAL2

42 43

CKXTAL1 CKXTAL2

LED GND 7 20 33 47

2

C3790
10PF
5% 50V CERM 402

1

R3755 1
4.7K
5% 1/16W MF-LF 402

R3756 1
4.7K
5% 1/16W MF-LF 402

1

R3757
4.7K
5% 1/16W MF-LF 402

2

2

2

2

Reserved for EMI per RealTek request.

Ethernet PHY (RTL8211CL)

A

SYNC_MASTER=SUMA

SYNC_DATE=05/23/2008

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

A

Configuration Settings:
SIZE DRAWING NUMBER
051-7918

REV.
C

PHYAD AN[1:0] RXDLY TXDLY

= = = =

01 11 0 0

(PHY Address 00001) (Full auto-negotiation) (RXCLK transitions with data) (No TXCLK Delay)

D
APPLE INC.
SCALE NONE

SHT
37

OF
109

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

3.3V ENET FET
@ 2.5V Vgs: Rds(on) = 90mOhm max I(max) = 1.7A (85C)
8A3

CRITICAL

Q3810
NTR4101P
SOT-23-HF

=PP3V3_S5_P3V3ENETFET
2

=PP3V3_ENET_FET

8B2

S

D

3

D

D

R3800 1
10K
5% 1/16W MF-LF 402

1

C3811
0.033UF
10% 16V X5R 402
1

G

2
2

R3810
P3V3ENET_EN_L 100K
1 5% 1/16W MF-LF 402 2

C3810
0.01UF
2 1

P3V3ENET_SS

Q3801
SSM6N15FEAPE
SOT563

D

3

10% 16V CERM 402

5

G

S

4

9D2

IN

=P3V3ENET_EN

MOBILE: Recommend aliasing PM_SLP_RMGT_L and =P3V3ENET_EN. Nets separated on ARB for alternate power options.

WLAN Enable Generation
"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0")) NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal. PM_WLAN_EN_L
OUT
31C1

C
Q3805
SSM6N15FEAPE
SOT563

Pull-up is with power FET.

D

1.05V ENET FET
8B3

C
1.8V Vgs

6

=PP1V05_ENET_P1V05ENETFET

2

G

S

1

C3840
AC_OR_S0_L
0.1UF

1 3

31D5 21C3 21A3

IN

AP_PWR_EN

Q3805
SSM6N15FEAPE
SOT563

D

3

6

D

Q3801
SSM6N15FEAPE
SOT563

8A3

=PP3V3_S5_P1V05ENETFET

R3840
100K
1 5% 1/16W MF-LF 402 2

20% 10V CERM 402

CRITICAL

2

D

Q3840
1

P1V05ENET_SS

G S

SI2312BDS
SOT23

R3842 1
5

Q3841
SSM6N15FEAPE
SOT563

D

6

2

=PP1V05_ENET_FET

G

S

4

1

S

G

2

69.8K
1% 1/16W MF-LF 402

8B2

40B2 39D5 21C7

IN

SMC_ADAPTER_EN

2

R3841
68D8 64D5 41A5 39C5 21C3 7C3

2

G

S

1 1

C3841
0.01UF
10% 16V CERM 402

IN

PM_SLP_S3_L

P1V05ENET_EN_L

10K
1 1% 1/16W MF-LF 402 2 2

Q3841
SSM6N15FEAPE
SOT563

D

3

P1V05ENET_EN_L_RC

5

G

S

4

B

9D2

IN

=P1V05ENET_EN

B

Non-ARB: Recommend aliasing PM_SLP_RMGT_L and =P1V05ENET_EN. Nets separated on ARB for alternate power options.

RTL8211 25MHz Clock
A
NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered. Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.

Ethernet & AirPort Support
SYNC_MASTER=SUMA SYNC_DATE=07/01/2008

NOTICE OF PROPRIETARY PROPERTY

A

R3895
75D3 18C3

IN

MCP_CLK25M_BUF0_R

22
1 2

RTL8211_CLK25M_CKXTAL1

OUT

33B6 75D3

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

5% 1/16W MF-LF 402 PLACEMENT_NOTE=Place close to U1400

REV.
C

D
APPLE INC.
SCALE NONE

SHT
38

OF
109

8

7

6

5

4

3

2

1

8
- COPY THIS PAGE FROM K36 CSA.39

7

6

5

4

3

2

1

D

D

PLACE ONE CAP EACH NEAR PINS 3 AND 4 OF T3901 AND T3902

ENET_CONN_CTAP
1

C3900
0.1UF

1

C3901
0.1UF

1

C3902
0.1UF

1

C3903
0.1UF

10% 16V 2 X5R 402

10% 16V 2 X5R 402

10% 16V 2 X5R 402

10% 16V 2 X5R 402

ETHERNET CONNECTOR
CRITICAL

CRITICAL
ENET_MDI_P<1> ENET_MDI_N<1>
1 2 3
TX

J3900
RJ45-M97-3
F-RT-TH

T3901 SM

75C3 33B3

BI

12 11 10

75C3

ENET_MDI_TRAN_P<1> ENET_MDI_TRAN_N<1>

9 10

75C3 33B3

BI

75C3

ENET_CENTER_TAP<1> 1

R3903 75 2
MF-LF 402 MF-LF 402
75C3

1 2 3 4 5 6

1% 1/16W 9 8 7
RX

TLA-6T213HF

C
75C3 33B3

4

R3902 75 2 ENET_CENTER_TAP<3> 1
1% 1/16W

C

BI

ENET_MDI_P<3> ENET_MDI_N<3>

5 6

ENET_MDI_TRAN_P<3> ENET_MDI_TRAN_N<3>

7 8

75C3 33B3

BI

75C3

11 12

CRITICAL
ENET_MDI_N<2> ENET_MDI_P<2>
1 2 3
TX

T3902 SM

514-0636
12 11 10 ENET_CENTER_TAP<2> 1 1% 1/16W 9 8 7
75C3

75C3 33B3

BI

ENET_MDI_TRAN_N<2> ENET_MDI_TRAN_P<2>

75C3 33B3

BI

75C3

R390175 2
MF-LF 402

TLA-6T213HF
4
75C3 33B3

ENET_CENTER_TAP<0> 1

R390075 2
MF-LF 402
75C3

1% 1/16W
BI

ENET_MDI_N<0> ENET_MDI_P<0>

5 6
RX

ENET_MDI_TRAN_N<0> ENET_MDI_TRAN_P<0>

75C3 33B3

BI

75C3

ENET_BOB_SMITH_CAP
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

CRITICAL
1

C3910
1000PF

B

10% 2KV 2 CERM 1206

B

ETHERNET CONNECTOR

A

SYNC_MASTER=SUMA

SYNC_DATE=04/04/2008

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
SCALE NONE

SHT
39

OF
109

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

ODD Power Control
CRITICAL

Q4590
FDC606P_G
6 2 5
8D5

=PP5V_S0_ODD
4

SOT-6

7C3 7B7

PP5V_SW_ODD

S

D
NOTE: 3.3V must be S0 if 5V is S3 or S5 to ensure the drive is unpowered in S3/S5.
36C7 8C5

D

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V

100K
5% 1/16W MF-LF 402

=PP3V3_S0_ODD

R4595
ODD_PWR_EN_LS5V_L
1

10% 10V 2 CERM 402

0.068UF

3

G

R4596
100K 2
5% 1/16W MF-LF 402

1

C4595

C4596
0.01UF
1 2 10% 16V CERM 402

R4597
100K
5% 1/16W MF-LF 402

ODD_PWR_SS

Q4596
SSM6N15FEAPE
SOT563

D 6

ODD_PWR_EN
2

G

Q4596
SSM6N15FEAPE
SOT563

D 3

S 1

5
21B3

G

S 4

IN

ODD_PWR_EN_L

1

D

C

SATA ODD Port
FL4520 90-OHM-100MA
DLP11S CRITICAL 3
SYM_VER-1

C
PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79 PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520
1 2

4

73A3

SATA_ODD_R2D_UF_P

C4521
CERM 402

SATA_ODD_R2D_C_P

IN

20D6 73A3

0.01UF
CRITICAL 55560-0168
M-ST-SM-LF 2 4
36D5 8C5

10% 16V 2

J4500
1 3 5 7 9

2

1

73A3

SATA_ODD_R2D_UF_N

1

C4520
CERM 402

SATA_ODD_R2D_C_N

IN

20D6 73A3

0.01UF
PLACEMENT_NOTE=Place FL4520 close to J4500
73A3 7B7 73A3 7C5

10% 16V

=PP3V3_S0_ODD

6 8 10

SATA_ODD_R2D_P 7B7 SATA_ODD_R2D_N SATA_ODD_D2R_C_N SATA_ODD_D2R_C_P

73A3 7B7 73A3 7B7

R45901
5% 1/16W MF-LF 402 2

12 14 16

11 13 15

33K

PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500 PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526

90-OHM-100MA DLP11S
SYM_VER-1

FL4525
CRITICAL 3 SATA_ODD_D2R_N OUT
20D6 73A3

C4526 1
0.01UF

2

73A3

SATA_ODD_D2R_UF_N

4

10% 16V CERM 402 2
73A3

516S0617
39B8 7B7

C4525 1
0.01UF

SATA_ODD_D2R_UF_P

1

2

SATA_ODD_D2R_P

OUT

20D6 73A3

OUT

SMC_ODD_DETECT

10% 16V CERM 402

Indicates disc presence

PLACEMENT_NOTE=Place FL4525 close to J4500

B
CRITICAL

B
C4501
0.1UF
CRITICAL

1

1

C4502
0.1UF
PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501 PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501

20374020E31
F-ST-SM 21

J4501

20% 2 10V CERM 402

FERR-70-OHM-4A
1 2 3 4 5 6 7 8 9 10 11 12 13 14
73A3 7C5 CRITICAL 7C5 7C3

L4500
0603

20% 2 10V CERM 402

SATA HDD Port
2

PP5V_S0_HDD_FLT

1

2

=PP5V_S0_HDD

8D5

PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501

FL4501 90-OHM-100MA
DLP11S
SYM_VER-1

PLACEMENT_NOTE=Place C4510 close to MCP79 PLACEMENT_NOTE=Place C4511 next to C4510
4
73A3

NC NC
73A3 7C5

3

SATA_HDD_R2D_UF_P

C4510 1
0.01UF

SATA_HDD_R2D_C_P

IN

20D6 73A3

10% 16V CERM 402 2

SATA_HDD_R2D_P
2 1
73A3

NC
73A3 7C5

SATA_HDD_R2D_UF_N

C4511 1
0.01UF
90-OHM-100MA DLP11S
SYM_VER-1

SATA_HDD_R2D_C_N

IN

20D6 73A3

SATA_HDD_R2D_N PLACEMENT_NOTE=Place FL4501 close to J4501 SATA_HDD_D2R_C_N SATA_HDD_D2R_C_P

10% 16V CERM 402

FL4502
CRITICAL

NC
73A3 7C5

C4515 1
0.01UF

2 10% 16V 2 10% 16V

73A3

SATA_HDD_D2R_UF_N

4

3

SATA_HDD_D2R_N

OUT

20D6 73A3

CERM 402
73A3

SATA Connectors
SYNC_MASTER=CHANGZHANG SYNC_DATE=04/14/2008

A

15 16 17 18 19 20

NC NC

C4516 1
0.01UF

SATA_HDD_D2R_UF_P

1

2

SATA_HDD_D2R_P

OUT

20D6 73A3

CERM 402

PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

A

PLACEMENT_NOTE=Place C4515 next to C4516 PLACEMENT_NOTE=Place C4516 close to J4501

22

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

REV.
C

518S0654
APPLE INC.

D
SCALE NONE

SHT
45

OF
109

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

D

Port Power Switch
CRITICAL

USB PORT A (FRONT PORT)
PLACEMENT_NOTE=NEAR J4600 CRITICAL

U4690

L4605
FERR-220-OHM-2.5A
7

C
20C2 20C2

TPS2064DGN
8C3

=PP5V_S3_EXTUSB USB_EXTA_OC_L USB_EXTB_OC_L

2 8 3

IN OC1* EN1 OC2* EN2

OUT1

PP5V_S3_RTUSB_A_ILIM
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

1 0603

2

PP5V_S3_RTUSB_A_F
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

MSOP
OUT2 6

C
CRITICAL

OUT

PP5V_S3_RTUSB_B_ILIM
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

C4605
0.01uF
20% 16V CERM 402

1

OUT

5 4

PLACEMENT_NOTE=NEAR J4600 CRITICAL
2

J4600
USB
F-RT-TH-M97-4 5 6

L4600 90-OHM
DLP0NS
SYM_VER-1

GND TPAD
1 9

USB_PWR_EN_R

NOSTUFF

CRITICAL

CRITICAL

74C3

USB_EXTA_MUXED_N

4

3

74C3

CONN_USB_EXTA_N

1 2

C4690
10UF
20% 6.3V X5R 603

1

1

C4691
0.1UF
20% 10V CERM 402

C4695
10UF
20% 6.3V X5R 603

1

1

C4696
100UF

C4617
10UF
20% 6.3V X5R 603

1

1

C4616
100UF
74C3

USB_EXTA_MUXED_P

1

2

74C3

CONN_USB_EXTA_P

3 4
2 5 3 4

2

2

2

20% 2 6.3V POLY-TANT CASE-B2-SM

2

2

20% 6.3V POLY-TANT CASE-B2-SM

NC IO NC IO

We can remove C4690 later if the output cap of the 5V_S5 regulator is close enough.
6 VBUS

7 8

R4690
64C6

IN

=USB_PWR_EN

1

0
5% 1/16W MF-LF 402

2

CAN NOSTUFF C4696 AND C4616 AFTER CHARACTERIZATION

1 GND

514-0638
D4600

NOSTUFF 1

STUFF R4691 IF USING TPS2060(ACTIVE LOW ENABLE) STUFF R4690 IF USING TPS2064(ACTIVE HIGH ENABLE)

R4691
0
5% 1/16W MF-LF

RCLAMP0502N
SLP1210N6

PLACEMENT_NOTE=NEAR J4610 CRITICAL CRITICAL We can add protection to 5V if we want, but leaving NC for now

2 402

L4615

FERR-220-OHM-2.5A
1 0603 2

PP5V_S3_RTUSB_B_F
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

Place L4600 and L4605 at connector pin

B

USB/SMC Debug Mux
8D1

1

C4615
0.01uF
20% 16V CERM 402

B
CRITICAL

2

=PP3V42_G3H_SMCUSBMUX SMC_DEBUG_YES
1 1

J4610
USB

C4650
0.1UF
20% 10V CERM 402

R4650
10K
5% 1/16W MF-LF 402
74B3 20C3

PLACEMENT_NOTE=NEAR J4610 CRITICAL

F-RT-TH-M97-4 5 6

2 2

L4610 90-OHM
DLP0NS
SYM_VER-1

1 3
74B3 74B3

BI

USB_EXTB_N

9

4

41C3 40B2 39C5 39B8 41C5 40C2 39C5 39B8

IN OUT

SMC_RX_L SMC_TX_L USB_EXTA_P USB_EXTA_N

5 M+ 4 M7 D+ 6 D-

VCC SMC_DEBUG_YES

CONN_USB_EXTB_N CONN_USB_EXTB_P

2 3 4

PI3USB102ZLE
74C3 20D3 74C3 20D3

U4650
TQFN

Y+ 1 Y- 2

74B3 20C3

BI

USB_EXTB_P

1

2 7
2 6 VBUS 1 GND 5 3 4

8

BI BI

NC IO NC IO

CRITICAL
SEL 10 GND 3 USB_DEBUGPRT_EN_L SEL=0 Choose SMC SEL=1 Choose USB
IN
39B8

514-0638

8

OE*

D4610
RCLAMP0502N
SLP1210N6

SMC_DEBUG_NO

CRITICAL

External USB Connectors
SYNC_MASTER=YUAN.MA SYNC_DATE=01/18/2008

A

R4651
1

0
5% 1/16W MF-LF 402

2

NOTICE OF PROPRIETARY PROPERTY
SMC_DEBUG_NO

A

R4652
1

USB PORT B (BACK PORT)

0
5% 1/16W MF-LF 402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

2

REV.
C

D
APPLE INC.
SCALE NONE

SHT
46

OF
109

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D
38B4 8C3 =PP5V_S3_IR

D

1

C4801
0.1UF
10% 16V X7R-CERM 402

2

VDD
74B3 20D3 74B3 20D3

BI BI

USB_IR_P DIFFERENTIAL_PAIR=USB2_IR DIFFERENTIAL_PAIR=USB2_IR USB_IR_N IR_VREF_FILTER

14 15 18 20

16

1

C4803
1UF
10% 10V X5R 402-1

23 24 25 26

2

P1_0/D+ P1_1/DP1_2/VREG P1_3/SSEL P1_4/SCLK P1_5/SMOSI P1_6/MISO P1_7

P0_0 P0_1 P0_2/INT0 P0_3/INT1 P0_4/INT2 P0_5/TIO0 P0_6/TIO1 P0_7 P2_0 P2_1

7 6 5 4 3 2 1 32 IR_RX_OUT_RC

R4800
1

100
5% 1/16W MF-LF 402

2

IR_RX_OUT

IN

7A7 38B4

U4800
21 22

C
27 28 29 30 31

P3_0 P3_1

CY7C63833
QFN CRITICAL OMIT

9 8

1

C4804
0.001UF
10% 50V CERM 402

2

C

P/N 338S0375
NC NC

10 11 12 17 19

THRM_PAD VSS
33 13

CYPRESS ’ENCORE II’ USB CONTROLLER

B

CRITICAL

B
R4805
1
1/16W
7A7 PP3V42_G3H_LIDSWITCH_R 7A7

FF18-6A-R11AD-B-3H
F-RT-SM 1 2 3 4 5 6
7A7 7A7

J4800

10
5% MF-LF

PLACE R4805 NEAR J4800 PLACE R4806 NEAR J4800 PLACE R4807 NEAR J4800 PLACE R4808 NEAR J4800

2
402

=PP3V42_G3H_LIDSWITCH

8D1

R4806
1
1/16W 5% MF-LF

PP5V_S3_IR_R

10

2
402

=PP5V_S3_IR

8C3 38D7

R4807
1

SMC_LID_R SYS_LED_ANODE_R

100
5% MF-LF

2
402

R4808
1
1/16W 5% MF-LF

1/16W

4.7

2
402

SMC_LID 39B5 SYS_LED_ANODE 40A6 IR_RX_OUT

40C2 47A5

7A7 38C4

518S0692

1

C4805
0.1UF
10% 16V X7R-CERM 402

1

C4806
0.1UF
10% 16V X7R-CERM 402

1

C4807
0.001UF
10% 50V CERM 402

1

C4808
0.001UF
10% 50V CERM 402

PLACE PLACE PLACE PLACE

C4805 C4806 C4807 C4808

NEAR NEAR NEAR NEAR

J4800 J4800 J4800 J4800

2

2

2

2

Front Flex Support

A

SYNC_MASTER=YUAN.MA

SYNC_DATE=05/28/2008

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
SCALE NONE

SHT
48

OF
109

8

7

6

5

4

3

2

1

8
NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.

7

6

5

4

3

2

1

40C6 7C2 49D7 40D8 40C7 40C1 8D1

PP3V3_S5_AVREF_SMC =PP3V3_S5_SMC

D
C4902
22UF
1 1

D
C4903
0.1UF
2 2 20% 10V CERM 402 2 1

C4904
0.1UF
20% 10V CERM 402

1

C4905
0.1UF
20% 10V CERM 402

1

C4906
0.1UF
20% 10V CERM 402

U4900
40D5 40D5 64A4 26B8 64B1

20% 6.3V CERM 805

2

2

OUT OUT IN IN

SMC_EXCARD_PWR_EN SMC_RSTGATE_L ALL_SYS_PWRGD RSMRST_PWRGD

21B7 60C7 23C5 21C7

OUT OUT OUT OUT

PM_RSMRST_L IMVP_VR_ON PM_PWRBTN_L ESTARLDO_EN

NC
SMC_PROCHOT_3_3_L SMC_BIL_BUTTON_L SMC_CPU_ISENSE SMC_CPU_VSENSE SMC_GPU_ISENSE SMC_GPU_VSENSE SMC_DCIN_ISENSE SMC_PBUS_VSENSE SMC_BATT_ISENSE SMC_NB_MISC_ISENSE SMC_WAKE_SCI_L
IN IN IN IN IN IN IN IN IN IN OUT
40D1 56B1

C4920
0.1UF
20% 10V CERM 402

1

E1

NC

B12 A13 A12 B13 D11 C13 C12 D10 D13 E11 D12 F11 E13 E12 F13 E10 A9 D9 C8 B7 A8 D8 D7 D6

P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 P50 P51 P52

H8S2117
LGA-HF (1 OF 3) OMIT

P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 P73 P74 P75 P76 P77 P80 P81 P82 P83 P84 P85 P86 P90 P91 P92 P93 P94 P95 P96 P97

L13 K12 K11 J12 K13 J10 J11 H12 N10 M11 L10 N11 N12 M13 N13 L12 A7 B6 C7 D5 A6 B5 C6 J4 G3 H2 G1 H4 G4 F4 F1

SMC_PM_G2_EN

PLACEMENT_NOTE=Place C4907 close to U4900 pin F1
OUT
7C3 64D8

NC NC NC
SMC_ADAPTER_EN
OUT
21C7 34B7 40B2

R4999
1

SMC_VCL PP3V3_S5_SMC_AVCC M12 B1 M1 H10 L11
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

4.7
5% 1/16W MF-LF 402

2

C4907
0.47UF
10% 6.3V CERM-X5R 402

1

2

2

AVCC

VCC

VCL AVREF NC E5

40D5

44B1 43D6 40B2 40D5 44B1 43B4 44A4

NC NC NC
40D5

PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15 PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15

H8S2117
LGA-HF (3 OF 3) OMIT

U4900

R4909 1
NC
10K
5% 1/16W MF-LF 402 2

1

R4901
10K

5% 1/16W MF-LF 2 402

SMC_P24

NC
40D5

41D3 40D6

IN
40A6

SMC_RESET_L SMC_XTAL SMC_EXTAL

D3 A3 A2

RES* XTAL EXTAL

MD1 MD2

D1 H1

SMC_MD1 SMC_KBC_MDE

IN

41C5

SMC_P26

NC
74C3 41D5 19B3 74C3 41D5 19B3 74C3 41D3 19B3

40B2 40A6 21C7 23C5

NMI

E3

SMC_NMI

IN

41C3

BI BI BI BI IN IN IN BI

C

74C3 41D3 19B3 74C3 41D5 19C3 26D1 74C3 26C1 41D3 19B7

D2 L3 F10 B11 C5

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L SMC_LRESET_L LPC_CLK33M_SMC LPC_SERIRQ

NC
PM_CLKRUN_L LPC_PWRDWN_L SMC_TX_L SMC_RX_L SMB_MGMT_CLK SMC_ONOFF_L SMC_BC_ACOK SMC_BS_ALRT_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L PM_CLK32K_SUSCLK SMB_0_S0_DATA
OUT IN OUT IN BI IN IN IN IN IN IN IN BI
19B7 41D5 19C3 41D3 37A8 39B8 40C2 41C5 37A8 39B8 40B2 41C3 42B5

ETRST AVSS VSS

H3 L9
1

SMC_TRST_L NO STUFF

IN

41D5

C

R4902
10K

1

R4998
10K

1

R4903
0

(OC)

XW4900
SM 2 1

40A3 40C2 40C7 47C3 40B2 40D5 56C1 7A7 40B2 56A8 7C3 21C3 34B7 41A5 64D5 68D8 7C3 21C3 40A2 64C8 40A2 26B1 74A3 42D5

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 2 402

NC
40D5 42B5 49B7

BI OUT

SMC_P41 SMB_MGMT_DATA SMS_ONOFF_L

(OC)

NC NC
40D5 48A6

OUT OUT OUT IN BI

SMC_GFX_THROTTLE_L SMC_SYS_KBDLED SMC_TX_L SMC_RX_L SMB_0_S0_CLK

D4 A5 B4 A1 C2 B2 C1 C3 G2 F3 E4

NOTE: P94 and P95 are shorted, P95 could be spare.

GND_SMC_AVSS

40B6 43B5 43C6 43D6 44A1 44A4 44B2 44B5 44C5 44D5

(OC)

41C5 40C2 39C5 37A8 41C3 40B2 39C5 37A8 42D5

(OC)

U4900
(DEBUG_SW_1) (DEBUG_SW_2)
26B3 37A6 29A5 28A5 21B3 21A4

B
56C2 40B2 23C5 21C7 23C5 21C7 36B7 7B7

SMC_PA0 SMC_PA1 PM_SYSRST_L OUT USB_DEBUGPRT_EN_L OUT MEM_EVENT_L BI 40A2 SMC_PA5 SYS_ONEWIRE BI PM_BATLOW_L OUT
40C2 40C2

(OC) (OC) (OC) (OC) (OC) (OC)

N3 N1 M3 M2 N2 L1 K3 L2 B8 C9 B9 A10 C10 B10 C11 A11 G11 G13 F12 H13 G10 G12 H11 J13 M10 N9 K10 L8 M9 N8 K9 L7

PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7

H8S2117
LGA-HF (2 OF 3) OMIT

PE0 PE1 PE2 PE3 PE4 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PH0 PH1 PH2 PH3 PH4 PH5

K1 J3 K2 J1 K4 K5 N5 M6 L5 M5 N4 L4 M4 M8 N7 K8 K7 K6 N6 M7 L6 E2 F2 J2 A4 B3 C4

SMC_CASE_OPEN SMC_TCK SMC_TDI SMC_TDO SMC_TMS

IN IN IN OUT IN

40B2 40B2 41D3 40B2 41D3 40B2 41D5 40B2 41D5

NC
SMC_SYS_LED SMC_LID
OUT IN
40A8 38B4 40C2 47A5

B
23B4

NC
OUT

40B2

SMC_RUNTIME_SCI_L SMC_ODD_DETECT IN 40C5 SMC_PB3 (See below) SMC_EXCARD_CP IN

NC NC
SMC_MCP_SAFE_MODE
OUT

NC NC NC
(OC) (OC) (OC) (OC) (OC) (OC) =SMC_SMS_INT SMB_BSA_DATA SMB_BSA_CLK SMB_A_S3_DATA SMB_A_S3_CLK SMB_B_S0_DATA SMB_B_S0_CLK SMC_PROCHOT SMC_THRMTRIP SMC_PH2 ALS_GAIN
IN BI BI BI BI BI BI OUT OUT
40C2 40B5 42C5 42C5 42D3 42D3 42C3 42C3

NC
40C5 40B2

IN IN OUT OUT OUT OUT IN IN IN IN IN IN IN IN IN IN IN IN

SMC_EXCARD_OC_L SMC_GFX_OVERTEMP_L SMC_FAN_0_CTL SMC_FAN_1_CTL SMC_FAN_2_CTL SMC_FAN_3_CTL SMC_FAN_0_TACH SMC_FAN_1_TACH SMC_FAN_2_TACH SMC_FAN_3_TACH SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS SMC_ANALOG_ID SMC_NB_CORE_ISENSE SMC_NB_DDR_ISENSE ALS_LEFT ALS_RIGHT

NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.

46B5 40D5 40D5 40D5 46C5 40B2 40B2 40B2

40C2 40C2

49B4 49B4 49B4 40C5 40D5

OUT

40C5

NC NC

SMC
SYNC_MASTER=T18_MLB SYNC_DATE=06/26/2008

A

40D5 40D5 40C5

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

A

SMC_PB3: SMC_IG_THROTTLE_L for MG systems. Otherwise, TP/NC okay (was ISENSE_CAL_EN)

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

REV.
C

D
APPLE INC.
SCALE NONE

SHT
49

OF
109

8

7

6

5

4

3

2

1

8

7

6
39A8

5
SMC_FAN_1_CTL SMC_FAN_2_CTL SMC_FAN_3_CTL SMC_GFX_THROTTLE_L NC_SMC_FAN_1_CTL
MAKE_BASE=TRUE

4

3

2
SMC FSB to 3.3V Level Shifting
40A1 8B5

1

=PP3V3_S0_SMC

39A8

NC_SMC_FAN_2_CTL
MAKE_BASE=TRUE

39A8

NC_SMC_FAN_3_CTL
MAKE_BASE=TRUE

1

R5060
470
5% 1/16W MF-LF 402

SMC Reset "Button" / Brownout Detect
39C8 39C8 49D7 40C7 40C1 39D4 8D1 =PP3V3_S5_SMC 56C1 40B2 39C5

SMC_IG_THROTTLE_L
MAKE_BASE=TRUE

21A4 21B3

8D7

=PP1V05_S0_SMC_LS

ESTARLDO_EN
SMC_BC_ACOK
MAKE_BASE=TRUE

NC_ESTARLDO_EN
MAKE_BASE=TRUE
1

R5061
3.3K
5% 1/16W MF-LF 402

2

TO SMC

=CHGR_ACOK

57C5

SMC_PROCHOT_3_3_L

OUT

39D5

D
SMC_MANUAL_RST_L NOSTUFF
1

C5000
0.1uF
20% 10V CERM 402

1

1

39C8

SMC_P24 SMC_P26 SMC_P41 SMC_NB_CORE_ISENSE SMC_NB_DDR_ISENSE ALS_LEFT
SMC_GPU_VSENSE

TP_SMC_P24
MAKE_BASE=TRUE
2

D

R5000
1K
5% 1/16W MF-LF 402

3

CRITICAL
2

39C8

SMC_BMON_MUX_SEL
MAKE_BASE=TRUE

44A5

Q5060
CPU_PROCHOT_BUF
5

U5000
NCP303LSN
SOT23-5-HF 5
NC
2

39C8

TP_SMC_P41
MAKE_BASE=TRUE

BC847BV-X-F SOT563-HF
4

4

CD NC GND
3

OUT IN

1 2

39A8

SMC_MCP_CORE_ISENSE
MAKE_BASE=TRUE

TO CPU
44D5 71C3 60C8 14B6 10C5 44C5

R5062
3.3K CPU_PROCHOT_L
1 2

6

SMC_RESET_L

OUT

39C3 41D3 39A8

SMC_MCP_DDR_ISENSE
MAKE_BASE=TRUE

BI

CPU_PROCHOT_L_R

2

Q5060
BC847BV-X-F SOT563-HF
1

5% 1/16W

R5001
0
5% 1/10W MF-LF 603

C5001
0.01UF
10% 16V CERM 402

1

39A8

SMC_CPU_FSB_ISENSE
MAKE_BASE=TRUE

44B5

MF-LF 402

SILK_PART=SMC_RST

39C5
2

SMC_MCP_VSENSE
MAKE_BASE=TRUE

6
43D6

D

Q5059
SSM6N15FEAPE
SOT563

2

Q5032
SSM6N15FEAPE
SOT563

D

3
39D8

SMC_EXCARD_PWR_EN SMC_RSTGATE_L SMC_PB3 ALS_GAIN SMC_ANALOG_ID ALS_RIGHT

TP_SMC_EXCARD_PWR_EN
MAKE_BASE=TRUE

39D8

TP_SMC_RSTGATE_L
MAKE_BASE=TRUE

39B8

NC_SMC_PB3
MAKE_BASE=TRUE

1

S

G

2

5
49D7 40D8 40C1 39D4 8D1 =PP3V3_S5_SMC

G

S

4
39A5

NC_ALS_GAIN
MAKE_BASE=TRUE

SMC_PROCHOT

IN

39A5

5
47B1 SMC_TPAD_RST_L

U5001
SN74LVC1G02
SOT553-5 4
39A8

1

NC_SMC_ANALOG_ID
MAKE_BASE=TRUE
71B3 14B7 10C6

OUT

PM_THRMTRIP_L

SMC_TPAD_RST

39A8

NC_ALS_RIGHT
MAKE_BASE=TRUE
3

47C3 40C2 40A3 39C5

SMC_ONOFF_L

2

02
3

D

Q5059
SSM6N15FEAPE
SOT563

4

S

G

5

SMC_THRMTRIP

IN

39A5

C
49D7 40D8 40C7 39D4 8D1

C
=PP3V3_S5_SMC
39B8 39B8

SMC_PA0 SMC_PA1

R5091 R5092

100K 100K

1 1

2

5%
2

1/16W 1/16W

MF-LF MF-LF

402 402

5%

SMC AVREF Supply
CRITICAL
47C3 40C7 40A3 39C5

SMC_ONOFF_L SMC_LID SMC_PH2 SMC_TX_L SMC_RX_L

VR5020
8D1

R5095
PP3V3_S5_AVREF_SMC
7C2 39D4 39B8

47A5 39B5 38B4 39A5
2

R5070 R5071 R5072 R5073 R5074

10K 100K 10K 10K 100K

1 1 1 1 1

2

5%
2

1/16W 1/16W 1/16W 1/16W 1/16W

MF-LF MF-LF MF-LF MF-LF MF-LF

402 402 402 402 402

=PPVIN_S5_SMCVREF
1

REF3333
SOT23-3

5%
2

0

IN GND

OUT

2

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V 1

OUT

SMC_EXCARD_OC_L

1 5% 1/16W MF-LF 402

EXCARD_OC_L

IN

20C2 41C5 39C5 39B8 37A8 41C3 39C5 39B8 37A8

5%
2

5%
2

5%

3

C5026
0.01UF
10% 16V CERM 402

39B5

OUT

=SMC_SMS_INT

SMS_INT_L
MAKE_BASE=TRUE

ONEWIRE_PU

IN

49C7 56C2 39B8 56A8 39C5 7A7 41D5 39B5 41D5 39B5

SYS_ONEWIRE SMC_BS_ALRT_L SMC_TMS SMC_TDO SMC_TDI SMC_TCK SMC_BC_ACOK SMC_GFX_OVERTEMP_L

2 1 1

R5075 R5076 R5077 R5078 R5079 R5080 R5087 R5050

2.0K 100K 10K 10K 10K 10K 470K 10K

1 1 1 1 1 1 1 1

2

5%
2

1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W

MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF

402 402 402 402 402 402 402 402

5%
2

C5020
0.47UF
10% 6.3V CERM-X5R 402

C5025
10uF
20% 6.3V X5R 603

5%
2

5%
2

2

2

41D3 39B5 41D3 39B5 56C1 40D5 39C5

5%
2

5%
2

GND_SMC_AVSS
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

39C2 43B5 43C6 43D6 44A1 44A4 44B2 44B5 44C5 44D5 39B8

5%
2

5%

B
39A8 39A8

B
SMC_FAN_1_TACH SMC_FAN_2_TACH SMC_FAN_3_TACH SMC_GPU_ISENSE SMC_NB_MISC_ISENSE SMC_ADAPTER_EN SMC_CASE_OPEN

R5051 R5052 R5053 R5054 R5055 R5085 R5086 R5088 R5090

10K 10K 10K 10K 10K 10K 10K

1 1 1 1 1

2

5%
2

1/16W 1/16W 1/16W 1/16W 1/16W

MF-LF MF-LF MF-LF MF-LF MF-LF

402 402 402 402 402

5%
2

System (Sleep) LED Circuit
8C3

39A8 39C5 39C5

5%
2

5%
2

=PP5V_S3_SYSLED

5%

SMC Crystal Circuit
R5031
523
1% 1/16W MF-LF 402 1 1

Debug Power "Button"
C5010
15pF

39D5 34B7 21C7 39B5

1 1

2

5%
2

1/16W 1/16W

MF-LF MF-LF

402 402

5%

R5030
20
1% 1/16W MF-LF 402
39C3

39B8

SMC_EXCARD_CP

10K

1

2

5%

1/16W

MF-LF

402

SMC_XTAL CRITICAL
1

1 5% 50V CERM 402

2

SMC_ONOFF_L NOSTUFF
1

OUT
NOSTUFF
1

39C5 40C2 40C7 47C3

39C5 64C8 39C5 21C3 7C3

PM_SLP_S5_L PM_SLP_S4_L

100K

1

2

2

2

5%

1/16W

MF-LF

402

SYS_LED_ILIM
2 SOD

Y5010
20.00MHZ
5X3.2-SM

R5015
0
5% 1/10W MF-LF 603

R5016
0
5% 1/10W MF-LF 603

PLACE R5015,R5001 ON BOTTOM SIDE PLACE R5016 ON TOP SIDE
40D2 8B5

SILK_PART=PWR_BTN
2

=PP3V3_S0_SMC

C5011
15pF
2

SYS_LED_L_VDIV

2SA2154MFV-YAE
1

2

Q5030
3

39C3

SMC_EXTAL

1 5% 50V CERM 402

2

SILK_PART=PWR_BTN
39B8

SMC_PA5

R5089

10K

1

2

R5032
1.47K

1

5%

1/16W

MF-LF

402

1% 1/16W MF-LF 402 2

SYS_LED_ANODE

OUT

38B4

SMC Support
SYS_LED_L

A
Q5032
SSM6N15FEAPE
SOT563
39B5

SYNC_MASTER=YUAN.MA
D
6

SYNC_DATE=05/28/2008

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

A

IN

SMC_SYS_LED
2

G

S

1

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

REV.
C

D
APPLE INC.
SCALE NONE

SHT
50

OF
109

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

LPC+SPI Connector
CRITICAL LPCPLUS

55909-0374

J5100

D

41C7 41C3 8D1 8D5

=PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS LPC_AD<0> LPC_AD<1> SPI_ALT_MOSI SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L SMC_TMS DEBUG_RESET_L SMC_TDO SMC_TRST_L SMC_MD1 SMC_TX_L

M-ST-SM 31 32 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

D
LPC_CLK33M_LPCPLUS LPC_AD<2> LPC_AD<3> SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO
IN BI BI
26B1 74C3 19B3 39C8 74C3 19B3 39C8 74C3

1
74C3 39C8 19B3 74C3 39C8 19B3

BI BI

3 5 7

74A3 41C5 74A3 41B5 74C3 39C8 19C3 39C5 19B7 40B2 39B5

IN OUT IN OUT OUT IN OUT

9 11 13 15 17 19 21 23 25 27 29

OUT IN IN BI IN OUT OUT OUT OUT OUT OUT

41C5 41C7 41C5 74A3 41B5 19B7 39C8 19C3 39C5 39B5 40B2 39B5 40B2 39C3 40D6 39C1 37A8 39B8 39C5 40B2 18B7

Alternate SPI ROM Support
MUX SEL CONTROLLED BY FRANKCARD SWITCH ONCE CS1 IS SUPPORTED IN MCP
41D5 41C7 41C3 8D1 50C6 41B5 8A3

39C1 39C1 40C2 39C5 39B8 37A8

IN OUT IN

33

34

=PP3V3_S5_LPCPLUS
1

=PP3V3_S5_ROM

LPCPLUS

C5114
0.1UF
20% 10V 402

R51901
SPI_CLK_R
74A3 41A5 21B3

5% 1/16W MF-LF 402 2
IN

9

10K

LPCPLUS
1 Y+ 2 Y-

2 CERM

516S0573
OUT OUT
41D3 74A3 41D5 74A3 8C5 41D5 41C7 8D1

MCP79 Internal SPI MUX Support
NOT SUPPORTED IN REV A01 OR B01 MCP79 SILICON =PP3V3_S0_LPCPLUS =PP3V3_S5_LPCPLUS

VCC

74A3 41A5 21B3

IN

C
R51911
5% 1/16W MF-LF 402 2

SPI_MOSI_R

PI3USB102ZLE
TQFN

U5110

M+ 5 M- 4 D+ 7 D- 6

SPI_ALT_CLK SPI_ALT_MOSI SPI_CLK_MUX SPI_MOSI_MUX

C
R5140 1
100K
5% 1/16W MF-LF 402

OUT OUT

41A8 50C6 41A8 50C3

10K

CRITICAL
41D3 41C5

MCP SPI Override Options
MCP79 REV A01 REQUIRES EXTERNAL MUX, REV B01 STILL DOES NOT SUPPORT INTERNAL MUX
41D3 41C7

MCP_CS1_YES
2 3

LPC_FRAME_PU

S

D

SPIROM_USE_MLB

10 SEL GND 3

OE* 8

2

SPIROM_USE_MLB

Q5140
SSM3J16FV
SOD-VESM-HF

MCP_CS1_YES R5141 1
470
5% 1/16W MF-LF 402 2

1

G

SEL HIGH OUTPUTS TO D (ON BOARD ROM) SEL LOW OUTPUTS TO M (FRANKCARD ROM)
41D5 41C7 41C3 8D1

MCP_CS1_NO

R5142
=PP3V3_S5_LPCPLUS
1

LPC_FRAME_R_L

OUT

19C5

LPCPLUS

From Frank Card

1

0

2

C5124
0.1UF
20% 10V 402

9

LPCPLUS SPI_MISO SPI_CS0_R_L
1 Y+ 2 Y-

5% PLACEMENT_NOTE=Place near J5100 1/16W MF-LF 402

2 CERM

SPI_ALT_MISO

74A3

SPI_CS1_R_L_USE_MLB
MAKE_BASE=TRUE

=SPI_CS1_R_L_USE_MLB

VCC
74A3 41A5 21B3 74A3 21B3

IN

41D5 74A3

BI

21C7

OUT IN

PI3USB102ZLE
TQFN

U5120

M+ 5 M- 4

1 SPI_ALT_CS_L_MUX

1/16W

MCP_CS1_NO Pull-up on debug card 0 2 R5127 SPI_ALT_CS_L
5% MF-LF 402
OUT
41D3

MCP_CS1_YES

R5147
1

0

2

To Frank Card
PLACEMENT_NOTE=PLACE NEXT TO U5120

D+ 7 D- 6 SPI_MLB_CS_L_MUX

SPI_MISO_MUX

IN

41A8 50C3

CRITICAL
10 SEL GND OE* 8 3

MCP_CS1_NO 0 2 R5126 SPI_MLB_CS_L 1 1/16W 402 5% MCP_CS1_NO MF-LF

5% 1/16W MF-LF 402

OUT

50C6

B
R5146
1

R5144
20K

1

=PP3V3_S5_ROM

8A3 41C7 50C6

MCP_CS1_YES&LPCPLUS_NOT 0
2

5% 1/16W MF-LF 402 2

SPI Frequency Clamp
ENSURES MCP79 SPI_DO OR SPI_CLK INPUT IS LOW WHEN STRAP IS LATCHED.NOT NEEDED FOR B01 OR LATER. NO STUFF Keep very short MCP_FORCE_SPI_DO_L
23C4 8A3

B

5% PLACEMENT_NOTE=PLACE NEXT TO U1400 1/16W MF-LF 402

R5161
1

0

2

SPI_MOSI SPI_CLK

OUT

50C4 74A3

SPI MUX BYPASS
LPCPLUS_NOT R5156
50C6 41C5

=PP3V3_S5_MCP_A01 MCP_A01&MCP_A01Q

MCP_A01&MCP_A01Q

Q5160
SSM6N15FEAPE
SOT563

D 6

5% 1/16W MF-LF 402

OUT

50C5 74A3

R51631
100K
5% 1/16W MF-LF 402 2

MCP_A01&MCP_A01Q

R5162
2

G

S 1

1

0

2

OUT

SPI_CLK_MUX

1

0
5% 1/16W MF-LF 402

2

SPI_CLK_R

IN

21B3 41C8 74A3

MCP_SPI_FORCE MCP_A01&MCP_A01Q

LPCPLUS_NOT R5157
0
1 2 5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

Q5160
SPI_MOSI_R
IN
21B3 41C7 74A3

D 3

50C3 41C5

OUT

SPI_MOSI_MUX

LPCPLUS_NOT R5158
50C3 41B5

SLP_S3# nVidia recommendation, SSM6N15FEAPE SOT563 not compatible with button-mashing. MCP_A01&MCP_A01Q

IN

SPI_MISO_MUX

0
1 5% 1/16W MF-LF 402 2

SPI_MISO

OUT

21B3 41B7 74A3 68D8 64D5 39C5 34B7 21C3 7C3

R5160
IN

5

G

PM_SLP_S3_L

1

0

S 4

2

MCP_SPI_FORCE_L

LPC+SPI Debug Connector
SYNC_MASTER=CHANGZHANG SYNC_DATE=05/09/2008

A

5% 1/16W MF-LF 402

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
SCALE NONE

SHT
51

OF
109

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

MCP79 SMBUS "0" CONNECTIONS
8C5

SMC "0" SMBus Connections
8C5

SMC "A" SMBus Connections
NOTE: SMC RMT bus remains powered and may be active in S3 state
8D3

=PP3V3_S0_SMBUS_MCP_0

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S3_SMBUS_SMC_A_S3

MCP79
U1400 (MASTER)

R5200
4.7K
5% 1/16W MF-LF 402

1

1

R5201
4.7K
5% 1/16W MF-LF 402

SO-DIMM "A"
J3100 (Write: 0xA0 Read: 0xA1) =I2C_SODIMMA_SCL =I2C_SODIMMA_SDA
28A5 39B8

SMC
U4900 (MASTER) SMB_0_S0_CLK SMB_0_S0_DATA
76D3

R5250
4.7K
5% 1/16W MF-LF 402

1

1

R5251
4.7K
5% 1/16W MF-LF 402

MCP Temp
EMC1403-5: U5535 (Write: 0x98 Read: 0x99) =I2C_MCPTHMSNS_SCL =I2C_MCPTHMSNS_SDA
45C3 39A5

SMC
U4900 (MASTER) SMB_A_S3_CLK SMB_A_S3_DATA
76D3 7D5 7B5

R5270 1
1K
5% 1/16W MF-LF 402

1

R5271
1K
5% 1/16W MF-LF 402

TRACKPAD
J5800 (Write: 0x90 Read: 0x91) =I2C_TPAD_SCL =I2C_TPAD_SDA
48C1

2

2

2

2

2

2

D

21C3 13B6 74B3 21C3 13B6 74B3

SMBUS_MCP_0_CLK
MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL
MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE

D

SMBUS_MCP_0_DATA
MAKE_BASE=TRUE

28A5

39C5

76D3

SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE

45C3

39A5

76D3 7D5 7B5

SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE

48C1

SO-DIMM "B"
J3200 (Write: 0xA2 Read: 0xA3) =I2C_SODIMMB_SCL =I2C_SODIMMB_SDA
29A5

ALS
J3401 (Write: 0x52 Read: 0x53) I2C_ALS_SCL I2C_ALS_SDA
31B6

29A5

31B6

SMC "Battery A" SMBus Connections
8D1

SMC "B" SMBus Connections
8C5

=PP3V42_G3H_SMBUS_SMC_BSA

=PP3V3_S0_SMBUS_SMC_B_S0

SMC

R5280 1
1K
5% 1/16W MF-LF 402
76D3 7B7 7A7

1

R5281
1K
5% 1/16W MF-LF 402

BATTERY & BIL
J6950 & J6955 (See Table) =SMBUS_BATT_SCL =SMBUS_BATT_SDA
56A3 56A6 39A5

SMC
U4900 (MASTER) SMB_B_S0_CLK SMB_B_S0_DATA
76D3

R5260 1
4.7K
5% 1/16W MF-LF 402

1

R5261
4.7K
5% 1/16W MF-LF 402

CPU Temp
EMC1403-5: U5515 (Write: 0x98 Read: 0x99) =I2C_CPUTHMSNS_SCL =I2C_CPUTHMSNS_SDA
45D3

MCP79 SMBUS "1" CONNECTIONS
C
8B5 8A3

U4900 (MASTER)
39B5

2

2

2

2

=PP3V3_S5_SMBUS_MCP_1 NOSTUFF NOSTUFF
1

SMB_BSA_CLK SMB_BSA_DATA

SMBUS_SMC_BSA_SCL
MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL
MAKE_BASE=TRUE

C

=PP3V3_S0_SMBUS_MCP_1

39B5

76D3

SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE

56A3 56A6

39A5

76D3

SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE

45D3

R5232
10K

1

R5233
10K

HDCP ROM
U2690 OR U2695 (Write: 0xA0-0xAE, Read: 0xA1-0xAF) (All 8 addresses used) =I2C_HDCPROM_SCL =I2C_HDCPROM_SDA
25A6

MCP79
U1400 (MASTER?)
74B3 21C3

R5230
2.0K

1

1

R5231
2.0K

5% 1/16W MF-LF 402 2

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 402 2

5% 1/16W MF-LF 2 402

Battery Charger

Battery
Battery Manager - (Write: 0x16 Read: 0x17) Battery LED Driver - (Write: 0x36 Read: 0x37) Battery Temp - (Write: 0x90 Read: 0x91)

ISL6258A - U7000 (Write: 0x12 Read: 0x13) =SMBUS_CHGR_SCL =SMBUS_CHGR_SDA
57C6

SMBUS_MCP_1_CLK
MAKE_BASE=TRUE

74B3 21C3

SMBUS_MCP_1_DATA
MAKE_BASE=TRUE

25A6

57C6

Mikey
U6860
(WRITE: 0X72 READ: 0X73)

=I2C_MIKEY_SCL =I2C_MIKEY_SDA

52C7

SMC "Management" SMBus Connections
The bus formerly known as "Battery B"
8D3

52C7

=PP3V3_S3_SMBUS_SMC_MGMT

SMC

R5290 1
4.7K
5% 1/16W MF-LF 402 2
76D3

1

R5291
4.7K

Vref DACs
U2900 (Write: 0x98 Read: 0x99) =I2C_VREFDACS_SCL =I2C_VREFDACS_SDA
27C7

B
39C5 39C8

U4900 (MASTER) SMB_MGMT_CLK SMB_MGMT_DATA

5% 1/16W MF-LF 2 402

B

SMBUS_SMC_MGMT_SCL
MAKE_BASE=TRUE

76D3

SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE

27C7

Margin Control
U2901 (Write: 0x30 Read: 0x31) =I2C_PCA9557D_SCL =I2C_PCA9557D_SDA
27A8

27A8

SMS
U5930 (Write: 0x70 Read: 0x71) =I2C_SMS_SCL =I2C_SMS_SDA
49D6

49C6

M97 SMBUS CONNECTIONS

A

SYNC_MASTER=BEN

SYNC_DATE=04/21/2008

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
SCALE NONE

SHT
52

OF
109

8

7

6

5

4

3

2

1

8

7
CPU Voltage Sense / Filter
8D7

6

5

4

3

2

1

=PPVCORE_S0_CPU_VSENSE

XW5309
SM 1 2

R5309
CPUVSENSE_IN
4.53K
1 1% 1/16W MF-LF 402 2

SMC_CPU_VSENSE
1

OUT

39C5

PLACEMENT_NOTE=Place near U1000 center

C5309
0.22UF
20% 6.3V X5R 402

2

D

GND_SMC_AVSS Place RC close to SMC

39C2 40B6 43B5 43C6 44A1 44A4 44B2 44B5 44C5 44D5

D

MCP Voltage Sense / Filter
8C7

=PPVCORE_S0_MCP_VSENSE

XW5359
SM 1 2

R5359
MCPVSENSE_IN
1

4.53K
1% 1/16W MF-LF 402

2

SMC_MCP_VSENSE
1

OUT

40D4

PLACEMENT_NOTE=Place near U1400 center

C5359
0.22UF
20% 6.3V X5R 402

2

GND_SMC_AVSS Place RC close to SMC

39C2 40B6 43B5 43D6 44A1 44A4 44B2 44B5 44C5 44D5

C
PBUS VOLTAGE SENSE ENABLE & FILTER

C

Q5315
NTUD3127CXXG
SOT-963

N-CHANNEL
D

6

PBUSVSENS_EN_L

R5316 1
64C1

IN

=PBUSVSENS_EN

2

G S

100K
1% 1/16W MF-LF 402

Enables PBUS VSense divider when high.

1 3 D

2

PPBUS_G3HRS5_VSENSE
MIN_LINE_WIDTH=0.20 mm MIN_NECK_WIDTH=0.20 mm VOLTAGE=18.5V

R5385 1
27.4K
1% 1/16W MF-LF 402

5
8C1

G S

=PPBUS_G3HRS5
4

2

RTHEVENIN = 4573 OHMS SMC_PBUS_VSENSE
OUT
39C5

B

P-CHANNEL

R53151
100K
1% 1/16W MF-LF 402

B

R5386
5.49K
1% 1/16W MF-LF 402

1 1

C5385
0.22UF
20% 6.3V X5R 402

2

2 2

PBUSVSENS_EN_L_DIV

GND_SMC_AVSS Place RC close to SMC

39C2 40B6 43C6 43D6 44A1 44A4 44B2 44B5 44C5 44D5

VOLTAGE SENSING

A

SYNC_MASTER=YUNWU

SYNC_DATE=02/04/2008

NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER
051-7918

A

REV.
C

D
APPLE INC.
SCALE NONE

SHT
53

OF
109

8

7

6

5

4

3

2

1

8

7
MCP VCore Current Sense
=PP5VR3V3_S0_MCPCOREISNS
1

6

5

4

3

2

1

8B5

R5490
0.001
1% 1W MF 1206
8C8

C5415
0.1uF
3
20%

10V 2 CERM 402

MCP VCore Current Sense Filter
R5416
6

V+

1 IN =PPVCORE_S0_MCP_REG_R 3
61C4 77D3

2 =PPVCORE_S0_MCP 4

OUT

8C8 22D5 24D8 61B1

U5400
SC70

D

ISNS_PVCORES0MCP_N ISNS_PVCORES0MCP_P

5 IN4 IN+

INA213
OUT

MCPCORE_IOUT

1

4.53K
1% 1/16W MF-LF 402

2

SMC_MCP_CORE_ISENSE
1

OUT

40D4

D

77D3

REF 1

C5472
0.22UF
20% 6.3V X5R 402

GND
2

2

GND_SMC_AVSS Place RC close to SMC

39C2 40B6 43B5 43C6 43D6 44A1 44A4 44B2 44B5 44C5

MCP MEM VDD Current Sense
8B5

=PP3V3_S0_MCPDDRISNS
1

R5491
0.002
1% 1/4W MF 1206
8B8

C5416
0.1uF
20% 10V 402

MCP MEM VDD Current Sense Filter

2 CERM

IN

=PP1V5_S0_FET_R

1 3

2 =PP1V5_S0 4
77D3

OUT

8B8

U5401
5 IN4 IN+ SC70

3 V+

ISNS_P1V5S0MCP_N ISNS_P1V5S0MCP_P

INA210

R5417
MCPDDR_IOUT
1

OUT 6
REF 1

4.53K
1% 1/16W MF-LF 402

2

SMC_MCP_DDR_ISENSE
1

OUT

40D4

77D3

C5435
0.22UF
20% 6.3V X5R 402

2

C

GND

2

C
39C2 40B6 43B5 43C6 43D6 44A1 44A4 44B2 44B5 44D5

GND_SMC_AVSS Place RC close to SMC

CPU 1.05V AND CPU VCORE HIGH SIDE CURRENT SENSE
8B5

=PP3V3_S0_CPUVTTISNS
1

R5492
0.01
0.5% 1W MF 0612
8C1

C5417
0.1uF
3
20% 402

CPU VCore Load Side Current Sense / Filter
Place RC close to SMC

2 10V CERM

V+

R5471
6.19K
60C7

IN

=PPCPUVCORE_VTT_ISNS_R 1 3

2 =PPCPUVCORE_VTT_ISNS OUT 4
77D3

8C2

U5402
5 IN4 IN+ SC70

ISNS_CPUVTT_N ISNS_CPUVTT_P

INA213

R5418
CPUVTT_IOUT
1

IN

IMVP6_IMON

1

2

SMC_CPU_ISENSE

OUT

39C5

1% 1/16W

OUT 6
REF 1

4.53K
1% 1/16W MF-LF 402

2 1

SMC_CPU_FSB_ISENSE

OUT

40D4

MF-LF 402

R5480
17.4K
1% 1/16W MF-LF 402

1

1

C5470
0.22UF
20% 6.3V

77D3

C5436
0.22UF
20% 6.3V X5R 402

2

X5R 402

2

GND
2

2

GND_SMC_AVSS

39C2 40B6 43B5 43C6 43D6 44A1 44A4 44B5 44C5 44D5

GND_SMC_AVSS

39C2 40B6 43B5 43C6 43D6 44A1 44A4 44B2 44C5 44D5

B
BMON CURRENT SENSE

Place RC close to SMC

B
DC-IN (AMON) CURRENT SENSE
R5481

PLACE U5413, R5423, R5431, C5459 NEAR SMC (U4900)
8D1

IN

CHGR_AMON

1

4.53K
1% 1/16W MF-LF 402

2 1

SMC_DCIN_ISENSE

OUT

39C5

C5487
0.22UF
20% 6.3V X5R 402

=PP3V42_G3H_BMON_ISNS ENG_BMON
1 2

C5459
0.1uF
20% 10V 402

ENG_BMON
1

U5413
BMON_INA_OUT
3 V+ NC7SB3157P6XG SC70 1 B1 SEL 6
1

GND_SMC_AVSS

39C2 40B6 43B5 43C6 43D6 44A4 44B2 44B5 44C5 44D5

C5418
0.1uF
20% 10V 402

2 CERM

SMC_BMON_MUX_SEL

IN

40D4

2 CERM

REGULATOR SIDE

ENG_BMON

2 GND
0

VCC 5

U5403
77D3 57B3

OUT

CHGR_CSO_R_P CHGR_CSO_R_N LOAD SIDE

5 IN4 IN+

INA213
SC70

R5401
4

OUT

6

57C5

IN

CHGR_BMON

3
B0 ENG_BMON A

BMON_AMUX_OUT
1 ENG_BMON

1

4.53K
1% 1/16W MF-LF 402

2 1

SMC_BATT_ISENSE

OUT

39C5

VER 1
77D3 57B3

IN

REF 1

PROD_BMON

R5431
GND
2

R5423
100K
5% 1/16W MF-LF 402

C5490
0.22UF
20% 6.3V X5R 402

Current Sensing
SYNC_MASTER=YUNWU SYNC_DATE=04/07/2008

A

0
5% 1/16W MF-LF 402 2

2

NOTE: MONITORING CURRENT FROM BATTERY TO PBUS (BATTERY DISCHARGE) ACROSS R7008

GND_SMC_AVSS

NOTICE OF PROPRIETARY PROPERTY
39C2 40B6 43B5 43C6 43D6 44A1 44B2 44B5 44C5 44D5

A

PLACE R5491 AND C5390 CLOSE TO SMC

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

INA213 has gain of 50V/V

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

PLACE U5403 AND C5418 NEAR R7008

For engineering, stuff U5313 and unstuff R5330 For production, stuff R5330 and unstuff U5313

SIZE

DRAWING NUMBER
051-7918

REV.
C

D
APPLE INC.
SCALE NONE

SHT
54

OF
109

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

CPU T-Diode Thermal Sensor
INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE
8B5

=PP3V3_S0_CPUTHMSNS

R5515
1

47
5% 1/16W MF-LF 402

2

PP3V3_S0_CPUTHMSNS_R
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V 1 1

D
77D3 10C6

VDD
BI

C5515
0.1uF
20% 10V CERM 402

R5516 1
10K
5% 1/16W MF-LF 402

1

R5517
10K
5% 1/16W MF-LF 402

D

CPU_THERMD_P
SIGNAL_MODOL=EMPTY

U5515
EMC1403-1-AIZL
2 3 TSSOP

2

2

2

DETEC

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