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苹果5C原厂图


8

7

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5

4

3

2
REV
2

1
ECN
0001669557

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

DESCRIPTION OF REVISION
ENGINEERING RELEASED

CK APPD DATE
2012-10-14

D

X155 PROTO1 SINGLE_BRD Mon Oct 8 11:06:07 2012
TO DO: CLEANUP ALTERNATES FOR X155

D

PDF PAGE
TABLE_TABLEOFCONTENTS_HEAD

CSA PAGE

CONTENTS

SYNC MASTER

DATE

ALTERNATES
TABLE_ALT_HEAD

X155 BOM CALLOUTS
TABLE_5_HEAD

PART NUMBER

2
TABLE_TABLEOFCONTENTS_ITEM

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

H5P JTAG, USB ,PLL H5P GPIO & CONTROL H5P IO POWER H5P SOC/CPU/SRAM PWR H5P W/ NAND H5P VIDEO BUTTON FLEX B2B L67 AUDIO CODEC (1/2) L67 AUDIO CODEC (2/2) CG FLEX B2B AGATHA PMU(1/2) AGATHA PMU(2/2) CHESTNUT + BACKLIGHT DRIVER SPKR AMP + LED DRIVER TRISTAR DOCKFLEX B2B D404 (TOUCH B2B, DRIVER ICS) LCM CONNECTOR SENSORS CAM0 CONNECTOR BATT B2B, TPS, PD FEATURES RADIO_MLB HIERARCH. SYMBOL

N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A

N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A

ALTERNATE FOR PART NUMBER 138S0652 339S0176 339S0176

BOM OPTION ALTERNATE ALTERNATE ALTERNATE

REF DES ? ? ?

COMMENTS:
TABLE_ALT_ITEM

PART# 051-9584 820-3329 825-6838

QTY 1 1 1

DESCRIPTION SCH, SINGLE_BRD, X155 PCB, SINGLE_BRD, X155 LABEL FOR X155 639-3796

REFERENCE DESIGNATOR(S) SCH PCB EEEE_F284

CRITICAL Y Y Y

BOM OPTION
TABLE_5_ITEM

138S0648 339S0177 339S0178

4.7UF CERM 0402 6.3V
TABLE_ALT_ITEM

?
TABLE_5_ITEM

3
TABLE_TABLEOFCONTENTS_ITEM

H5P ALTERNATE
TABLE_ALT_ITEM

?
TABLE_5_ITEM

H5P ALTERNATE

EEEE_16G

4
TABLE_TABLEOFCONTENTS_ITEM

5
TABLE_TABLEOFCONTENTS_ITEM

6
TABLE_TABLEOFCONTENTS_ITEM

7
TABLE_TABLEOFCONTENTS_ITEM

COMPASS BOM OPTIONS
TABLE_5_HEAD

GYRO BOM OPTIONS
TABLE_5_HEAD

8
TABLE_TABLEOFCONTENTS_ITEM

PART# 639-4024

QTY 1

DESCRIPTION ST GYRO - COMPASS POP

REFERENCE DESIGNATOR(S) U16

CRITICAL Y

BOM OPTION
TABLE_5_ITEM

PART# 338S1158 132S0391

QTY 1 1

DESCRIPTION ST GYRO ST GYRO - CP CAP

REFERENCE DESIGNATOR(S) U8 C11

CRITICAL Y Y

BOM OPTION
TABLE_5_ITEM

C

9
TABLE_TABLEOFCONTENTS_ITEM

COMPASS_POP

GYRO_ST
TABLE_5_ITEM

C

10
TABLE_TABLEOFCONTENTS_ITEM

NAND BOM OPTIONS
TABLE_5_HEAD

GYRO_ST

PART# 335S0878

QTY 1

DESCRIPTION NAND,19NM,16GX8,MLC,PPN1.5

REFERENCE DESIGNATOR(S) U4

CRITICAL Y

BOM OPTION
TABLE_5_ITEM

11
TABLE_TABLEOFCONTENTS_ITEM

CHESTNUT BOM OPTIONS
TABLE_5_HEAD

NAND_16G

PART# 338S1172 152S1649
TABLE_5_HEAD

QTY 1 1 1 1

DESCRIPTION TI CHESTNUT TI CHESTNUT - 1.5 UH IND INTERSIL CHESTNUT INTERSIL CHESTNUT -2.2 UH IND

REFERENCE DESIGNATOR(S) U3 L19 U3 L19

CRITICAL Y Y Y Y

BOM OPTION
TABLE_5_ITEM

12
TABLE_TABLEOFCONTENTS_ITEM

HORIZONTAL CAP BOM OPTIONS
PART# 138S0801 138S0801 138S0801 138S0801 138S0801 138S0801 138S0801 138S0801 138S0801 138S0794 138S0582 QTY 5 5 5 5 5 5 3 1 4 2 1 DESCRIPTION HRZN CAPS_1:10UF,0402,6.3V HRZN CAPS_1:10UF,0402,6.3V HRZN CAPS_1:10UF,0402,6.3V HRZN CAPS_1:10UF,0402,6.3V HRZN CAPS_1:10UF,0402,6.3V HRZN CAPS_1:10UF,0402,6.3V HRZN CAPS_1:10UF,0402,6.3V HRZN CAPS_1:10UF,0402,6.3V HRZN CAPS_1:10UF,0402,6.3V HRZN CAPS_1:10UF,0402,10V 4.7UF 0.55MM HEIGHT REFERENCE DESIGNATOR(S) C422,C74,C92,C250,C265 C293,C294,C257,C299,C262 C264,C378,C189,C203,C245 C190,C204,C239,C246,C195 C205,C243,C247,C252,C297 C386,C387,C333,C332,C335
C42_RF,C43_RF,C44_RF

CHESTNUT_TI
TABLE_5_ITEM

CHESTNUT_TI
TABLE_5_ITEM

13
TABLE_TABLEOFCONTENTS_ITEM

CRITICAL Y Y Y Y Y Y Y Y Y Y Y

BOM OPTION
TABLE_5_ITEM

338S1168 152S1611
TABLE_5_ITEM

CHESTNUT_INTERSIL
TABLE_5_ITEM

14
TABLE_TABLEOFCONTENTS_ITEM

HRZN_CAP_GRP1 HRZN_CAP_GRP2
TABLE_5_ITEM

CHESTNUT_INTERSIL

15
TABLE_TABLEOFCONTENTS_ITEM

HRZN_CAP_GRP3
TABLE_5_ITEM

TRISTAR BOM OPTIONS
TABLE_5_HEAD

HRZN_CAP_GRP4
TABLE_5_ITEM

PART# 343S0614
TABLE_5_ITEM

QTY 1 1 2 2

DESCRIPTION CBTL1608A1UK,WCSP,TRISTAR CBTL1610A0UK,WCSP,TRISTAR2 RES 15OHM 01005 5% RES 200HM 01005 5%

REFERENCE DESIGNATOR(S) U2 U2 R102,R103 R102,R103

CRITICAL Y Y Y Y

BOM OPTION
TABLE_5_ITEM

16
TABLE_TABLEOFCONTENTS_ITEM

HRZN_CAP_GRP5 HRZN_CAP_GRP6
TABLE_5_ITEM

TRISTAR
TABLE_5_ITEM

17
TABLE_TABLEOFCONTENTS_ITEM

343S0639 118S0671
TABLE_5_ITEM

TRISTAR2
TABLE_5_ITEM

HRZN_CAP_GRP7 HRZN_CAP_GRP8
TABLE_5_ITEM

TRISTAR
TABLE_5_ITEM

18
TABLE_TABLEOFCONTENTS_ITEM

C1201_RF C182,C307,C209,C187 C52,C156 C193

117S0202

TRISTAR2

HRZN_CAP_GRP10
TABLE_5_ITEM

B

19
TABLE_TABLEOFCONTENTS_ITEM

HRZN_CAP_GRP11
TABLE_5_ITEM

20
TABLE_TABLEOFCONTENTS_ITEM

LOW_Z_CAP

B

21
TABLE_TABLEOFCONTENTS_ITEM

BOARD_ID RADIO BOM OPTIONS
TABLE_5_HEAD

22
TABLE_TABLEOFCONTENTS_ITEM

PART# 118S0621 118S0732 117S0159 118S0626 118S0626

QTY 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

DESCRIPTION 1.00M 1% 01005 50K 1% 01005 470K 5% 01005 100K 1% 01005 100K 1% 01005 162K 1% 01005 100K 1% 01005 267K 1% 01005 255K 1% 01005 100K 1% 01005 147K 1% 01005 100K 1% 01005 100K 1% 01005 499K 1% 01005 50K 1% 01005 1.00M 1% 01005

REFERENCE DESIGNATOR(S) R25_RF R26_RF R25_RF R26_RF R25_RF R26_RF R25_RF R26_RF R25_RF R26_RF R25_RF R26_RF R25_RF R26_RF R25_RF R26_RF

CRITICAL Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y

BOM OPTION
TABLE_5_ITEM

N51_CFG_A
TABLE_5_ITEM

23
TABLE_TABLEOFCONTENTS_ITEM

N51_CFG_A
TABLE_5_ITEM

N51_CFG_B
TABLE_5_ITEM

N51_CFG_B
TABLE_5_ITEM

N53_CFG_A
TABLE_5_ITEM

SCH 051-9584 BRD 820-3329
A

118S0726 118S0626 118S0623 118S0659 118S0626 118S0689 118S0626

N53_CFG_A
TABLE_5_ITEM

N53_CFG_B
TABLE_5_ITEM

N53_CFG_B
TABLE_5_ITEM

N48_CFG_A
TABLE_5_ITEM

N48_CFG_A
TABLE_5_ITEM

N48_CFG_B
TABLE_5_ITEM

N48_CFG_B
TABLE_5_ITEM

BOM 639-3796 X155
8 7 6

118S0626 118S0650 118S0732 118S0621

N49_CFG_A
TABLE_5_ITEM

N49_CFG_A
TABLE_5_ITEM

DRAWING TITLE

A
DRAWING NUMBER

N49_CFG_B
TABLE_5_ITEM

SCH,SINGLE_BRD,X155
Apple Inc.
R

N49_CFG_B

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE SHEET

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

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NO_XNET_CONNECTION=TRUE
19 18 14 12 11 10 7 6 5 4 3 2 21 20

PP1V0 2
1

7 12

D

C34

PP1V8

SM 1

2

XW5
1

10% 6.3V 2 X5R 01005

0.01UF

PP1V8_PLL

C33

1

10% 6.3V 2 X5R 01005

0.01UF

C20

1

NOSTUFF

10% 6.3V 2 X5R 01005

0.01UF

C21

10% 6.3V 2 X5R 01005

0.01UF

C141 1
100PF
5% 10V NP0-C0G 2 01005 1

PP3V3_USB

12

C32

1

10% 6.3V 2 X5R 01005

0.01UF

C35

1

5% 6.3V 2 NP0-C0G 01005

56PF

C128
10UF

1

C157

20% 6.3V 2 CERM-X5R 0402-1

20% 6.3V 2 X5R 0201

0.22UF

12 7 2

PP1V0

0.22UF

C93

1

1

C392

12 4

PP1V2

PP1V8

2 3 4 5 6 7 10 11 12 14 18 19 20 21

20% 6.3V X5R 2 0201

20% 6.3V 2 X5R 0201

0.22UF

0.22UF

C2

1

1

C28

(3X 11.9MA)

(3X 2.7MA)

(2X 1MA)

(2X 1MA)

20% 6.3V X5R 2 0201

20% 6.3V 2 X5R 0201

0.22UF

(5.4MA) (28MA) (22MA)

(1MA) (1MA) (1MA) (1MA)

(1MA)

HSIC_VDD121 L29 HSIC_VDD122 J29 HSIC_VDD123 AK17

HSIC1_DVDD101 M29 HSIC2_DVDD102 K29 HSIC3_DVDD103 AK16

G19 J19 G18 J18 J21 G20 J20 G21

VDD_ANA_PLLUSB J22

23

BASEBAND

23

50_AP_BI_BB_HSIC1_DATA 50_AP_BI_BB_HSIC1_STB

F34 HSIC1_DATA F33 HSIC1_STB E34 HSIC2_DATA E33 HSIC2_STB

H5P-SC58950C03
SYM 1 OF 12

U1

USB_DVDD G29 USB_VDD330 J26 USB_ASW_VDD18 G28

C

C

VDD_ANA_PLL0 VDD_ANA_PLL1 VDD_ANA_PLL2 VDD_ANA_PLL3 VDD_ANA_PLL4 VDD_ANA_PLL5 VDD_ANA_PLL6 VDD_ANA_PLL7

FCMSP

WDOG AT13 XI0 A12 XO0 A13

WDOG

13

1.00M 2

45_XTAL_24M_I 45_XTAL_24M_O

FINAL XTAL PASSIVES 11/30/2011
3

12PF
1 2

C36
5% 16V CERM 01005

1% 1/32W MF 01005

R7

WLAN (TOP)

1

1.60X1.20MM-SM

1

23 23

50_AP_BI_WLAN_HSIC3_DATA 50_AP_BI_WLAN_HSIC3_STB

AV15 HSIC3_DATA AU15 HSIC3_STB AN15 AM15 AN13 AP15 AM16 AN16 AM14 JTAG_SEL JTAG_TRTCK JTAG_TRST* JTAG_TDO JTAG_TDI JTAG_TMS JTAG_TCK

USB11_DP C34 NO_CONNECT OKAY USB11_DM D34 90_USBHS_H5P_P USB_DP A32 90_USBHS_H5P_N USB_DM A31 USBHS ON/OFF TOLERANCE 5V/1.98V E27 USB_ANALOGTEST USB_VBUS F29 USB_ID E29 USB_BRICKID F28 USB_REXT A30 USB_REXT
12 12

24.000MHZ-30PPM-9.5PF-60OHM
1 5% 1/32W

2 4

Y1
1.00K2

R71

XTAL_24M_O_R

12PF
1 2

C37
5% 16V CERM 01005

XTAL_GND

SHORT-10L-0.1MM-SM 1 2

XW44

MF 01005

USB_VBUS_DETECT 12

SERIAL MODE NAMES

16 16

B
PP1V8
1

TRISTAR_BI_AP_JTAG_SWDIO TRISTAR_TO_AP_JTAG_SWCLK

1 1/32W

0.00 2
0% MF 01005

R1

90_AP_BI_TRISTAR_USB0_P

16

1

0.00 2
0% 1/32W MF 01005

R30

90_AP_BI_TRISTAR_USB0_N

16

AT15 TESTMODE R28 FUSE1_FSRC AV10 TST_STPCLK AR16 TST_CLKOUT A19 FAST_SCAN_CLK USB_ASW_VSS18 AP14 HOLD_RESET L28 HSIC_VSS121 J28 HSIC_VSS122 AL17 HSIC_VSS123 USB_VSSA0 USB_VSSA0 USB_VSSA0 AV11 RESET* AV13 CFSB K16 DDR0_CKEIN N8 DDR1_CKEIN M28 HSIC1_DVSS K28 HSIC2_DVSS AL16 HSIC3_DVSS CPU0_SWITCH AR9 CPU0_SWITCH CPU1_SWITCH AU10 CPU1_SWITCH USB_BRICKID_DM_MON G27
1

B

R6

19 18 14 12 11 10 7 6 5 4 3 2 21 20

13

AP_TO_PMU_TEST_CLKOUT

R67

1% 1/32W MF 2 01005

43.2

5% 1/32W MF 2 01005
23 22 19 16 14 13 12

47.0K

RESET_1V8_L

1.8V TOLERANT
1

C1

H27 H26 H29

PLACE R49 AND C1 CLOSE TO EACH OTHER AND U1 PER EMC

A

H28

10% 6.3V 2 X5R-CERM 01005

1000PF

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

H5P JTAG, USB ,PLL
DRAWING NUMBER

Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE SHEET

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

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FLOAT=LOW, PULLUP=HIGH 1111 X155 INITIAL 1101 - PROTO1 TRISTAR 1100 - PROTO1 TRISTAR 2

7

6

5

4

3
2 01005 MF 1/32W 5% 2 01005 MF 1/32W 5% 1

2
PP1V8 2
3 4 5 6 7 10 11 12 14 18 19 20 21

1

BOARD_REV[3:0]={EHCI_PORT3,EHCI_PORT_PWR2,EHCI_PORT_PWR1,EHCI_PORT_PWR0}

<---PROTO1 SELECTED

2.2K

R171
5% 1/32W MF 01005 2

1

R18

1

10

45_AP_TO_CODEC_I2S_MCLK

1

33.2 2
1% 1/32W MF 01005

R16

R91 1

2.2K

5% 1/32W MF 2 01005

2.2K

R19

1

5% 1/32W MF 2 01005

2.2K

R21

5% 1/32W MF 2 01005

2.2K

R92

2.2K

1 1

PP P4MM SM PP P4MM SM

PP13 PP15

10

D

BOARD_ID[3:0]={GPIO16,SPIO0_MISO,SPI0_MOSI,SPI0_SCLK}
FLOAT=LOW, PULLUP=HIGH 1010 X155 MLB <--- SELECTED

CODEC ASP

AP30 45_I2S0_MCK_R 45_AP_TO_CODEC_ASP_I2S0_BCLK AM30 AH31 10 AP_TO_CODEC_ASP_I2S0_LRCLK 10 CODEC_TO_AP_ASP_I2S0_DIN AH30 AJ30 10 AP_TO_CODEC_ASP_I2S0_DOUT AK29 AL31 AN31 AH29 AH32 AM29 AM28 AJ31 AM33 AN30 AM31 AK31 AL28 AL30 AP31 AK30 AM32 AP32 AK32 AR32

23

BASEBAND

23 23

BOOT_CONFIG[3:0]={GPIO29_CONFIG3,GPIO28_CONFIG2,GPIO25_CONFIG1,GPIO18_CONFIG0}
FLOAT=LOW, PULLUP=HIGH 0000 SPI0 0001 SPI3 0010 SPI0 W/TEST 0011 SPI3 W/TEST 0100 FMI0 2CS 0101 FMI0 4CS 0110 FMI0 4CS W/TEST 0111 RESERVED 1000 FMI1 2 CS 1001 FMI1 4 CS 1010 FMI1 4CS W/TEST 1100 FMI0/1 2/2 CS <--- SELECTED 1101 FMI0/1 4/4 CS 1110 FMI0/1 4/4 CS W/TEST 1111 RESERVED
15

45_AP_TO_SPKAMP_I2S2_MCLK

45_I2S2_MCK_R 1% 15 10 45_AP_TO_CODEC_XSP_I2S2_BCLK 1/32W MF 15 10 AP_TO_CODEC_XSP_I2S2_LRCLK 01005 15 10 CODEC_TO_AP_XSP_I2S2_DIN CODEC XSP & SPKR AMP 15 10 AP_TO_CODEC_XSP_I2S2_DOUT
1

33.2 2

R5

23

45_AP_TO_BB_I2S1_BCLK AP_TO_BB_I2S1_LRCLK BB_TO_AP_I2S1_DIN AP_TO_BB_I2S1_DOUT

I2S0_MCK I2C0_SCL I2S0_BCLK I2C0_SDA I2S0_LRCK H5P-SC58950C03 FCMSP I2S0_DIN I2C1_SCL I2S0_DOUT I2C1_SDA SYM 3 OF 12 I2S1_MCK I2C2_SCL I2S1_BCLK I2C2_SDA I2S1_LRCK I2S1_DIN SWI_DATA I2S1_DOUT DWI_CLK I2S2_MCK DWI_DI I2S2_BCLK DWI_DO I2S2_LRCK I2S2_DIN I2S2_DOUT

U1

AR7 AT4 AV6 AT3 AT9 AR8 AP5
1%

AP_TO_I2C0_SCL 13 14 15 16 20 AP_BI_I2C0_SDA 13 14 15 16 20 I2C0 AP_TO_I2C1_SCL AP_BI_I2C1_SDA
20 20

AGATHA PMU: CS35L20 AMP: AP3GDL20-BC GYRO: TRISTAR: LM3534: CHESTNUT:

1110100X ???????? 1101010X 0011010X 1100011X 0100111X

I2C1

AP3DSH ACCEL: 0011101X AK8963C COMPASS: 0001100X CT814 ALS: 0101001X

D

AP_TO_I2C2_SCL AP_BI_I2C2_SDA

11 11

I2C2

AT7 45_AP_TO_PMU_DWI_CLK_H5P 1 33.2 2 1/32W 01005 AV7 AM8

R47

MF

45_AP_TO_PMU_DWI_CLK 45_AP_TO_PMU_DWI_DI 45_AP_TO_PMU_DWI_DO

13 14 13 13 14

23

BLUETOOTH

23 23 23

45_AP_TO_BT_I2S3_BCLK AP_TO_BT_I2S3_LRCLK BT_TO_AP_I2S3_DIN AP_TO_BT_I2S3_DOUT

I2S3_MCK I2S3_BCLK I2S3_LRCK I2S3_DIN I2S3_DOUT I2S4_MCK I2S4_BCLK I2S4_LRCK I2S4_DIN I2S4_DOUT

10

COMMON PULL UP FOR BOARD_REV, BOARD_ID AND BOOT_CONFIG PINS
3

10

BOARD_INFO

1 01005

R12

2

1.00K

PP1V8

CODEC VSP
2 3 4 5 6 7 10 11 12 14 18 19 20 21

10 10

45_AP_TO_CODEC_VSP_I2S4_BCLK AP_TO_CODEC_VSP_I2S4_LRCLK CODEC_TO_AP_VSP_I2S4_DIN AP_TO_CODEC_VSP_I2S4_DOUT

C

R12 MUST WIN OVER 6X INTERNAL PULL-DOWNS THAT ARE ~100K BOARD_ID2 BOARD_ID1 BOARD_ID0 NOSTUFF FOR TRISTAR2 STUFF FOR TRISTAR
01005 1
19

AR31 SPDIF AM4 AR5 AM2 AP3 AN3 AL3 AK1 AR4 AN4 AM3 AN6 AN1 AP9 AM9 AM13 AN12 SPI0_MISO SPI0_MOSI SPI0_SCLK SPI0_SSIN SPI1_MISO SPI1_MOSI SPI1_SCLK SPI1_SSIN SPI2_MISO SPI2_MOSI SPI2_SCLK SPI2_SSIN SPI3_MISO SPI3_MOSI SPI3_SCLK SPI3_SSIN

C

3

BOARD_INFO

LCM_TO_AP_PIFA TOUCH_TO_AP_SPI1_MISO AP_TO_TOUCH_SPI1_MOSI AP_TO_TOUCH_SPI1_CLK AP_TO_TOUCH_SPI1_CS_L FCAM_TO_AP_ALS_INT_L BB_TO_AP_IPC_GPIO AP_TO_WLAN_HSIC2_RDY WLAN_TO_AP_HSIC2_RDY
10

R51

18

2

1.00K

PP1V8

11 12 14 18 19 20 21 2 3 4 5 18 6 7 10 18

GRAPE

18

23 16 14 13 12 10 4

PP1V8_SDRAM

11 23

B

A

W3 N2 M4 V3 T4 W2 P3 M3 U3 P4 L19A KEEP (STAYING) ALIVE --> 15 AP_TO_SPKAMP_BEE_GEES W1 BB_TO_AP_HSIC1_REMOTE_WAKE 23 BB_JTAG_TCK 23 AP_TO_BB_JTAG_TCK M2 RESERVED BB_JTAG_TDI 23 AP_TO_BB_JTAG_TDI R3 BB_JTAG_TMS 23 AP_TO_BB_JTAG_TMS N3 BB_JTAG_TDO 23 BB_TO_AP_JTAG_TDO M1 AC3 T3 BOARD_ID3 3 BOARD_INFO V1 AP_TO_BB_HSIC1_RDY 23 AC2 BOOT_CONFIG0 V4 KEEPACT 13 R31 23 WLAN_TO_AP_HSIC2_REMOTE_WAKE P34 TOUCH_TO_AP_INT_L 18 P33 AP_TO_LCM_RESET_L 19 LCM_TO_AP_HIFA_BSYNC P32 19 18 N32 23 AP_TO_BB_RST_L L33 BOOT_CONFIG1 P30 22 FORCE_DFU P31 DFU STATUS 21 L34 PP1V8 BOOT_CONFIG2 3 2 20 19 18 14 12 11 10 7 6 5 4 M32 21 BOOT_CONFIG3 3 2 PP1V8 20 19 18 14 12 11 10 7 6 5 4 K32 10 CODEC_TO_AP_INT_L L32 DEV_HSIC1_RDY 23 BB_TO_AP_HSIC1_RDY C22 23 AP_TO_RADIO_ON_L D22 20 GYRO_TO_AP_INT1 SM 1 C21 20 COMPASS_TO_AP_INT_2 P2MM PP D21 AP_TO_BB_WAKE_MODEM 23 C20 20 ACCEL_TO_AP_INT2 D20 RESERVED FOR NON-TRISTAR DESIGN ---> C19 11 ALS_TO_AP_INT_L D19 AP_TO_TOUCH_GRAPE_RESET_L 18 BUTTON_TO_AP_MENU_KEY_BUFF_L BUTTON_TO_AP_HOLD_KEY_BUFF_L 13 8 BUTTON_TO_AP_VOL_UP_L 13 8 BUTTON_TO_AP_VOL_DOWN_L BUTTON_TO_AP_RINGER_A 13 8 15 SPKAMP_TO_AP_INT_L PMU_TO_AP_IRQ_L (OPEN DRAIN@PMU) NEW ---> 13 AP_TO_BT_WAKE 23

220K

R52

1

13 3 13 3

5% 1/32W MF 01005 2

PP5

17 17

AP_TO_HEADSET_HS3_CTRL AP_TO_HEADSET_HS4_CTRL

GPIO0 EHCI_PORT_PWR0 GPIO1 EHCI_PORT_PWR1 GPIO2 H5P-SC58950C03 EHCI_PORT_PWR2 FCMSP GPIO3 EHCI_PORT_PWR3 GPIO4 SYM 2 OF 12 GPIO5 TMR32_PWM0 GPIO6 TMR32_PWM1 GPIO7 TMR32_PWM2 GPIO8 GPIO9 UART0_RXD GPIO10/SDIO_D3 UART0_TXD GPIO11/SDIO_D2 GPIO12/SDIO_D1 UART1_CTSN GPIO13/SDIO_D0 UART1_RTSN GPIO14/SDIO_CMD UART1_RXD GPIO15/SDIO_CLK UART1_TXD GPIO16 GPIO17 UART2_CTSN GPIO18 UART2_RTSN GPIO19 UART2_RXD GPIO20 UART2_TXD GPIO21 GPIO22 UART3_CTSN GPIO23 UART3_RTSN GPIO24 UART3_RXD GPIO25 UART3_TXD GPIO26 GPIO27 UART4_CTSN/SPI4_SSIN GPIO28 UART4_RTSN/SPI4_SCLK GPIO29 UART4_RXD/SPI4_MISO GPIO30 UART4_TXD/SPI_MOSI GPIO31 GPIO32 UART5_RXD GPIO33 UART5_TXD GPIO34 GPIO35 UART6_CTSN GPIO36 UART6_RTSN GPIO37 <50MHZ UART6_RXD GPIO38 UART6_TXD GPIO39 <50MHZ GPIO_SVSEL18_FMI AT11 GPIO_3V0 GPIO_SVSEL25_FMI AP12 GPIO_3V1 GPIO_VSEL25_I2C2 GPIO_VSEL25_SPI3

U1

AE4 BOARD_REV0 AD3 AD4 PP1V8 AE3 PP1V8 AT6 AP8 AP1 AR15 AU12 AA3 AB2 AB3 AF5 AG3 AA1 AE2 AF3 AH3 AB1 AF4 AG4 AJ4 AE1 AJ2 AH4 AK4 AJ3 AH2 AL1 AK3 AD1 AU13 AR14 AR13 AT12

21 19 20 12 14 10 11 6 7 18 2 3 4 5 20 21 2 3 4 5 6 7 10 11 12 14 18 19

BOARD_REV0 BOARD_REV1 BOARD_REV2 BOARD_REV3

23 23

10

CODEC
10 10

GYRO_TO_AP_INT2 20 VIB_PWM 8 45_AP_TO_TOUCH_CLK32K_RESET_L VIB_LDO_EN AP_TO_LEDDRV_EN
8 15

CODEC_TO_AP_SPI3_MISO AP_TO_CODEC_SPI3_MOSI AP_TO_CODEC_SPI3_CLK AP_TO_CODEC_SPI3_CS_L

18

BB_TO_AP_UART1_CTS_L 23 AP_TO_BB_UART1_RTS_L 23 BB BB_TO_AP_UART1_RXD 16 23 AP_TO_BB_UART1_TXD 16 23 TRISTAR_TO_AP_INT 13 ACCEL_TO_AP_INT1 20 TRISTAR_TO_AP_ACC_UART2_RXD 16 AP_TO_TRISTAR_ACC_UART2_TXD 16 BT_TO_AP_UART3_CTS_L AP_TO_BT_UART3_RTS_L BT_TO_AP_UART3_RXD AP_TO_BT_UART3_TXD
23 23 23 23 12 16

B

MENU & POWER / HOLD KEY
BT PP1V8_ALWAYS
1

AP_TO_BB_JTAG_TRST_L 23 AP_TO_CAM_RF_VDDCORE_EN 21 WLAN_TO_AP_UART4_RXD 23 AP_TO_WLAN_UART4_TXD 23 AP_BI_BATTERY_SWI BB_TO_AP_RESET_DET_L
13 22 23

R22

1

WIFI UART

1% 1/32W MF 2 01005
17

392K

R20

1% 1/32W MF 2 01005

392K

74AUP2G34GN SOT1115
1Y 6 2Y 4 GND 2

U25

GAS GAUGE

BUTTON_TO_AP_MENU_KEY_L BUTTON_TO_AP_HOLD_KEY_L

1 1A 3 2A

5 VCC

BUTTON_TO_AP_MENU_KEY_BUFF_L BUTTON_TO_AP_HOLD_KEY_BUFF_L

3 13

BB_TO_AP_PP_SYNC 23 AP_TO_SPKAMP_RESET_L 15 TRISTAR_TO_AP_DEBUG_UART6_RXD 16 AP_TO_TRISTAR_DEBUG_UART6_TXD 16

8

3 13

DEBUG UART: TOLERANCE 1.98V

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

H5P GPIO & CONTROL
DRAWING NUMBER

FMI, 00=1.8V | 01=3.0V | 10=3.3V
R

Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE SHEET

I2C2, 0=1.8V | 1=3.0V SPI3, 0=1.8V | 1=3.0V

3 OF 23 3 OF 46

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

12 4

PP1V2_SDRAM
1

4 DDR0_ZQ 4 DDR1_ZQ

C81

D
1

20% 6.3V 2 X5R-CERM 01005

0.1UF

R34
243
2

(DDR IMPEDANCE CONTROL)
1

R33
243
2 1% 1/32W MF 01005

1% 1/32W MF 01005

DDR0_VREF_CA DDR1_VREF_CA 4 DDR0_VREF_DQ 4 DDR1_VREF_DQ 4 DDR0_ZQ 4 DDR1_ZQ
4 4

AV4 AN34 L16 N9 AV8 AK34 B31 R2 AV3 AP34 AD33 AJ33 AN33 AU14 AU5 AU9

DDR0_RREF H5P-SC58950C03 FCMSP DDR1_RREF SYM 7 OF 12 DDR0_VDD_CKE(<1MA) DDR1_VDD_CKE(<1MA) DDR0_VREF_CA DDR1_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ DDR0_ZQ DDR1_ZQ

U1

VDDCA

(80MA) BUCK4 1P2

12 4

PP1V2_SDRAM
1 1

C388
56PF

1

C390
56PF

C68

1

5% 6.3V 2 NP0-C0G 01005

5% 6.3V 2 NP0-C0G 01005

20% 2 6.3V CERM-X5R 0402-1

10UF

C75
1UF

1

C88

20% 2 4V X6S 0204

20% 2 4V X7S 0204

0.47UF

AA34 AF1 AL33 AR33 AT1 AU16 AU7 B10 B11 B29 M34 P1 R1 A10 A11 AB33 AF2 AT33 AU3 AV16 B32 M33 T2 A3 AA2 AD2 AG2 AK2 AN2 AR2 B12 B14 B17 B20 B22 B25 B27 B30 B5 B7 B9 C33 D2 F2 G33 J2 K33 L2 N33 P2 T33 U2 W33

VSS VDD2 (340MA)

C

23 16 14 13 12 10 3

PP1V8_SDRAM
1

C883

1

20% 4V 2 X7S 0204

0.47UF

C87

20% 4V 2 X5R-CERM 0610

4.3UF

VDD1

(20MA)

12 4 2

PP1V2
1

C76

1

POR CAPS 9/1/11

20% 6.3V 2 CERM-X5R 0402-1

10UF

C85

1

20% 4V 2 X5R-CERM 0610

4.3UF

C89

20% 4V 2 X7S 0204

0.47UF

A1 A2 AT30 AV9 B15 C1 C12 C27 D18 D7 E1 E12 E23 F16 F5 G3 G32 H15 J1 K3 K30 L19 M16 N15 P10 R32 R9 T20 U6 V2 V29 W21 W23 W25 Y1 Y12 Y14 Y16 Y18 Y2 Y20 Y22 Y24 Y10 Y29 Y3 Y32 Y4 Y5 Y8

12 4 2

PP1V2

POR CAPS NOV/1/2010 CAPS FOR VDDIOD ARE SHARED WITH VDDQ

NOSTUFF

C816 1
0.1UF

20% 6.3V X5R-CERM 2 01005

G11 G13 G15 G17 G5 G7 G9 H10 H12 H14 H16 H6 H8 J10 J11 J12 J13 J14 J15 J16 J17 J5 J7 J8 J9 K6 K7 L5 L7 M6 M7 N5 N7 P6 P7 R5 R7 T6 T7 U5 U7 V6 V7 W5 W7 Y6 Y7

H5P-SC58950C03
FCMSP
SYM 9 OF 12

U1

(INCLUDED IN VDDQ) VDDIOD

VSS

19 18 14 12 11 10 7 6 5 3 2 21 20

PP1V8

1

C72

1

20% 4V 2 X5R-CERM 0610

4.3UF

C77
1UF

1

C953
15PF

20% 4V 2 X6S 0204

5% 16V 2 NP0-C0G-CERM 01005

B

VDDQ (666MA)

AA7 AB7 AC7 AD7 AE7 AF7 AG7 AH7 AJ7 AK10 AK11 AK12 AK13 AK14 AK15 AK7 AK8 AK9

VDDIO18_GRP1 (45MA)

1KOHM-25%-0.2A
1 0201 2

FL40

PP1V8_XTAL

K20 K21

VDDIO18_GRP2 (8MA)

C123 1
20% 4V X5R-CERM 2 0201

2.2UF

R29 VDDIO18_GPIO22 (7MA)

AJ28 AK28

VDDIO18_I2S0_MCK (18MA)

AT10 PVDDP_I2C2_SDA

AE13 AE15 AE17 AE19 AE21 AE23 AE25 AE27 K26 AF10 AF12 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AF6 AF8 AG1 AG11 AG13 AG15 AG17 AG19 AG21 AG23 AG25 AG27 AG28 AG29 AG30 AG31 AG32 AG33 AG34 AG5 AG6 AG9 AH10 AH12 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH33 AH5 AH6 AH8 AJ1 AJ11 AJ13 AJ15 AJ17 AJ19 AJ21 AJ23 AJ25 AJ27 AJ29 AJ32 AJ5 AJ6 AJ9 AK33 AK5 AK6 AR25 D33

D

C

B

12 4

PP1V2_SDRAM

12 4 2

PP1V2

1

A

C60

1

10% 6.3V 2 X5R 01005

0.01UF

R11
10K

1

C78

1

R14
10K

1

1% 1/32W MF 2 01005

10% 2 6.3V X5R 01005
4

0.01UF

1% 1/32W MF 2 01005

C90

1

R25

1

10% 2 6.3V X5R 01005
4

0.01UF

1% 1/32W MF 2 01005

4.7K

C94

1

R28

10% 6.3V 2 X5R 01005
4

0.01UF

1% 1/32W MF 2 01005

4.7K
SYNC_MASTER=N/A
PAGE TITLE
4

SYNC_DATE=N/A

A

DDR0_VREF_CA
1

DDR1_VREF_CA
1

DDR0_VREF_DQ
1

DDR1_VREF_DQ

H5P IO POWER
DRAWING NUMBER

C66

1

10% 6.3V 2 X5R 01005

0.01UF

R13
10K

C80

1

R24
10K

1% 1/32W MF 2 01005

10% 2 6.3V X5R 01005

0.01UF

C91

1

R27

1

1% 1/32W MF 2 01005

10% 2 6.3V X5R 01005

0.01UF

1% 1/32W MF 2 01005

4.7K

C96

1

R29

10% 6.3V 2 X5R 01005

0.01UF

1% 1/32W MF 2 01005

4.7K

Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE SHEET

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

4 OF 23 4 OF 46

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

C86 MOVED TO PP1V1_SOC FROM PP1V2, PER SEG SIMS
12

PP1V1_SOC
1

C83 MOVED TO CPUB FROM 1V2_SDRAM PER SEG SIM RESULTS

C162
10UF

1

C171
10UF

1

C86
1UF
AA10 AA12 AA14 AA26 AA8 AB11 AB13 AB15 AB9 AC10 AC12 AC14 AC26 AC8 AD11 AD13 AD15 AD9 AE10 AE12 AE14 AE26 AE8 AF11 AF13 AF15 AF27 AF9 AG10 AG12 AG14 AG26 AG8 AH11 AH13 AH15 AH27 AH9 AJ10 AJ12 AJ14 AJ26 AJ8 K11 K13 K15 K17 K23 K25 K27 K9 L10 L12 L14 L18 L20 L22 L24 L26 L8 M11 M13 M15 M17 M19 M21 M23 M25 M27 M9 N10 N12 N14 N16

D

12

PP1V1_CPUB
1

C83
1UF

1

C127
4.3UF

20% 4V 2 X6S 0204

20% 4V 2 X5R-CERM 0610

0.47UF
20% 6.3V CERM 0402

C135

C151
1UF
20% 4V CERM 0402

1

C158

20% 4V 2 X7S 0204

0.47UF

1

3 2 4

1 2 4

3

12

CPU0_SW_S

1

0.00 2
0% 1/32W MF 01005 1

R46

CPU0_SENSE

SHORT-10L-0.1MM-SM 1 2

XW1

AA16 AA18 AA20 AA22 AA24 AC16 AC18 AC20 AC22 AC24

H5P-SC58950C03
SYM 8 OF 12 VDD_CPUB (716MA)

U1

FCMSP

12

PP1V1_CPU0
1

C104
1UF

C106
4.3UF

1

C103
1UF

20% 2 4V X6S 0204

20% 4V 2 X5R-CERM 0610

20% 4V 2 X6S 0204

0.47UF
20% 6.3V CERM 0402

C132

C113
1UF
20% 4V CERM 0402

1

C140

1

20% 4V 2 X7S 0204

0.47UF

C146
4.3UF

20% 4V 2 X5R-CERM 0610

1 C104 MOVED TO CPU0 FROM PP1V8 PER SEG SIMS 2 4

3

1 2 4

3

12

CPU1_SW_S

1

0.00 2
0% 1/32W MF 01005 1

R53

XW3 SHORT-10L-0.1MM-SM
CPU1_SENSE 1
2

AE16 AE18 AE20 AF19 AG16 AG18 AG20 AH17 AH19 AJ16 AJ20

VDD_CPU0 (1500MA)

12

PP1V1_CPU1

C

C101
1UF

1

C108
4.3UF

POR CAPS 9/1/2011

20% 2 4V X6S 0204

20% 2 4V X5R-CERM 0610

0.47UF
20% 6.3V CERM 0402

C133

C114
1UF
20% 4V CERM 0402

1

C142

1

20% 2 4V X7S 0204

0.47UF

C152
4.3UF

20% 2 4V X5R-CERM 0610

1 2 4

3

1 2 4

3

AE22 AE24 AF21 AF23 AG22 AG24 AH21 AH23 AH25 AJ24

VDD_CPU1 (1500MA)

12

PP1V0_SRAM
1

C100
10UF

1

C112
4.3UF

1

C117
4.3UF

1

C745
1UF

1

C145
1UF

1

C154

1

POR CAPS 5/6/2011

20% 6.3V 2 CERM-X5R 0402-1

20% 2 4V X5R-CERM 0610

20% 2 4V X5R-CERM 0610

20% 2 4V X6S 0204

20% 2 4V X6S 0204

20% 4V 2 X7S 0204

0.47UF

C746

20% 2 4V X7S 0204

0.47UF

AB17 AB19 AB21 AB23 AB25 AD17 AD19 AD21 AD23 AD25 AF17 AF25

VDD_SRAM (400MA)

VSS

R953

B

6

PP3V0_NAND_XW

1

0.00 2
0% 1/32W MF 01005

PP3V0_IO
1

19 18 14 12 11 10 7 6 5 4 3 2 21 20

PP1V8

C148
56PF

1

C139

5% 6.3V 2 NP0-C0G 01005

20% 6.3V 2 X5R 0201

0.22UF

F19 F20 G30 AR10

PVDDP_FAST_SCAN_CLK (2MA) VDDIO30_FAST_SCAN_CLK (40MA) VDDIO30_USB11_DM (5MA) VDDIO30_GPIO_3V0 (7MA)

AN10 VDDIOD0 (2MA SPI3) AP11 VDDIOD1 (2MA I2C2)

AB27 AC27 AD27

VDDIOD2 (45MA NAND 1CH)

V27 W27 Y26

VDDIOD3 (45MA NAND 1CH)

NAND POWER GROUP
POR CAPS 12/14/2011 THERE WERE 10X 0.01UF HERE BUT THEY WERE NOT NEEDED PER P.CODD 1/6/11
19 18 14 12 11 10 7 6 5 4 3 2 21 20

AJ18 VDD_ANA0(5MA) AJ22 VDD_ANA1 (5MA) Y17 VDD_ANA_TMPSADC0 K18 VDD_ANA_TMPSADC1

PP1V8
1

A

C111
10UF

1

C115
4.3UF

1

C134
10UF

1

C155
10UF

1

C161
10UF

20% 6.3V 2 CERM-X5R 0402-1

20% 4V 2 X5R-CERM 0610

20% 6.3V 2 CERM-X5R 0402-1

20% 6.3V 2 CERM-X5R 0402-1

20% 6.3V 2 CERM-X5R 0402-1

A14 A15 A16 A17 A18 A20 A23 A26 A29 A33 A34 A4 A5 A6 A7 A8 A9 AA11 AA13 AA15 AA17 AA19 AA21 AA23 AA25 AA33 AA4 AA5 AA6 AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AB26 AB29 AB32 AB4 AB5 AB6 AB8 AC1 AC11 AC13 AC15 AC17 AC19 AC21 AC23 AC25 AC34 AC4 AC5 AC6 AC9 AD10 AD12 AD14 AD16 AD18 AD20 AD22 AD24 AD26 AD29 AD32 AD5 AD6 AD8 AE11 AE5 AE6 AE9 AK27 AL13 AM22 AN21 AP16 AP33 AR26 AT19

20% 6.3V 2 CERM-X5R 0402-1

20% 6.3V 2 CERM-X5R 0402-1

20% 4V 2 X6S 0204

H5P-SC58950C03
FCMSP
SYM 10 OF 12

U1

1

C164
4.3UF

1

C172
4.3UF

20% 2 4V X5R-CERM 0610

20% 2 4V X5R-CERM 0610

C166
1UF
20% 4V CERM 0402

1

C175
1UF

1

C179
1UF

20% 4V 2 X6S 0204

20% 4V 2 X6S 0204

1 2 4

3

0.47UF

C169
20% 6.3V CERM 0402

1

C181
1UF

1

C177
1UF

C173
1UF
20% 4V CERM 0402

20% 2 4V X6S 0204

20% 2 4V X6S 0204

1 3 2 4

3

1 2 4

1

C178
0.1UF

1

C183
0.1UF

C174
1UF
20% 4V CERM 0402

20% 6.3V 2 X5R-CERM 01005

20% 6.3V 2 X5R-CERM 01005

1 2 4

3

VDD

(VDD_SOC 3700MA)

VDD

C181,C177,C174 CHANGED FROM 0.47UF TO 1UF PER SEG - ZHENGGANG - 09/01/12 PRE-PROTO1

12

BUCK2_FB

SHORT-10L-0.1MM-SM 1 2

XW4

N18 N20 N22 N24 N26 P11 P13 P15 P17 P19 P21 P23 P25 P27 P9 R10 R12 R14 R16 R18 R20 R22 R24 R26 R8 T11 T13 T15 T17 T19 T21 T23 T25 T27 T9 U10 U12 U14 U16 U18 U20 U22 U24 U26 U8 V11 V13 V15 V17 V19 V21 V23 V25 V9 W10 W12 W14 W16 W18 W20 W22 W24 W26 W8 Y11 Y13 Y15 Y9 Y19 Y21 Y23 Y25

D

C

B

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

H5P SOC/CPU/SRAM PWR
DRAWING NUMBER

Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE SHEET

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

5 OF 23 5 OF 46

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

NAND
D
FOR NAND CURRENT MEASUREMENT
5

D
XW2 SM
1 1 2
PP3V0_NAND
12

PP3V0_NAND_XW

1

C105

1

20% 4V 2 X7S 0204

0.47UF

C3

20% 4V 2 X6S 0204

1UF

1

C185
1UF

1

C182
10UF

C307
10UF

1

C209
10UF

1

C187
10UF

20% 2 4V X6S 0204

20% 6.3V 2 CERM-X5R 0402-1

OMIT_TABLE

20% 6.3V 2 CERM-X5R 0402-1

OMIT_TABLE

20% 6.3V 2 CERM-X5R 0402-1

OMIT_TABLE

20% 6.3V 2 CERM-X5R 0402-1

OMIT_TABLE PP1V8

PP1V2_NAND_VDDI NOSTUFF
1
2 3 4 5 6 7 10 11 12 14 18 19 20 21

C50

1

20% 4V 2 X5R-CERM 0201
19 18 14 12 11 10 7 6 5 4 3 2 21 20

2.2UF

C26

1

C95

1

20% 4V 2 X5R-CERM 0201

2.2UF

1000MA

500MA

20% 6.3V 2 CERM-X5R 0402-1

10UF

C107
1UF

1

C627
4.3UF

1

C109
15UF

1

20% 4V 2 X6S 0204

20% 4V 2 X5R-CERM 0610

20% 4V 2 X5R 0402

C605

20% 4V 2 X7S 0204

0.47UF

POR CAPS 1/7/11

PP1V8 OB8
1

5% 1/32W MF 2 01005
6

100K

5% 1/32W MF 2 01005

100K

10% 6.3V 2 X5R 01005

0.01UF

1% 1/32W MF 2 01005

OMIT

VDDI FMI0_IO<0> 6 FMI0_IO<1> 6 FMI0_IO<2> 6 FMI0_IO<3> 6 FMI0_IO<4> 6 FMI0_IO<5> 6 FMI0_IO<6> 6 FMI0_IO<7>
6

B6 F2 M6 VCC

50K

FMI0_CEN0

XXNM-XGBX8-MLC-PPN1.5-ODP

C
6 6 6 6 6 6 6 6

AE29 AE30 AE32 AE34 AA29 AB30 AA30 AB28 AA28 AA31 AB34 AB31 AD31 AE31 AD34 AE33 AC28 AC31 6 FMI0_ALE AD30 6 FMI0_CLE 6 FMI0_WE_L AC29 AC30 AC33 AC32 AD28 FMI0_DQVREF PP1V8

FMI0_CEN0 FMI1_CEN0 FMI0_CEN1 FMI1_CEN1 H5P-SC58950C03FMI1_CEN2 FMI0_CEN2 FCMSP FMI0_CEN3 FMI1_CEN3 SYM 4 OF 12 FMI0_CEN4 FMI1_CEN4 FMI0_CEN5 FMI1_CEN5 FMI0_CEN6 FMI1_CEN6 FMI0_CEN7 FMI1_CEN7

U1

W28 Y34 AA32 Y33 T34 V31 U34 U31 U33 U29 V32 W32 W34 W31 Y30 Y31 U28 W29 Y28 V28 W30 V34 V33 V30

FMI1_CEN0 6
1

FMI0_DQVREF 6

N1 N7 OC8 OD8 OE0 OF8 G0 OA8 VCCQ
1

1

R78

1

R82

1

C136

R137

C144

1

10% 6.3V 2 X5R 01005

0.01UF

R143
50K

1% 1/32W MF 2 01005

G3 H2 J3 K2 L5 K6 J5 H6 G1 J1 L1 N3 N5 L7 J7 G7

IO0-0 IO1-0 IO2-0 IO3-0 IO4-0 IO5-0 IO6-0 IO7-0 IO0-1 IO1-1 IO2-1 IO3-1 IO4-1 IO5-1 IO6-1 IO7-1

LGA-12X17

U4

CE0* CLE0 ALE0 WE0*

A5 A3 C1 E3

FMI0_CEN0 FMI0_CLE FMI0_ALE FMI0_WE_L

6 6 6 6

R48

5% 1/32W MF 2 01005

100K

NOSTUFF

C

RE0 B4 RE0* C7 DQS0 H4 DQS0* F4 R/B0* E5 CE1* CLE1 ALE1 WE1* C5 C3 D2 E1

45_FMI0_RE_L 6 45_FMI0_DQS
6

1

R160
100K

FMI0_IO<0> FMI0_IO<1> FMI0_IO<2> FMI0_IO<3> FMI0_IO<4> FMI0_IO<5> FMI0_IO<6> FMI0_IO<7>

FMI0_IO0 FMI0_IO1 FMI0_IO2 FMI0_IO3 FMI0_IO4 FMI0_IO5 FMI0_IO6 FMI0_IO7 FMI0_WENN/RE_P FMI0_ALE FMI0_CLE FMI0_WEN FMI0_REN FMI0_DQS FMI0_DQSN FMI0_DQVREF

FMI1_IO0 FMI1_IO1 FMI1_IO2 FMI1_IO3 FMI1_IO4 FMI1_IO5 FMI1_IO6 FMI1_IO7 FMI1_WENN/RE_P FMI1_ALE FMI1_CLE FMI1_WEN FMI1_REN FMI1_DQS FMI1_DQSN FMI1_DQVREF

FMI1_IO<0> FMI1_IO<1> FMI1_IO<2> FMI1_IO<3> FMI1_IO<4> FMI1_IO<5> FMI1_IO<6> FMI1_IO<7>

5% 1/32W MF 2 01005

NAND_RDYBSY0_L FMI1_CEN0 FMI1_CLE FMI1_ALE FMI1_WE_L
6 6 6 6

NOSTUFF

FMI1_ALE 6 FMI1_CLE 6 FMI1_WE_L 6 45_FMI1_RE_L 6 45_FMI1_DQS 6 FMI0_DQVREF PP1V8
6

RE1 D4 RE1* D6 DQS1 M4 DQS1* K4 R/B1* E7

45_FMI1_RE_L 6 45_FMI1_DQS
6

6 6

45_FMI0_RE_L 45_FMI0_DQS
6

NAND_RDYBSY1_L FMI0_DQVREF PPN_ZQ
6

19 18 14 12 11 10 7 6 5 4 3 2 21 20 6

AA27 PVDDP_FMI0 AE28 FMI0_VREF

PVDDP_FMI1 U27 FMI1_VREF Y27

2 3 4 5 6 7 10 11 12 14 18 19 20 21 6

PP19 P2MM
SM PP

PP17 P2MM
SM PP

VREF G5 NAND_TCKC NAND_TMSC OA0 TCKC OB0 TMSC ZQ A1 VSS B2 F6 L3 VSSQ A7 M2 OC0 OD0 OE8 OF0 G8

1

1

243
1% 1/32W MF 01005

R8

2

FMI0_DQVREF

FMI0_DQVREF

1

B

B

PP2 PP3 PP14

P4MM
SM SM SM

PP PP PP

1 1 1

FMI0_IO<0> 45_FMI0_RE_L 45_FMI0_DQS

NOTE: NAND PADS SHOULD BE SHIELDED FROM TRACES WITH A GROUND PLANE
6 6

P4MM P4MM

6

A

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

H5P W/ NAND
DRAWING NUMBER

Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE SHEET

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

6 OF 23 6 OF 46

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

C

B

AN29 LPDP_PAD_AVSS2 AN28 LPDP_PAD_AVSS1 AN27 LPDP_PAD_AVSS0

DP_PAD_AVSS_AUX

A

DP_PAD_AVSSP0

DP_PAD_AVSSX

DP_PAD_AVSS1 DP_PAD_AVSS0

DAC_AVSS18A2

DP_PAD_DVSS

DAC_AVSS18D

AL10 AL11 AL12 AL14 AL15 AL29 AL32 AL4 AL5 AL6 AL7 AL8 AL9 AM1 AM17 AM18 AM26 AM5 AM6 AM7 AN11 AN14 AN17 AN18 AN19 AN20 AN22 AN23 AN24 AN25 AN26 AN32 AN5 AN7 AN8 AP10 AP13 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP4 AP7 AR1 AR11 AR17 AR18 AR19 AR20 AR21 AR22 AR23 AR24 AR27 AR28 AR29 AT14 AT16 AT17 AT18 AT2 AT20 AT21 AT22 AT23 AT24 AT25 AT26 AT27 AT28 AT29 AT31 AT32 AT5 AT8 AU1 AU2 AU33 AU34 AU4 AV1 AV14 AV2 AV33 AV34 AV5

AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26

(2MA) MIPI0D_VDD10_PLL AM21 MIPI1D_VDD10_PLL AM23

(2MA) MIPI0D_VDD18 AM19 MIPI1D_VDD18 AM25

1

H5P-SC58950C03
FCMSP
SYM 11 OF 12

H5P-SC58950C03
FCMSP
SYM 12 OF 12

C53

20% 6.3V 2 X5R-CERM 01005

0.1UF

1

C57

1

C266
4.3UF

MIPI0D_VREG_0P4V AM20 MIPI1D_VREG_0P4V AM24

U1

AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26

VSS

VSS

B1 B13 B16 B18 B19 B2 B21 B23 B24 B26 B28 B3 B33 B34 B4 B6 B8 C10 C11 C13 C14 C15 C16 C17 C18 C2 C23 C24 C25 C26 C28 C29 C3 C30 C31 C32 C4 C5 C6 C7 C8 C9 D1 D10 D11 D12 D13 D14 D15 D16 D17 D23 D24 D25 D26 D27 D28 D29 D3 D30 D31 D32 D4 D5 D6 D8 D9 E10 E11 E13 E14 E15 E16 E17 E18 E19 E2 E20 E21 E22 E24 E25 E26 E28 E3 E30 E4 E5 E6 E7 E8 E9

E31 E32 F1 F10 F11 F12 F13 F14 F15 F17 F18 F21 F22 F27 F3 F30 F31 F32 F4 F6 F7 F8 F9 G1 G10 G12 G14 G16 G2 G22 M31 G31 G34 G4 G6 G8 H1 H11 H13 H17 H18 H19 H2 H20 H21 H22 H3 H30 H31 H32 H33 H4 H5 H7 H9 J27 J3 J30 J31 J32 J33 J4 J6 K1 K10 K12 K14 U30 K19 K2 K22 K24 K31 K4 K5 K8 L1 L11 L13 L15 L17 L21 L23 L25 L27 L3 L31 L4 L6 L9 M10 M12

U1

VSS

VSS

M14 M18 M20 M22 M24 M26 M5 M8 N1 N11 N13 N17 N19 N21 N23 N25 N27 N31 N34 N4 N6 P12 P14 P16 P18 P20 P22 P24 P26 P5 P8 R11 R13 R15 R17 R19 R21 R23 R25 R27 R30 R33 R34 R4 R6 T1 T10 T12 T14 T16 T18 T22 T24 T26 T28 T29 T30 T31 T32 T5 T8 U1 U11 U13 U15 U17 U19 U21 U23 U25 U32 U4 U9 V10 V12 V14 V16 V18 V20 V22 V24 V26 V5 V8 W11 W13 W15 W17 W19 W4 W6 W9

12 7 2

PP1V0 MIPI0D_VREG MIPI1D_VREG
1 1 1

PP1V8

2 3 4 5 6 7 10 11 12 14 18 19 20 21

C191
0.1UF

20% 6.3V 2 X5R-CERM 01005

0.1UF

20% 4V 2 X5R-CERM 0610

2200PF

C6

C7

MIPI_VDD10 (28MA)

10% 6.3V X5R-CERM 2 01005

10% 6.3V 2 X5R-CERM 01005

2200PF

20% 2 6.3V X5R-CERM 01005

PP1V8
1

2 3 4 5 6 7 10 11 12 14 18 19 20 21

D

R37

1

21 21

90_CAM0_TO_AP_MIPI_DATA0_P 90_CAM0_TO_AP_MIPI_DATA0_N 90_CAM0_TO_AP_MIPI_DATA1_P 90_CAM0_TO_AP_MIPI_DATA1_N 90_CAM0_TO_AP_MIPI_DATA2_P 90_CAM0_TO_AP_MIPI_DATA2_N 90_CAM0_TO_AP_MIPI_DATA3_P 90_CAM0_TO_AP_MIPI_DATA3_N 90_CAM0_TO_AP_MIPI_CLK_P 90_CAM0_TO_AP_MIPI_CLK_N 90_AP_TO_LCM_MIPI_DATA0_P 90_AP_TO_LCM_MIPI_DATA0_N 90_AP_TO_LCM_MIPI_DATA1_P 90_AP_TO_LCM_MIPI_DATA1_N 90_AP_TO_LCM_MIPI_DATA2_P 90_AP_TO_LCM_MIPI_DATA2_N 90_AP_TO_LCM_MIPI_DATA3_P 90_AP_TO_LCM_MIPI_DATA3_N

ISP0_FLASH H5P-SC58950C03 ISP0_PRE_FLASH FCMSP AU21 MIPI0C_DPDATA0 ISP0_SCL SYM 5 OF 12 AV21 MIPI0C_DNDATA0 ISP0_SDA AU20 MIPI0C_DPDATA1 AV20 MIPI0C_DNDATA1 AU18 MIPI0C_DPDATA2 AV18 MIPI0C_DNDATA2 AU17 MIPI0C_DPDATA3 AV17 MIPI0C_DNDATA3 AU19 MIPI0C_DPCLK AV19 MIPI0C_DNCLK AU26 MIPI0D_DPDATA0 AV26 MIPI0D_DNDATA0 AU25 MIPI0D_DPDATA1 AV25 MIPI0D_DNDATA1 AU23 MIPI0D_DPDATA2 AV23 MIPI0D_DNDATA2 AU22 MIPI0D_DPDATA3 AV22 MIPI0D_DNDATA3 AU24 MIPI0D_DPCLK AV24 MIPI0D_DNCLK ISP1_FLASH ISP1_PRE_FLASH ISP1_SCL ISP1_SDA

AR3 MIPI_VSYNC

U1

AR12 AM11 AR6 AH1 AU11 AM12 AL2 AU6

CAM0_TORCH

15

5% 1/32W MF 2 01005

1.00K

R39

1

5% 1/32W MF 2 01005

1.00K

R41

1

5% 1/32W MF 2 01005

1.00K

R42

5% 1/32W MF 2 01005

1.00K

AP_TO_CAM_RF_SCL AP_BI_CAM_RF_SDA

15 21 15 21

21 21

AP_TO_CAM_FF_SCL AP_BI_CAM_FF_SDA

11 11

21 21

21 21

45_AP_TO_CAM_RF_CLK_R SENSOR0_CLK AN9 SENSOR0_RST AP6 AP_TO_CAM_RF_SHUTDOWN 21 SENSOR1_CLK AP2 45_AP_TO_CAM_FF_CLK_R SENSOR1_RST AM10 AP_TO_CAM_FF_SHUTDOWN MIPI1D_DNDATA0 AV27 MIPI1D_DPDATA0 AU27 MIPI1D_DNDATA1 AV29 MIPI1D_DPDATA1 AU29 MIPI1D_DNCLK AV28 MIPI1D_DPCLK AU28 MIPI1C_DPDATA0 AU30 MIPI1C_DNDATA0 AV30 MIPI1C_DPDATA1 AU32 MIPI1C_DNDATA1 AV32 MIPI1C_DPCLK AU31 MIPI1C_DNCLK AV31 MIPI_VSS 90_CAM1_TO_AP_MIPI_CLK_P 90_CAM1_TO_AP_MIPI_CLK_N
11 11

R38 1
1% MF

2 1/32W 01005

33.2

45_AP_TO_CAM_RF_CLK 21

MAIN CAMERA

R40 1
1% 1

33.2 2
1/32W 01005 1

45_AP_TO_CAM_FF_CLK 11

21 21

11

FF CAMERA

1

SHUTDOWN IS ALSO RESET CAM1

C259
56PF

19 19

5% 6.3V 2 NP0-C0G 01005

C274
56PF

1

C280
56PF

MF

C284
56PF

5% 6.3V 2 NP0-C0G 01005

5% 6.3V 2 NP0-C0G 01005

5% 6.3V 2 NP0-C0G 01005

19 19

C
90_CAM1_TO_AP_MIPI_DATA0_P 90_CAM1_TO_AP_MIPI_DATA0_N
11 11

19 19

19 19

19 19

90_AP_TO_LCM_MIPI_CLK_P 90_AP_TO_LCM_MIPI_CLK_N

LPDP NOT USED, NO CAP NEEDED ON THIS PIN PP1V8
12 7 2

PP1V0 LPDP_PAD_CMN_AVDDH AL27 LPDP_PAD_CMN_AVDD AM27 LPDP_PAD_AUX_AVDD AP27 LPDP_PAD_LN1_AVDD AP29 LPDP_PAD_LN0_AVDD AP28 DP_PAD_DVDD J25 (15MA) DP_PAD_AVDDX G25 (11MA) DP_PAD_AVDDP0 G24 (1MA) DP_PAD_AVDD1 G23 (2X 65MA) DP_PAD_AVDD0 J23 DP_PAD_AVDD_AUX J24 (8MA) DAC_AVDD18D L30 (12MA)

2 3 4 5 6 7 10 11 12 14 18 19 20 21

20% 6.3V X5R-CERM 2 01005

0.1UF

C58 1

DAC_AVDD18A N29 (12MA)

1

C268
0.1UF

20% 2 6.3V X5R-CERM 01005

B

N30 DAC_VREF P29 DAC_IREF P28 DAC_COMP

DAC_OUT3 H34 DAC_OUT2 J34 DAC_OUT1 K34

H5P-SC58950C03 (0MA LPDP)
SYM 6 OF 12

U1

FCMSP

G26 DP_PAD_DC_TP F26 DP_PAD_R_BIAS DP_HPD AU8 AV12 LPDP_HPD AT34 LPDP_PAD_AUXP AR34 LPDP_PAD_AUXN AM34 LPDP_PAD_TX0P AL34 LPDP_PAD_TX0N AJ34 LPDP_PAD_TX1P AH34 LPDP_PAD_TX1N AR30 LPDP_PAD_R_BIAS DP_PAD_TX0P A25 DP_PAD_TX0N A24 DP_PAD_TX1P A22 DP_PAD_TX1N A21

DP_PAD_AUXP A28 DP_PAD_AUXN A27

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

H5P VIDEO
DRAWING NUMBER

Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE SHEET

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

H25

F25

F24

F23 H23

H24

M30

N28

7 OF 23 7 OF 46

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

BUTTON FLEX
D

(VIBE DRIVER, BUTTONS, ANC REF MIC, STROBE, STROBE_NTC)
120-OHM-210MA
2 01005 1 1

FL21

CAM_RF_TO_STROBE_NTC

15

STROBE: STROBE NTC

C397
56PF

5% 6.3V 2 NP0-C0G 01005

D
FL47
01005 1

120-OHM-210MA
8

CODEC_TO_MIC2_BIAS_CONN 1
1

2

PP_CODEC_TO_MIC2_3_BIAS

10 11

WIFI FLEX PAC: VDD (3.0V)

R977
16 12

PP3V0_ALWAYS

1

0.00 2
0% 1/32W MF 01005

C45

PP3V0_ALWAYS_CONN

8

5% 6.3V 2 NP0-C0G 01005

56PF

C216
1.0UF

NO_XNET_CONNECTION=TRUE

20% 6.3V 2 X5R 0201-1

1

C697
56PF

ON MLB ----> 516S1040 PLUG 516S1041 RCPT (FLEX)

5% 6.3V 2 NP0-C0G 01005

105847-018
M-ST-SM

J2

2 SHORT-10L-0.1MM-SM
NO_XNET_CONNECTION=TRUE

MIC2 (ANC REF MIC): MIC2/3 BIAS, MIC2_P,_N

XW41

20 19

1

9 8 22 9 8 8

BUTTON_TO_AP_HOLD_KEY_CONN_L MIC2_TO_CODEC_N MIC2_TO_CODEC_P CODEC_TO_MIC2_BIAS_CONN

1 3 5 7 9 11 13 15

2 4 6 8 10 12 14

CAM_RF_TO_STROBE_NTC_CONN

MIC2_TO_CODEC_N 8 MIC2_TO_CODEC_P 8

9 9 22

BB_TO_ANT_PAC_SPI_SCLK_BUTTON_CONN

BB_TO_ANT_PAC_SPI_MOSI_BUTTON_CONN PP_VIBE 8
8

C244 1
5% 6.3V NP0-C0G 2 01005

56PF

C
120-OHM-210MA
3

BUTTON_TO_AP_RINGER_A_CONN

FL3
01005

BUTTON_TO_AP_VOL_UP_CONN_L BUTTON_TO_AP_VOL_DOWN_CONN_L

16 PP3V0_ALWAYS_CONN

17

18 21 22

BB_TO_ANT_PAC_SPI_CS_BUTTON_CONN_L

120-OHM-210MA
1 01005 2

FL71

C
BB_TO_ANTENNA_PAC_SPI_SCLK 23

BUTTON_TO_AP_HOLD_KEY_L

1

2 1

C314 1
100PF
5% 10V NP0-C0G 2 01005

DZ1

12V-33PF
01005-1

120-OHM-210MA
1 01005 2

FL70

2

BB_TO_ANTENNA_PAC_SPI_MOSI 23

WIFI FLEX PAC: PAC SPI BUS

120-OHM-210MA
13 3

FL7
01005

120-OHM-210MA
1 1 2 01005

FL72

BUTTON_TO_AP_RINGER_A

1

2

C313 1
100PF

DZ7

BB_TO_ANTENNA_PAC_SPI_CS_L 23

BUTTONS: RINGER, HOLD, VOL_UP/DOWN
13 3

5% 10V NP0-C0G 2 01005

12V-33PF 01005-1

C382 1 C384
56PF
5% 6.3V 01005 2

1

1

56PF

C383
56PF

2

5% 6.3V 01005 2

5% 2 6.3V 01005

120-OHM-210MA
BUTTON_TO_AP_VOL_DOWN_L
1 01005 2 1

FL8

C311 1
100PF
5% 10V NP0-C0G 2 01005

DZ2

PGND_VIBE_RETURN

VIBE RETURN
8

12V-33PF 01005-1

2

C1201 1
100PF
5% 16V NP0-C0G 2 01005

B

120-OHM-210MA
13 3

FL46
01005

BUTTON_TO_AP_VOL_UP_L

1 1

2 1

B
DZ3
12V-33PF 01005-1
PP_STRB_DRIVER_TO_LED
1
15

C197
100PF

5% 10V NP0-C0G 2 01005

2

C208
27PF

1

C241
100PF

STROBE: LED COOL

5% 16V 2 NP0-C0G 01005

5% 16V 2 NP0-C0G 01005

NOSTUFF LP5907UVX-3.3V USMD A1 VIN VOUT A2PP3V3_VIB B1 VEN

U70

NOSTUFF
1

23 22 15 12

PP_BATT_VCC VIB_LDO_EN

0.00 2
0% 1/32W MF 01005 1

R70

PP_VIBE

8

3

C118
4.7UF

GND B2

C120
100PF

1

100K

R69

1

5% 1/32W MF 01005 2
12

R970 TO VIB NET MINIMIZE DCR

20% 6.3V 2 X5R 0402

5% 16V NP0-C0G 2 01005

R970
PP3V0_VIBE
1 0% 1/32W MF 01005

NOSTUFF

0.00 2

K

D3 LLP-DFN1006-2
BAS40LP
PGND_VIBE_RETURN

VIBE DRIVE

A

8

A
XW80 SM
3

3

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

D
VIBE_PWM_G
1

VIB_PWM
1

1

2

G S

Q7

BUTTON FLEX B2B
DRAWING NUMBER

DMN3730UFB4
DFN1006H4-3
SYM_VER_1
R

Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

051-9584 2.0.0

SIZE

D

R9401
10K
2

REVISION BRANCH PAGE SHEET

1% 1/32W MF 2 01005

8 OF 23 8 OF 46

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

L67 AUDIO CODEC
D D

AUDIO I/O
(ANALOG MIC IN, DIG MIC IN, HPOUT, LINEOUT, RECEIVER OUT, MIKEYBUS)
TO DO: REVIEW AUDIO MIC PATHS, WHICH BIAS OUTPUT USED FOR WHICH MIC, WHICH INPUT FOR WHICH MIC, ETC.

C222
0.1UF
1 20% 4V 2 X5R 01005

VOICE MIC

22 17

MIC1_TO_CODEC_P MIC1_TO_CODEC_N

17

C223
0.1UF
1 20% 4V 2 X5R 01005

1

C227
56PF

1

C230
56PF

5% 6.3V 2 NP0-C0G 01005

5% 6.3V 2 NP0-C0G 01005

U21
1 20% 4V 2 X5R 01005

HEADPHONE MIC

17

EXTMIC_TO_CODEC_P EXTMIC_TO_CODEC_N

17

C221
0.1UF
1 20% 4V 2 X5R 01005 1

EXTMIC_TO_CODEC_L67_P EXTMIC_TO_CODEC_L67_N

F4 AIN2+ HEADPHONE F3 AIN2- MIC F2 AIN3+ ANALOG F1 AIN3- MIC IN

CS42L67-CWZR-A0

C

C220
0.1UF
MIC1_TO_CODEC_L67_P MIC1_TO_CODEC_L67_N

SYM 1 OF 3 G2 AIN1+ PRIMARY G1 AIN1- (VOICE) MIC

WLCSP

AOUT1+ K7 AOUT1- L7 AOUT2+ L5 AOUT2- K5
LINEOUT_REF K8 LINEOUTA J8 LINEOUTB H8

50PF LIMIT ON AOUTX PINS CODEC_TO_RCVR_P 11 CODEC_TO_RCVR_N 11 CODEC_TO_HAC_P CODEC_TO_HAC_N
11 11

C

C226
56PF

1

C229
56PF
RCVR_TO_CODEC_RCVR_TEST_L67 N/C,INTERNAL WEAK BIAS TO VCM MIC2_TO_CODEC_L67_P MIC2_TO_CODEC_L67_N

5% 6.3V 2 NP0-C0G 01005

5% 6.3V 2 NP0-C0G 01005

E4 AIN4+ ANC REF MIC2 E3 AIN4E1 AIN5+ ANC E2 AIN5- REF MIC1 D1 AIN6+ ANC D2 AIN6- ERROR MIC D3 AIN7+ ANALOG D4 AIN7- LINEIN C1 AIN8+ ANALOG LINEIN C2 AIN8A6 DMIC1_SD B6 DMIC1_SCLK A3 DMIC2_SD A2 DMIC2_SCLK

HPOUTA J9 HPOUTB K9 HS3 K1 HS4 L2 HS3_REF L9 HS4_REF L8 HPDETECT G8 DN G10 DP F10 MBUS_REF F11

CODEC_TO_HPHONE_L CODEC_TO_HPHONE_R CODEC_TO_HPHONE_HS3 CODEC_TO_HPHONE_HS4
17

17 17

HEADPHONES

C224
0.1UF
1 20% 4V
22 8

2 X5R 01005

MIC3_TO_CODEC_L67_P MIC3_TO_CODEC_L67_N HPHONE_TO_CODEC_HPHONE_TEST_L67 N/C,INTERNAL WEAK BIAS TO VCM

C235
56PF

1

C236
56PF

1

17

CODEC_TO_HPHONE_HS3_REF 17 CODEC_TO_HPHONE_HS4_REF 17 HPHONE_TO_CODEC_DET
17

5% 6.3V NP0-C0G 2 01005

5% 6.3V NP0-C0G 2 01005

MIC2_TO_CODEC_P MIC2_TO_CODEC_N

ANC REF MIC

8

C225
0.1UF
1 20% 4V 2 X5R 01005 1

HAC_TO_CODEC_TEST_L67 N/C,INTERNAL WEAK BIAS TO VCM

C228
56PF

1

C231
56PF

C138
100PF
1 2 5% 10V NP0-C0G 01005 1

5% 2 6.3V NP0-C0G 01005

5% 6.3V 2 NP0-C0G 01005

OMIT_TABLE

R102

B
ANC ERROR MIC
22 11

0.1UF
1 20% 4V 2 X5R 01005

C55

1

15.0 2
MF 01005

90_CODEC_BI_TRISTAR_MIKEYBUS_L67_N 90_CODEC_BI_TRISTAR_MIKEYBUS_L67_P

5% 1/32W

C51

R103
1 5% 1/32W

MIC3_TO_CODEC_P MIC3_TO_CODEC_N

15.0 2
MF 01005

5% NOSTUFF 10V 2 NP0-C0G 01005

100PF

90_CODEC_BI_TRISTAR_MIKEYBUS_N 90_CODEC_BI_TRISTAR_MIKEYBUS_P

B
16

MIKEY TO TRISTAR
16

11

0.1UF
1 20% 4V 2 X5R 01005 1

C61

C64

1

5% 6.3V 2 NP0-C0G 01005

56PF

C65

OMIT_TABLE

C143
100PF
1 2 5% 10V NP0-C0G 01005

5% 6.3V 2 NP0-C0G 01005

56PF

R102, R103 VALUE CONTROLLED VIA BOMOPTION 15OHM FOR TRISTAR, 20OHM FOR TRISTAR2

0.01UF
11

C354
1 2 10% 6.3V X5R 01005

RCVR_TO_CODEC_RCVR_TEST

0.01UF
17

C356
1 2 10% 6.3V X5R 01005

HPHONE_TO_CODEC_HPHONE_TEST

A
11

0.01UF
HAC_TO_CODEC_TEST
1 2 10% 6.3V X5R 01005

C362

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

L67 AUDIO CODEC (1/2)
DRAWING NUMBER

Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE SHEET

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

9 OF 23 9 OF 46

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

L67 AUDIO CODEC
D D

POWER, MICBIAS
SHORT-10L-0.1MM-SM
23 14 13 12

DIGITAL SYSTEM I/O
U21
CS42L67-CWZR-A0
A1 C5 B1 F9 D5 D7 E5 E6 E7 F5 F6 F7 F8 G7 H3 H4 J3 J4

XW43
1 2

PP_VCC_MAIN

PP_VCC_MAIN_CODEC
1

C422
10UF

1

C421
0.1UF

1

C420
0.1UF

3

45_AP_TO_CODEC_I2S_MCLK 45_AP_TO_CODEC_ASP_I2S0_BCLK AP_TO_CODEC_ASP_I2S0_LRCLK AP_TO_CODEC_ASP_I2S0_DOUT CODEC_TO_AP_ASP_I2S0_DIN 45_AP_TO_CODEC_VSP_I2S4_BCLK AP_TO_CODEC_VSP_I2S4_LRCLK AP_TO_CODEC_VSP_I2S4_DOUT CODEC_TO_AP_VSP_I2S4_DIN 45_AP_TO_CODEC_XSP_I2S2_BCLK AP_TO_CODEC_XSP_I2S2_LRCLK AP_TO_CODEC_XSP_I2S2_DOUT CODEC_TO_AP_XSP_I2S2_DIN AP_TO_CODEC_SPI3_CS_L AP_TO_CODEC_SPI3_CLK AP_TO_CODEC_SPI3_MOSI CODEC_TO_AP_SPI3_MISO CODEC_TO_AP_INT_L CODEC_TO_PMU_MIKEY_INT_L CODEC_RESET_L

A9 C10 B11 C9 A8 E9 E8 D10 D11 B8 B7 C7 A7 B5 B4 B3 A4 G4 G5 G3 E10 E11 A5 C6 C8 D6

MCLK ASP_SCLK ASP_LRCK ASP_SDIN ASP_SDOUT

WLCSP SYM 3 OF 3

OMIT_TABLE
20 19 18 14 12 11 7 6 5 4 3 2 21

20% 6.3V 2 CERM-X5R 0402-1

10% 6.3V 2 X5R 201

10% 6.3V 2 X5R 201

3 3 3 3

PP1V8
1

PCB: C421 AT U21.L6

C413
0.1UF

3 3 3 3

20% 4V 2 X5R 01005
23 13 4 3 12 10 16 14

VSP_SCLK VSP_LRCK/FSYNC VSP_SDIN VSP_SDOUT

GND

PP1V8_SDRAM
1

C414
10UF

1

C416
0.1UF

15 3 15 3 15 3 15 3

120-OHM-210MA

FL96
01005

20% 2 6.3V CERM-X5R 0402-1

20% 2 4V X5R 01005

XSP_SCLK XSP_LRCK/FSYNC XSP_SDIN/DAC2B_MUTE XSP_SDOUT CS* CCLK CDIN CDOUT INT* WAKE* RESET*

VCP G11

VA J1

VL B9

20% 6.3V 2 X5R 0201-1

1.0UF

VP L6

1

C412

VPROG_CP H11

C

2

1

PP1V7_VA_L67 A11 B10

3 3 3 23 16 14 13 12 10 4 3

C

VD

PP1V8_SDRAM
1

3

KEEP THESE CAPS AT CODEC PINS
1

CS42L67-CWZR-A0

SYM 2 OF 3 FLYC

WLCSP

U21

C232
4.7UF

R145
1.00K

3

FLYP J11 PP_CODEC_VHP_FLYP G9 PP_CODEC_VHP_FLYC H10 J10 PP_CODEC_VHP_FLYN H9 PP_CODEC_VCPFILT+ PGND_CODEC_GNDCP

20% 6.3V 2 X5R-CERM1 402 1

5% 1/32W MF 2 01005

13

C233
4.7UF

KEEP THESE CAPS AT CODEC PINS
1

J5 MIC1_BIAS

FLYN

20% 6.3V 2 X5R-CERM1 402
SHORT-10L-0.1MM-SM

C425
4.7UF

+VCP_FILT K11
GNDCP0 K10 GNDCP1 L11

XW48
1 2

1

R100
2.21K
PP_EXTMIC_BIAS_IN PP_EXTMIC_BIAS PP_EXTMIC_BIAS_FILT_IN PP_EXTMIC_BIAS_FILT
17

J6 MIC1_BIAS_FILT

20% 6.3V 2 X5R-CERM1 402

TSTO

D8 D9 B2 TSTI C3 C4 C11

1% 1/32W MF 2 01005

1

-VCP_FILT L10

PP_CODEC_VCPFILT-

C429
4.7UF

L4 MIC2_BIAS_IN L3 MIC2_BIAS K4 MIC2_BIAS_FILT_IN K3 MIC2_BIAS_FILT H7 MIC3_BIAS G6 MIC3_BIAS_FILT

SPEAKER_VQ J7 PP_CODEC_SPKR_VQ
1

KEEP THESE CAPS AT CODEC PINS

1

C237
1.0UF

GNDP K6 FILT+ H1 PP_CODEC_FILT+ FILT- H2 1 GNDA J2

C234
4.7UF
KEEP THIS CAP AT CODEC PINS

20% 6.3V 2 X5R-CERM1 402

TSTO MUST BE NC

20% 2 6.3V X5R 0201-1 1

C238
4.7UF

C424
10UF

20% 6.3V 2 X5R-CERM1 402

C218
4.7UF
2 1 20% 6.3V X5R-CERM1 402

C219
4.7UF
2 1 20% 6.3V X5R-CERM1 402

A

A10 GNDD

L1 GNDHS0 K2 GNDHS1

B

20% 6.3V 2 X5R-CERM1 402

PP_CODEC_TO_MIC1_BIAS PGND_MIC1_TO_CODEC_RET_FILT

11 8

H6 MIC4_BIAS PP_CODEC_TO_MIC2_3_BIAS PGND_MIC2_3_TO_CODEC_RET_FILT H5 MIC4_BIAS_FILT

20% 6.3V CERM-X5R 2 0402-1

KEEP THIS CAP AT CODEC PINS

B

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

L67 AUDIO CODEC (2/2)
DRAWING NUMBER

Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

10 OF 23 10 OF 46

SHEET

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

CG FLEX B2B
7

120-OHM-25%-250MA-0.5DCR
45_AP_TO_CAM_FF_CLK
1 01005 2 1

FL13

(FF CAM, PROX, ALS, RECEIVER, ANC ERROR MIC)
C198
56PF
1 90-OHM-50MA TCM0605-1
SYM_VER-2

D
FRONT CAM: CLK, I2C, SHDN

120-OHM-25%-250MA-0.5DCR
7

FL15
01005

5% 2 6.3V NP0-C0G 01005 2 1

L35

4

AP_TO_CAM_FF_SCL

1

90_CAM1_TO_AP_MIPI_CLK_N 90_CAM1_TO_AP_MIPI_CLK_P

7 7

D

C192
56PF

2

3 90-OHM-50MA TCM0605-1
SYM_VER-2

120-OHM-25%-250MA-0.5DCR
7 AP_TO_CAM_FF_SHUTDOWN

FL12
01005

5% 2 6.3V NP0-C0G 01005

THIS ON ONE MLB ---> 516S0986 RCPT 516S0987 PLUG 45_AP_TO_CAM_FF_CLK_CONN

L39

1

4

1

2 1

90_CAM1_TO_AP_MIPI_DATA0_N 90_CAM1_TO_AP_MIPI_DATA0_P
2 3

7 7

C202
56PF
AP_TO_CAM_FF_SCL_CONN AP_TO_CAM_FF_SHUTDOWN_CONN AP_BI_CAM_FF_SDA_CONN

120-OHM-25%-250MA-0.5DCR
7

FL14
01005

5% 6.3V 2 NP0-C0G 01005 2

AA22L-S034VA1
39 35

J1

F-ST-SM

70-OHM-300MA
2 1 01005-1 1

FL44

36

OMIT_TABLE

AP_BI_CAM_FF_SDA

1

C402
1 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34

1

C193
4.7UF

PP2V8_CAM_AVDD 12 50 MA

21

FRONT CAM: POWER AND MIPI

C196
56PF

3 5 7 9

5% 6.3V 2 NP0-C0G 01005

MIPI GROUND 90_CAM1_TO_AP_MIPI_CLK_CONN_N 90_CAM1_TO_AP_MIPI_CLK_CONN_P MIPI GROUND 90_CAM1_TO_AP_MIPI_DATA0_CONN_N 90_CAM1_TO_AP_MIPI_DATA0_CONN_P MIPI GROUND PP2V8_FCAM_CONN FCAM ANALOG GROUND PP1V8_FCAM_CONN NOTE: MIC3_TO_CODEC_P NOTE: MIC3_TO_CODEC_N PP_CODEC_TO_MIC3_BIAS_CONN FCAM_TO_AP_ALS_INT_CONN_L PGND_IRLED_K NOTE: IRLED_A
1

5% 6.3V NP0-C0G 2 01005

56PF

20% 2 6.3V X5R 603

120-OHM-25%-250MA-0.5DCR
12 11

FL45
01005

PP3V0_PROX 45_PROX_TO_CUMULUS_RX_CONN PROX GROUND
CUMULUS_TO_PROX_RX_EN_1V8_CONN
1

11 13 15 17 19 21 23 25 27 29 31 33

70-OHM-300MA
1 2

FL23
01005-1

PP1V8 2

21

3 4 5 6 7 10 12 14 18 19 20

PP3V0_PROX_ALS 5 MA

2

C407
0.1UF

1

C410 1
5% 6.3V NP0-C0G 2 01005

NO_XNET_CONNECTION=TRUE

C194 1
1.0UF
20% 6.3V X5R 2 0201-1

C

PROX_RX SIGNAL MUST BE TREATED WITH CARE

PROX: POWER, RX, RX_EN

18

45_PROX_TO_CUMULUS_RX

0.00 1 2
MF 01005 0% 1/32W 1

R125

5% 6.3V NP0-C0G 2 01005

56PF

C63

1

AP_BI_I2C2_SDA_ALS_CONN ALS_TO_AP_INT_CONN_L AP_TO_I2C2_SCL_ALS_CONN PP3V0_ALS CODEC_TO_HAC_CONN_N CODEC_TO_HAC_CONN_P

20% 4V X5R 2 01005

56PF

C
C67
5% 6.3V 2 NP0-C0G 01005

56PF

C62

5% 2 6.3V NP0-C0G 01005

56PF

MIC3_TO_CODEC_P 9 MIC3_TO_CODEC_N 9

22

37 40

38 2

MIC3 (ANC ERROR MIC)
XW42 SHORT-10L-0.1MM-SM
1

FL58
18

NO_XNET_CONNECTION=TRUE

CUMULUS_TO_PROX_RX_EN_1V8

2 01005

1 1

C380
1UF

120-OHM-210MA

C201
56PF

1

20% 6.3V 2 X5R 0201

FL2
3

5% 6.3V 2 NP0-C0G 01005 1 2

120-OHM-210MA
1 2 01005

FL48

PP_CODEC_TO_MIC2_3_BIAS

8 10

AP_BI_I2C2_SDA

1 01005

C253
56PF

120-OHM-210MA

FL57
3

5% 2 6.3V NP0-C0G 01005 1

ALS_TO_AP_INT_L

1 01005

2

1

120-OHM-210MA

DZ18
01005-1

DZ16
01005-1

12V-33PF
2

12V-33PF

11.5

R451
1% 1/20W MF 201 2

R133
1 0% 1/32W

0.00 2
MF 01005

FCAM_TO_AP_ALS_INT_L NOTE: J1.30 IS GND ON POR BOARDS, J1.30 IS ALS_INT FROM FF CAM FOR SPECIAL CONFIG OF PROTO2 (CONTROLLED VIA BOMOPTION)

3

CAM1 ALS INT

B

ALS: POWER, I2C, INT

FL20
3

2 2 1

FF_ALS_INT

AP_TO_I2C2_SCL

1 01005

R132 C211
56PF
1

120-OHM-210MA

C212
56PF

1

C210
56PF
1

PCB: PLACE THESE AT J1 CONN

PGND_IRLED_DRAIN

1

0.00 2
MF 01005

0% 1/32W

120-OHM-25%-250MA-0.5DCR
12 11

FL4
01005

5% 2 6.3V NP0-C0G 01005

5% 6.3V 2 NP0-C0G 01005

5% 6.3V 2 NP0-C0G 01005

DZ19
01005-1

1

DZ17
01005-1

B
CUMULUS_TO_PROX_TX_EN_BUFF
18

12V-33PF
2

12V-33PF

Q1

3

NO_FF_ALS_INT

PP3V0_PROX_ALS 0.25 MA

1

2 1

2

D G S

DMN3730UFB4
1 DFN1006H4-3 1

C56

1

20% 2 4V X5R 01005

0.1UF

C199
56PF
SYM_VER_1

5% 2 6.3V NP0-C0G 01005

R85

2

70-OHM-300MA
1 01005-1 2 1

FL65

5% 1/32W MF 2 01005

1.00M

PROX: PWR, TX EN
IRLED = 104-128MA PP3V0_PROX_IRLED
12

R95

HAC

9 9

CODEC_TO_HAC_N CODEC_TO_HAC_P
9

HAC_TO_CODEC_TEST
-21.4 DB SIGNAL OF HAC VPP

1% 1/32W MF 2 01005 1

15.8K

C200
56PF

1

1

C44

1

5% 6.3V NP0-C0G 2 01005

20% 4V 2 X5R 01005

0.1UF

C256
4.7UF
SPECIAL Z = 0.60 MM MAX

20% 6.3V 2 X5R 0402

R94
10K

70-OHM-300MA
1 01005-1 2

FL64

1% 1/32W MF 2 01005

A

70-OHM-300MA
2 01005-1 1 1

FL51

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

R3

CG FLEX B2B
DRAWING NUMBER

RECEIVER

9 9

CODEC_TO_RCVR_P CODEC_TO_RCVR_N

9

RCVR_TO_CODEC_RCVR_TEST
-21.4 DB SIGNAL OF RCVR VPP

1% 1/32W MF 2 01005 1

10K

Apple Inc.
CODEC_TO_RCVR_CONN_P CODEC_TO_RCVR_CONN_N
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

R9

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

70-OHM-300MA
2 01005-1 1

FL52

1% 1/32W MF 2 01005

15.8K

11 OF 23 11 OF 46

SHEET

8

7

6

5

4

3

2

1

8
23 14 13 12 10

7

6

5
CSD58874W1015
5

4
Q3
C2 B2 BGA
S G

3
CSD58874W1015
5

2
Q4
C2 B2 A2
S G

1

PP_VCC_MAIN PP1V1_CPU0

PP1V1_CPU1

BGA

1

C74

1

20% 6.3V 2 CERM 0402

10UF

C92

1

OMIT_TABLE OMIT_TABLE

20% 6.3V 2 CERM 0402

10UF

C250
10UF

1

C265
10UF

1

C293
10UF

1

C257
10UF

1

C262
10UF

1

C264
10UF

1

C378
10UF

A2

20% 6.3V 2 CERM 0402

20% 6.3V 2 CERM 0402

20% 6.3V 2 CERM 0402

20% 6.3V 2 CERM 0402

OMIT_TABLE

20% 6.3V 2 CERM 0402

OMIT_TABLE

20% 6.3V 2 CERM 0402

OMIT_TABLE

20% 6.3V 2 CERM 0402

C1 B1
D

1

C273
15UF

C1 B1
D

1

C301
15UF

OMIT_TABLE

A1

OMIT_TABLE OMIT_TABLE OMIT_TABLE

20% 4V 2 X5R 0402

A1

20% 4V 2 X5R 0402

1.5UH-20%-2A-0.142OHM

SHORT-10L-0.1MM-SM 1 2

L18

23 22 15 8

PP_BATT_VCC A2 B1 B2 C1

1.5UH-20%-2A-0.142OHM

Q5
A1 G

10% 10V X5R 2 201

1.5UH-20%-2A-0.142OHM

0.01UF

C16 1

NOSTUFF

NOSTUFF

1

1

L23

OMIT_TABLE

OMIT_TABLE

VPUMP

10% 6.3V X5R 2 01005

TFA201610G-SM TFA201610G-SM

10% 6.3V X5R 2 01005

20% 4V 2 X5R 0402

20% 4V 2 X5R 0402

20% 4V 2 X5R 0402

20% 4V 2 X5R 0402

20% 4V 2 X5R 0402

0.01UF

SAME POLARITY

0.01UF

SAME POLARITY

5% 6.3V 2 NP0-C0G 01005

5% 16V NP0-C0G 2 01005

5% 6.3V 2 NP0-C0G 01005

5% 16V NP0-C0G 2 01005

20% 6.3V 2 CERM 0402

20% 6.3V 2 CERM 0402

C269 1

1

C271
15UF

1

C276
15UF

1

C278
15UF

1

C281
15UF

1

C282
15UF

SHORT-10L-0.1MM-SM 1 2

56PF

100PF

56PF

100PF

NO_XNET_CONNECTION=TRUE

XW10

XW16

10UF

10UF

NO_XNET_CONNECTION=TRUE

1

C688 C689

1

1

C686 C687 1

1

C294

1

C299

PP1V1_CPU0_FET

1.5UH-20%-2A-0.142OHM

D

23 14 13 12 10

PP_VCC_MAIN

12

VCENTER

PP1V1_CPU1_FET
1

D
1

C289

2

2

1

C295
15UF

1

C302
15UF

C305
15UF

1

C312
15UF

1

C318
15UF

20% 4V 2 X5R 0402

20% 4V 2 X5R 0402

20% 4V 2 X5R 0402

20% 4V 2 X5R 0402

20% 4V 2 X5R 0402

2

TFA201610G-SM TFA201610G-SM

2

CSD68803W15
BGA

2.2UH-20%-1.7A-200MOHM
1 TFA201610G-SM 2 1

L26

L12

2

USB_VBUS_DETECT 1

1

C260

1

IBAT CPUA_EN CPUA_SW_S CPUA_SW_OUT BUCK0A_LXM BUCK0A_LXL BUCK0A_FB CPUB_EN CPUB_SW_S CPUB_SW_OUT BUCK0B_LXM BUCK0B_LXL BUCK0B_FB B19CPU0_SWITCH 2 N21 5 CPU0_SW_S L19 CPU0_SW_CONTROL A12 BUCK0A_LXM A14 BUCK0A_LXL D21 BUCK0A_FB A22 K19 J19 A16 A18 C22 CPU1_SWITCH 2 5 CPU1_SW_S CPU1_SW_CONTROL BUCK0B_LXM BUCK0B_LXL BUCK0B_FB BUCK0C_LX BUCK0C_FB BUCK2_LXL BUCK2_LXM BUCK2_LXR BUCK2_FB TO SOC BUCK3_LX BUCK3_FB

1

1/32W 1%

68.1K2

R55

22 12

BATTERY_TO_PMU_SENSE VCENTER E1 E2

D2013B28HGAHVCC2
BGA (1 OF 3) VPUMP L21

U7

L13

2.2UH-20%-1.7A-200MOHM

2.2UH-20%-1.7A-200MOHM

2.2UH-20%-1.7A-200MOHM

2

2

TFA201610G-SM

TFA201610G-SM

L14

L15

1

NO_XNET_CONNECTION=TRUE

10% 5% 25V X5R 2 2 25V NP0-C0G-CERM 0402 0201
23 14 13 12 10

56PF

2.2UH-20%-1.7A-200MOHM
1 TFA201610G-SM SOD523 A K 2

L16

1 C444 C248 1UF

1

VSW_CHG

H1 H2

C283

CHG_LX

SHORT-10L-0.1MM-SM 1 2

D4

1

1

1

10% 2 6.3V X5R 01005

0.01UF
NOSTUFF

2.2UH-20%-1.7A-200MOHM

C
PP_VCC_MAIN
1

17

PP5V0_USB_PROT

TFA201610G-SM

L11

L1 L2

2

2

TFA201610G-SM

XW15

1

1

1

20% 6.3V 2 CERM-X5R 0402-1

OMIT_TABLE

20% 6.3V 2 CERM-X5R 0402-1

OMIT_TABLE

20% 6.3V 2 X5R 0201-1

20% 6.3V 2 CERM-X5R 0402-1

OMIT_TABLE PP1V8_SDRAM
1

TFA201610G-SM

L24

L25

1

1

1

1

20% 2 6.3V CERM-X5R 0402-1

10UF

OMIT_TABLE

20% 2 6.3V CERM-X5R 0402-1

10UF

OMIT_TABLE

20% 2 6.3V CERM-X5R 0402-1

10UF

OMIT_TABLE

20% 2 6.3V CERM-X5R 0402-1

10UF

C261
1.0UF

OMIT_TABLE

1

1

3 4 5 6 7 10 11 12 14 18 19 20 21

1

C195
10UF

1

C205
10UF

1

C243
10UF

1

C247
10UF

12 4

PP1V2_SDRAM
1

C258
1.0UF

20% 6.3V 2 CERM-X5R 0402-1

OMIT_TABLE

20% 6.3V 2 CERM-X5R 0402-1

OMIT_TABLE

20% 2 6.3V CERM-X5R 0402-1

OMIT_TABLE

20% 6.3V 2 CERM-X5R 0402-1

BUCK4_LXL A10 BUCK4_LXM A8 BUCK4_FB D1 VBUCK4_SW M21 CPU1V2_SW M22 VLDO1 VLDO2 VLDO3 VLDO4 VLDO5 VLDO6 VLDO7 VLDO8 VLDO9 VLDO10 VLDO11 VLDO12 VLDO16 ON_BUF

BUCK4_LXL BUCK4_LXM BUCK4_FB

OMIT_TABLE

20% 2 10V X5R-CERM 0201-1

XW17

20% 10V 2 X5R-CERM 0201-1

B
PLACE CLOSE TO PMU

Q3 P4 Q19 Q10 N22 P5 P8 P7 P6 Q12 Q1 P2 Q2 M2 L4 M4

CALIBRATION

VDD_LDO1_6 VDD_LDO2 VDD_LDO3_8 VDD_LDO4_7 VDD_LDO5 VDD_LDO9 VDD_LDO10 VDD_LDO11 VDD_LDO12 VDD_LDO16 TDEV1 TDEV2 TDEV3 TDEV4 TCAL TBAT

VBUCK3_SW K22 WDIG_SW K21 CPU1V8_SW L22

PP1V8_GRAPE 18 PP1V8 2

NO_XNET_CONNECTION=TRUE

SHORT-10L-0.1MM-SM 1 2

C190

C204

C239

C246

23 16 14 13 12 10 4 3

BUCK3_LX H22 BUCK3_FB E22

SAME POLARITY

TFA201610G-SM

A13 A17 A21 A5 A1 G22 A9

VDD_BUCK0A VDD_BUCK0B VDD_BUCK0C VDD_BUCK2LM VDD_BUCK2R VDD_BUCK3 VDD_BUCK4

2.2UH-20%-1.7A-200MOHM

10UF

10UF

1.0UF

10UF

PMEG3010EB/S500

BUCK2_LXL BUCK2_LXM BUCK2_LXR BUCK2_FB

A6 A4 A2 D2

L17

C189

C203

C217

C245

2.2UH-20%-1.7A-200MOHM

1

2

2

C207 1
100PF
5% 16V NP0-C0G 2 01005

1
2 7

PP2V5_CAM0_AF_COMP

21

Y2
32.768K-20PPM-12.5PF
1 2

OSC32I OSC32O

P1 XTAL1 N1 XTAL2

PP1V0 PP1V0_SRAM
5

1% 1/32W MF 01005

1 1

C251
18PF

1

2012-1

C263
18PF

C267
0.1UF

1

C987
1.0UF

1

C270
0.1UF
NOSTUFF

1

C272
0.1UF
NOSTUFF

2% 16V CERM 2 01005

2% 16V 2 CERM 01005

20% 6.3V 2 X5R-CERM 01005

20% 6.3V 2 X5R 0201-1

10% 6.3V 2 X5R 201

10% 2 6.3V X5R 201

XW14 SM
1 2

PGND_CAM0_AF_RET

21

THIS XW LINK AT PMU AREA

NOTE: PLACE C987 UNDERNEATH C270 NOTE: ROUTE TRACES BETWEEN LDO AND CAP TO ALLOW 0.050 OHM ESR

A
NO_XNET_CONNECTION=TRUE

FOREHEAD NTC
NTC_FOREHEAD_P 12 I394
2

CAMERA NTC
NTC_CAM_P I390
NO_XNET_CONNECTION=TRUE
12

H5P NTC
NTC_H5P_P I382
NO_XNET_CONNECTION=TRUE
12

RADIO PA NTC
NTC_PA_P 12 I649
NO_XNET_CONNECTION=TRUE

C1

C159
100PF

1

5% 16V NP0-C0G 2 01005

100PF IS NEEDED FOR SAMPLING CAP IN ADC IN PMU

8

D S A3 B3 C2 C3
1 1 0201

PP1V1_CPUB

5

C310
10UF

1

C317
10UF

1

C319
10UF

01005 MF C291 1

20% 20% 6.3V 6.3V CERM-X5R 2 CERM-X5R 2 0402-1 0402-1

10UF

10UF

SHORT-10L-0.1MM-SM 1 2

XW20

20% 2 6.3V CERM-X5R 0402-1

20% 2 6.3V CERM-X5R 0402-1

20% 2 6.3V CERM-X5R 0402-1

C1 VBAT ACT_DIO C2 ACT_DIO J1 J2

NO_XNET_CONNECTIO=TRUE L11-L13 POLARITY ALL SAME
1

PP1V1_SOC

5

C285
15UF

1

C288
15UF

1

C290
15UF

1

C292
15UF

VCENTER

20% 4V 2 X5R 0402

20% 4V 2 X5R 0402

20% 4V 2 X5R 0402

20% 4V 2 X5R 0402

VBUS

C
PP1V8_SDRAM
1
3 4 10 12 13 14 16 23

F1 VCC_MAIN F2 K1 VCC_MAIN_S

BUCK0C_LX A20 BUCK0C_FB C21

C379
15UF

1

C385
15UF

1

C389
15UF

1

C391
15UF

20% 4V 2 X5R 0402

20% 4V 2 X5R 0402

20% 4V 2 X5R 0402

20% 4V 2 X5R 0402

PP1V2_SDRAM
1

4 12

5

C296
10UF

1

C303
10UF

1

C308
10UF

1

C316
10UF

20% 2 6.3V CERM-X5R 0402-1

20% 2 6.3V CERM-X5R 0402-1

20% 2 6.3V CERM-X5R 0402-1

20% 2 6.3V CERM-X5R 0402-1

PP1V2

2 4

B
PP1V7_VA_L20 19-25 MILLIOHM
15

R54

22 17

BATTERY_TO_PMU_NTC
1

12 12 12 12

0.1% 1/20W MF 2 0201

3.92K

C255
100PF

5% 16V 2 NP0-C0G 01005

NTC_FOREHEAD_P NTC_CAM_P NTC_PA_P NTC_H5P_P TCAL

Q17 VDD_VIB Q18 VIB P20 VIB_PWM_EN

P3 PP3V0_ALWAYS 8 16 Q5 P18 PP3V3_USB 2 P9 P22 PP3V0_NAND 6 Q4 P10 PP3V0_IMU 20 P19 PP3V0_PROX_ALS 11 Q6 PP3V0_VIBE Q9 PP3V0_PROX_IRLED 11 Q8 PP2V8_CAM_AVDD 11 21 Q7 Q13 P17 PP1V8_ALWAYS 3

PP2V5_CAM0_AF PP3V0_ACC
1
8 16

21 23 16 14 13 12 10 4 3

TPS22924X
PP1V8_SDRAM A2 B2 CSP VIN VOUT A1 B1 PP1V8
2 3 4 5 6 7 10 11 12 14 18 19 20 21

U11

C17

1

C277
4.7UF

TBD: VALUE MUST BE TUNED
23 22 19 16 14 13 2

20% 6.3V 2 X5R-CERM1 402

4.7UF

20% 2 6.3V X5R-CERM1 402

RESET_1V8_L

C2 ON GND

10.2 2

R56

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

R108
NO_XNET_CONNECTION=TRUE

2

R110
NO_XNET_CONNECTION=TRUE

2

R57
NO_XNET_CONNECTION=TRUE

2

R90
NO_XNET_CONNECTION=TRUE

AGATHA PMU(1/2)
DRAWING NUMBER

C167 1
100PF
5% 16V NP0-C0G 2 01005

C168
100PF

1

C322
100PF

1

PLACE CLOSE TO PMU 10KOHM-1%-0.31MA
SHORT-10L-0.1MM-SM 1 2 NTC_FOREHEAD_N

PLACE CLOSE TO PMU
1

5% 16V NP0-C0G 2 01005

PLACE CLOSE TO PMU
1

5% 16V NP0-C0G 2 01005

Apple Inc.
PLACE CLOSE TO PMU
1 10KOHM-1%-0.31MA 0201 SHORT-10L-0.1MM-SM 1 2
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

XW6

10KOHM-1%-0.31MA
0201

NTC_CAM_N

SHORT-10L-0.1MM-SM 1 2

XW8

10KOHM-1%-0.31MA
0201

NTC_H5P_N

SHORT-10L-0.1MM-SM 1 2

XW9

XW11

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

NTC_PA_N

12 OF 23 12 OF 46

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8

7

6

5

4

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1

D

A15 A3 J22 A7 A11 A19 G4 E19 E21

BGA VSS_BUCK0AB (3 OF 3) VSS_BUCK2 VSS_BUCK3 VSS_BUCK24 VSS_BUCK40 VSS_BUCK0BC VSSA_BUCK2 VSSA_BUCK3 VSSA_BUCK40

D2013B28HGAHVCC2
G14 G15 G16 G17 G18 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16

U7

D

P16 VSS_WLED P15 VSS_LCM D22 VSS_REF G1 G2 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 G5 G6 G7 G8 G9 G10 G11 G12 G13

VSS_SW_CHG

1% 1/20W

200K 2 1

R65

R921
MF 201 1 MF

6.34K2 TRISTAR_TO_PMU_USB_BRICKID
1% 01005 CHESTNUT_TO_PMU_ADCIN7

1/32W

16 13 14

C323
0.1UF
1 10% 6.3V 2 X5R 201 1

C343

C325
1.0UF
1 2

10% 2 6.3V X5R 01005

0.01UF

0.01UF

C327 1
10% 6.3V 2 X5R 01005

AMUX VOLTAGE LIMIT IS APPROX. = VDD_REF = PP_VCC_MAIN BUTTON_TO_AP_HOLD_KEY_BUFF_L K6 1.8V ---> 13 3 K5 1.8V ---> 13 3 BUTTON_TO_AP_MENU_KEY_BUFF_L K4 1.8V ---> 13 8 3 BUTTON_TO_AP_RINGER_A J6 8 3 BUTTON_TO_AP_VOL_UP_L 1.8V ---> J5 8 3 BUTTON_TO_AP_VOL_DOWN_L 1.8V ---> J4 19 14 LCD_PWR_EN H6 13 TRISTAR_TO_PMU_USB_BRICKID_R 3.33V ---> H5 14 13 CHESTNUT_TO_PMU_ADCIN7 H4 PMU_AMUX_AY 22 F4 23 RADIO_TO_PMU_ADC_SMPS1_MSMC_1V05 F5 23 RADIO_TO_PMU_ADC_SMPS3_MSME_1V8 E4 16 TRISTAR_TO_PMU_MIKEYBUS_TEST_POS E5 16 TRISTAR_TO_PMU_MIKEYBUS_TEST_NEG 1.8V ---> D4 23 13 45_PMU_TO_WLAN_CLK32K 1.8V ---> D5 23 RADIO_TO_PMU_ADC_LDO6_RUIM_1V8 BASEBAND ---> D6 AP_TO_PMU_TEST_CLKOUT 2 B1 23 RADIO_TO_PMU_ADC_LVS1 B2 22 PMU_AMUX_BY

D2013B28HGAHVCC2
AMUX_A0 AMUX_A1 AMUX_A2 AMUX_A3 AMUX_A4 AMUX_A5 AMUX_A6 AMUX_A7 AMUX_AY AMUX_B0 AMUX_B1 AMUX_B2 AMUX_B3 AMUX_B4 AMUX_B5 AMUX_B6 AMUX_B7 AMUX_BY GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 SCL SDA DWI_CK DWI_DI DWI_DO BGA (2 OF 3) IREF VREF VDD_REF VDD_RTC P21 Q21 B22 F22 IREF VREF VDD_REF VDD_RTC
13

U7

20% 6.3V

X5R 0201-1

C

C326
0.1UF
1 10% 6.3V 2 X5R 201 1

PP_VCC_MAIN

10 12 14 23

R68

C

VSS

BRICK_ID M1 ADC_IN7 K2 ADC_REF F21 ACC_ID Q20 DPHP FW_DPHP_DET ACC_DET BUTTON1 BUTTON2 BUTTON3

TRISTAR_TO_PMU_USB_BRICKID_R

EMC REVIEW REQUESTS THIS GO TO 1K

R487
0% 1/32W MF 01005

1

0.00 2

5% 1/32W MF 2 01005

220K

E75_TO_PMU_ACC_DETECT KEEPACT
1
3

16 17

BASEBAND --->

VSS

B18 N2 B21 E75_TO_PMU_ACC_DETECT_R B12 BUTTON_TO_AP_MENU_KEY_BUFF_L B13 BUTTON_TO_AP_HOLD_KEY_BUFF_L B14 BUTTON_TO_AP_RINGER_A

NOSTUFF
1
3 13 3 13 3 8 13

R66

R488
0.00

0% 1/32W MF 2 01005

5% 1/32W MF 2 01005

1.00M

KEEPACT G21 SHDN F19 LCM_LX VBOOST_LCM VLCM1 VLCM2 LCM2_EN VLCM3 WLED_LX VOUT_LED WLED1 WLED2 Q15 P12 P13 Q11 B20 P11 Q16 Q22 P14 Q14

B

PMU_AP_TO_LCM_RESET_L BB_TO_PMU_HOST_WAKE BB_RST_PMU_R_L 23 PMU_TO_BB_RST_L 5% 16 3 TRISTAR_TO_AP_INT 1/32W MF 23 13 45_PMU_TO_WLAN_CLK32K 01005 22 3 AP_BI_BATTERY_SWI 23 WLAN_TO_PMU_HOST_WAKE R63 10 CODEC_TO_PMU_MIKEY_INT_L 10K 1 2 BT_REG_ON_R 23 PMU_TO_BT_REG_ON 5% MF R64 1/32W 01005 23 BT_TO_PMU_HOST_WAKE 10K 1 2 WIFI_REG_ON_R 23 PMU_TO_WLAN_REG_ON 5% MF 01005 DRIVEN TO VCC_MAIN ------------> 1/32W 23 PMU_TO_BB_VBUS_DET

1.00K 1 2

R60

19 23

B3 B4 B5 B6 B7 B8 B9 B10 B11 B15 B16 B17 G19 H19 M19 M18 M17

B

20 16 15 14 3 20 16 15 14 3 14 14 3 45_AP_TO_PMU_DWI_CLK 3 45_AP_TO_PMU_DWI_DO 3 45_AP_TO_PMU_DWI_DI

AP_TO_I2C0_SCL AP_BI_I2C0_SDA
SM

1 1 1

2 2 2

SM SM

XW26 XW27 XW28

PMU_DWI_CLK PMU_DWI_DI PMU_DWI_DO

ACCESS POINTS

22 19 16 14 12 2 23 3

PMU_RESET_IN RESET_1V8_L PMU_TO_AP_IRQ_L

J21 RESET_IN D19 RESET* H21 IRQ*

23 16 14 12 10 4 3

PP1V8_SDRAM
6

74LVC1G32
SOT891 4 1

I2C ADDRESS: 1110100X
ACTIVE HIGH

2

WDOG FROM H5P TRISTAR_TO_PMU_HOST_RESET FROM TRISTAR

2 1

U14
NC

16

100K

R591
5% 1/32W MF 01005 2

5

3

C99

5% 2 10V NP0-C0G 01005

100PF

A

GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 RESET_IN RESET* IRQ*

PP1V8_SDRAM OUPUT ’0’ INPUT, W/O PD PP1V8_SDRAM OUPUT ’0’ PP1V8_SDRAM OUPUT ’0’ PP1V8_SDRAM OUPUT ’0’ INPUT, W/ PU IN BATTERY PCM INPUT, W/ PD IN PMU INPUT, W/ PU TO PP1V8_SDRAM PP1V8_SDRAM OUTPUT ’0’ INPUT, W/ PD IN PMU PP1V8_SDRAM OUTPUT ’0’ VCC_MAIN OUPUT ’0’ ACTIVE HIGH INPUT W/ INTERNAL 200K PD OPEN DRAIN OUTPUT OPEN DRAIN OUTPUT

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

AGATHA PMU(2/2)
DRAWING NUMBER

Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

13 OF 23 13 OF 46

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4

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1

CHESTNUT, BACKLIGHT DRIVER
D

D404 DISPLAY PMU (INTERSIL CHESTNUT, 338S1168) (TI CHESTNUT, 338S1172)
14 23 14 13 12 10

NOSTUFF

TPS799L57
WCSP

U10

D
PP5V7_TO_LCD_AVDDH U10_BYPASS
1
14 19

1

1

C562
56PF

2.2UH-20%-1.7A-200MOHM
TFA201610G-SM

L19
2

5% 16V 2 NP0-C0G 01005

20% 6.3V X5R-CERM1 2 402

4.7UF

C47

1

I2C0: 0100111X
1

NOSTUFF
20% 6.3V 2 X5R 0402

GND

PP_VCC_MAIN

C3 IN PP6V0_LCM_BOOST A1 EN 19 14 13 LCD_PWR_EN

OUT C1 NR A3

C121
4.7UF

B2

C592
4.7UF
NOSTUFF

OMIT_TABLE

ISL97751IIA0PZ
WLCSP D1 VIN CP CN

U3

PP_CHESTNUT_CP C4 E4 PP_CHESTNUT_CN VPOS VPOS VNEG VSUB VO1 B3 B4 E3 E2 A4 A3 A1
19 18

0.01UF

C122 1
10% 6.3V 2 X5R 01005

1

OMIT_TABLE

C54

20% 2 6.3V X5R 0402

PP_CHESTNUT_LXP
18

B2 LXP

20% 10V 2 X5R-CERM 0402-1

10UF

NOSTUFF

LCM_TO_AP_HIFA_BSYNC_BUFF A2 SYNC AP_TO_I2C0_SCL AP_BI_I2C0_SDA LCD_PWR_EN D3 SCL D2 SDA C3 EN C2 NRST PGND C1 AGND E1 AMUX

14

PP6V0_LCM_BOOST

20 16 15 14 13 3

20 16 15 14 13 3

NOSTUFF PP1V8
1

19 18 14 12 11 10 7 6 5 4 3 2 21 20

0.00 2
0% 1/32W MF 01005

R49

PN5V7_SAGE_AVDDN
1

1

C662
56PF

1

C329
22UF

PP5V7_TO_LCD_AVDDH_CHESTNUT 1 0.00 2 PP5V7_TO_LCD_AVDDH 14
0% 1/32W MF 01005

R512

14 19

19 14 13

CHESTNUT_NRESET CHESTNUT_TO_PMU_ADCIN7 TO DO: ADD 1NF CAP HERE ON ADCIN7
13

PP5V7_SAGE_AVDDH PP5V7_TO_LCD_AVDDH_CHESTNUT PP5V1_GRAPE_VDDH
1
18

18

C330
10UF

1

C762
56PF

5% 16V 2 NP0-C0G 01005

20% 2 10V X5R-CERM 0603

VO2 VO3

14

20% 2 10V X5R-CERM 0402-1

5% 2 16V NP0-C0G 01005

OPTION TO ZERO OUT U10 AND POWER IT DOWN

B1 D4

23 22 19 16 13 12 2

RESET_1V8_L

1

0.00 2
0% 1/32W MF 01005

R61

1

C52

1

C441
1UF

C

20% 6.3V 2 X5R 0201

20% 10V 2 X5R-CERM 0402-1

10UF

C69

OMIT_TABLE

20% 10V 2 X5R-CERM 0402-1

10UF

SAGE NEG BOOST TIMING INFO:
2 MS NOMIAL START UP DELAY FOR LCM POWER SEQUENCING 0 MS DELAY AT SHUTDOWN ACTIVE DISCHARGE 2MS TO RAIL DOWN

C

REFER TO RADAR 12410499. THIS IS PART OF BUILD MATRIX TO POTENTIALLY IMPLEMENT LCD PANIC FUNCTION

D404 BACKLIGHT DRIVER
I2C0: 1100011X

B
23 14 13 12 10

22UH-20%-0.38A-0.876OHM
PP_VCC_MAIN
1 1 2

L3

NSR0620P2XXG
PP_WLED_LX
A K

D1

B

C252
10UF

1

C297
10UF

VLF302510T-SM

U23
A3 SW C3 IN AP_BI_I2C0_SDA AP_TO_I2C0_SCL PP1V8 PP1V8_SDRAM A1 A2

SOD-923-HF

OMIT_TABLE

20% 6.3V CERM-X5R 2 0402-1

20% 6.3V 2 CERM-X5R 0402-1

LM3534TMX-A1
BGA

OVP D1 PP_LCM_BL_CAT1 PP_LCM_BL_CAT2 45_AP_TO_PMU_DWI_CLK 45_AP_TO_PMU_DWI_DO
3 13 3 13 19 19

PP_LCM_BL_ANODE
1

19

OMIT_TABLE
20 16 15 14 13 3 20 16 15 14 13 3

SDA SCL

ILED1 D3 ILED2 D2 SCK B2 SDI C2

C213
56PF
LCM_DESENSE

1

C27

1

19 18 14 12 11 10 7 6 5 4 3 2 21 20

C1 VIO_SPI B1 HWEN GND B3

5% 16V 2 NP0-C0G 01005 1

20% 2 25V X5R-CERM 0402-1

2.2UF

C97

1

20% 2 25V X5R-CERM 0402-1

2.2UF

C98

20% 2 25V X5R-CERM 0402-1

2.2UF

23 16 13 12 10 4 3

C214
56PF

5% 16V 2 NP0-C0G 01005

NOTE: STACKED TO MEET VOLTAGE REQ, LOOK INTO 18+V CAPS

A

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

CHESTNUT + BACKLIGHT DRIVER
DRAWING NUMBER

Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

14 OF 23 14 OF 46

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1

SPEAKER AMP, LED DRIVER
D

SPEAKER AMP (REPLACED WITH L20)
I2C ADDRESS: 1000000X TO DO: CHANGE NETNAMES WITH ’L19’ TO ’L20’ WHEN WE UPDATE TO NEW SILICON
PCB: PLACE AT C335.1
1

D

C335
10UF

1

C337
1.0UF

20% 6.3V 2 CERM-X5R 0402-1

OMIT_TABLE

20% 6.3V 2 X5R 0201-1

PP1V7_VA_L20

12

PCB: PLACE C335,337 AT VP INPUT PP_L20_VBOOST
1
23 22 15 12 8

PP_BATT_VCC

C348
22UF

1

C342
0.1UF
VBST_B A1 VBST_A B1 VBST_A C1 VBST_A D1

1

C339
0.1UF
V = 1.0V C= 1UF MIN
1

VA F5

VP A4 VP A5

20% 2 10V X5R-CERM 0603

10% 2 16V X5R-CERM 0201

10% 2 6.3V X5R 201

V= VA PIN C= 2.2UF MIN

1.0UH-20%-3.2A-0.065OHM
1 2 TFA252010-SM
20 16 14 13 3 20 16 14 13 3

L4

C29

1

PP_SPKAMP_SW

C333
PCB: PLACE C332, C333 AT L4.1

1

20% 6.3V CERM-X5R 2 0402-1

10UF

C332
10UF

1

A2 B2 D5 D6 A7

CS35L20
SW SDA SCL INT* WLCSP VER1

U22

FILT+ F2 PP_SPKAMP_FILT LDO_FILT C5 PP_SPKAMP_LDO_FILT VSENSE- E3 VSENSE+ E2 ISENSE- F1 ISENSE+ E1 OUT+ D2 OUT- C2 L20_SPKAMP_VSENSE_N L20_SPKAMP_VSENSE_P

20% 2 6.3V X5R 0201-1

1.0UF

C341
1.0UF

1

C340
4.7UF

20% 2 6.3V X5R 0201-1

20% 2 6.3V X5R-CERM1 402

R126
1

20% 6.3V CERM-X5R 2 0402-1

AP_BI_I2C0_SDA AP_TO_I2C0_SCL SPKAMP_TO_AP_INT_L

C367

1 1% 1/32W

10K

2 SPEAKER_TO_SPKAMP_VSENSE_N MF 01005

17

OMIT_TABLE

OMIT_TABLE
3

10% 2 10V X7R-CERM 01005

220PF

R127
1 1% 1/32W

C

3

AP_TO_SPKAMP_RESET_L
1

A6 RESET*
3

SPEAKER_TO_SPKAMP_ISENSE_N SPEAKER_TO_SPKAMP_ISENSE_P SPKAMP_TO_SPEAKER_OUT_P SPKAMP_TO_SPEAKER_OUT_N

10K

2 SPEAKER_TO_SPKAMP_VSENSE_P MF 01005

17

R129
510K
(LEFT CONFIG)
3

AP_TO_SPKAMP_BEE_GEES

D7 ALIVE C7 ADO

C
FL6
0402

5% 1/32W MF 2 01005

1

45_AP_TO_SPKAMP_I2S2_MCLK 45_AP_TO_CODEC_XSP_I2S2_BCLK AP_TO_CODEC_XSP_I2S2_LRCLK AP_TO_CODEC_XSP_I2S2_DOUT CODEC_TO_AP_XSP_I2S2_DIN

E7 MCLK E6 SCLK F6 LRCK/FSYNC F7 SDIN E5 SDOUT GNDP A3 B3 B4 C3 C4 D3 D4

IREF+ B7 SPKAMP_IREF
1

C309

10 3

R35

10 3

1% 1/32W MF 2 01005

44.2K

20% 2 6.3V X5R-CERM 01005

0.1UF

120OHM-25%-1.8A-0.06DCR
1 2

SPKAMP_TO_SPEAKER_OUT_CONN_P

17 22

10 3

10 3

~700MA RMS @ 4.1W INTO 8OHM GNDA B5 B6 C6 E4 F3 F4

120OHM-25%-1.8A-0.06DCR
1 0402 2

FL9

SPKAMP_TO_SPEAKER_OUT_CONN_N

17 22

1000PF

C360 1
10% 10V X5R 2 01005

1000PF

C363 1
10% 10V X5R 2 01005

1000PF

C500

1

1

C501

10% 10V 2 X5R 01005

10% 2 10V X5R 01005

1000PF 1000PF

C545
NOSTUFF

1

1

C546

10% 10V 2 X5R 01005

10% 2 10V X5R 01005

1000PF

NOSTUFF

B
23 22 15 12 8

LED DRIVER
I2C ADDRESS: 1100011X
PP_BATT_VCC

B

C386 1
10UF
OMIT_TABLE
20% 6.3V CERM 2 0402

C387
10UF

1

OMIT_TABLE

20% 6.3V CERM 2 0402

0.47UH-20%-3.2A-0.046OHM
1 TFA201610G-SM 2

L5

LM3563A3TMX
C4 A3 B3 D4 IN SW0 SW1 ENABLE STROBE TORCH TX SDA SCL GND0 GND1

U17
BGA

LED_DRV_LX

OUT0 A2 OUT1 B2 LED0 A1 LED1 B1 TEMP C1 PP_STRB_DRIVER_TO_LED

LED_BOOST_OUT
1

C394
10UF

1

C396
10UF

1

C488
100PF

3

AP_TO_LEDDRV_EN
1

R463
220K

21

CAM0_TO_LEDDRV_STROBE_EN C3
7

20% 6.3V 2 CERM-X5R 0402-2

20% 6.3V 2 CERM-X5R 0402-2

5% 16V 2 NP0-C0G 01005

5% 1/32W MF 2 01005

CAM0_TORCH

C2 D1 D2 D3

8

23

BB_TO_LEDDRV_GSM_BLANK AP_BI_CAM_RF_SDA AP_TO_CAM_RF_SCL

21 7

100PF
CAM_RF_TO_STROBE_NTC
8

C73 1

21 7

5% 16V NP0-C0G 2 01005

A

A4 B4

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

SPKR AMP + LED DRIVER
DRAWING NUMBER

Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

15 OF 23 15 OF 46

SHEET

8

7

6

5

4

3

2

1

8

7

6

5

4
12C ADDRESS: 0011010X

3

2

1

12 8

PP3V0_ALWAYS
1

C38

1

D

VDD_1V8 F3

VDD_3V0 F4

13

TRISTAR_TO_PMU_MIKEYBUS_TEST_POS
1

NO_XNET_CONNECTION=TRUE

OMIT_TABLE

R83

R43
9 9

90_CODEC_BI_TRISTAR_MIKEYBUS_P 90_CODEC_BI_TRISTAR_MIKEYBUS_N

1 5% 1/20W

0

5% 1/32W MF 2 01005 2 MF 201

100K

CBTL1608A1
90_CODEC_BI_TRISTAR_MIKEYBUS_DIG_P 90_CODEC_BI_TRISTAR_MIKEYBUS_DIG_N
23

U2

R44
1 5% 1/20W

C3 C4 A1 B1 C2 A3 B3 E2 E1 F2 F1 D2 D1 A5 B5

DIG_DP DIG_DN USB1_DP USB1_DN BRICK_ID USB0_DP USB0_DN UART0_TX UART0_RX UART1_TX UART1_RX UART2_TX UART2_RX JTAG_CLK JTAG_DIO

WCSP

ACC_PWR D5

TRISTAR

20% 2 6.3V X5R 0201-1

1.0UF

C254
0.1UF

23 14 13 12 10 4 3

PP1V8_SDRAM
1

20% 2 4V X5R 01005

C39

10% 6.3V 2 X5R 01005

0.01UF
PP3V0_ACC ACC_PWR
12

D

0

2 MF 201 1

BB DEBUG USB

23

90_TRISTAR_BI_BB_USB_P 90_TRISTAR_BI_BB_USB_N TRISTAR_TO_PMU_USB_BRICKID 90_AP_BI_TRISTAR_USB0_P 90_AP_BI_TRISTAR_USB0_N AP_TO_TRISTAR_ACC_UART2_TXD TRISTAR_TO_AP_ACC_UART2_RXD AP_TO_TRISTAR_DEBUG_UART6_TXD TRISTAR_TO_AP_DEBUG_UART6_RXD BB_TO_AP_UART1_RXD AP_TO_BB_UART1_TXD TRISTAR_TO_AP_JTAG_SWCLK TRISTAR_BI_AP_JTAG_SWDIO

P_IN F6 ACC1 C5 ACC2 E5 DP1 A2 DN1 B2 DP2 A4 DN2 B4

PP_E75_TO_TRISTAR_ACC1 17 PP_E75_TO_TRISTAR_ACC2 17 90_TRISTAR_BI_E75_PAIR1_P 90_TRISTAR_BI_E75_PAIR1_N 90_TRISTAR_BI_E75_PAIR2_P 90_TRISTAR_BI_E75_PAIR2_N E75_TO_PMU_ACC_DETECT

C304 1
1UF
17 22 17 22

PP5V0_USB_RPROT 17 PIN FOR HANDSHAKE

PLACEHOLDERS FOR INDUCTORS

R84

10% 25V X5R 2 0402

5% 1/32W MF 2 01005

100K

BRICK_ID SOC USB

13

17 22 17 22

2 2

13

TRISTAR_TO_PMU_MIKEYBUS_TEST_NEG

NO_XNET_CONNECTION=TRUE ACCESSORY UART

CON_DET_L E3 OVP_SW_EN* D6 SWITCH_EN E4 HOST_RESET B6 SDA SCL INT BYPASS DVSS DVSS DVSS D3 D4 C6 E6

13 17

1

3 3

PP

P4MM
SM

PP22
17

TRISTAR_TO_PMU_OVP_SW_EN_L RESET_1V8_L
2 12 13 14 19 22 23

DEBUG UART

3 3

TO DO: ADD PPS TO SOC-SIDE USB

23 3 23 3

C

2 2

AP_BI_I2C0_SDA 3 13 AP_TO_I2C0_SCL 3 13 TRISTAR_TO_AP_INT TRISTAR_BYPASS
1

14 15 20 14 15 20 3 13

TRISTAR_TO_PMU_HOST_RESET 13 HOST_RESET ACTIVE HIGH AMBER HAS 200K INT PD
1

R8401
100K

C338
1.0UF

5% 1/32W MF 2 01005

C

NO_XNET_CONNECTION=TRUE

F5 C1 A6

C110
100PF

1

20% 6.3V 2 X5R 0201-1

5% 10V NP0-C0G 2 01005

B

B

A

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

TRISTAR
DRAWING NUMBER

Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

16 OF 23 16 OF 46

SHEET

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

DOCKFLEX B2B
FL5
01005
3

(USB VBUS, MENU BTN, SPEAKER, HP, HP EXTMIC, NAVAJO, ANTENNA PAC/LAT SW CTRL, MIC1 (VOICE MIC), ACC DET/ID/PWR, E75 DIFFPAIRS)
120-OHM-210MA
1
50NA @ 2.5V

FL2302
01005

120-OHM-210MA
BUTTON_TO_AP_MENU_KEY_L
1 2 1

2

BATTERY_TO_PMU_NTC 12

22

BATTERY NTC

MENU BUTTON

C176
56PF

5% 2 6.3V NP0-C0G 01005

12V-33PF
01005-1

DZ15

1

1

C2307
56PF

D
HPHONE: HS3/HS4
9 9

120-OHM-210MA
1 2 01005

FL10 FL1
01005

2

NOSTUFF

5% 16V 2 NP0-C0G 01005

120-OHM-210MA
2 1 01005

L7

D

CODEC_TO_HPHONE_HS3 CODEC_TO_HPHONE_HS4

120-OHM-210MA
1 2

CODEC_TO_HPHONE_HS3_CONN CODEC_TO_HPHONE_HS4_CONN

17

100PF

C5

1

1

C8

6.8V-100PF 01005

DZ6 1
2

1

R23

120-OHM-210MA
10

FL49
01005

5% 16V NP0-C0G 2 01005

5% 16V 2 NP0-C0G 01005

100PF

1% 1/32W MF 2 01005

100K
CODEC_TO_HPHONE_L
9 9

HPHONE_TO_CODEC_HPHONE_TEST

PP_CODEC_TO_MIC1_BIAS

2

1

PP_CODEC_TO_MIC1_BIAS_CONN

100K

R10

1

CODEC_TO_HPHONE_R

HPHONE AUDIO

9

C215
1.0UF

1

1% 1/32W MF 01005 2

120-OHM-210MA
2 01005 1

L6

MIC1 PRIMARY MIC

20% 6.3V X5R 2 0201-1

NO_XNET_CONNECTION=TRUE
1

6.8V-100PF 01005

DZ5 1
2

PER STAN, REPLACING L7 AND L6 WITH 01005 PARTS

C355
56PF

1

C359
56PF

2

XW45

5% 2 6.3V NP0-C0G 01005
9 22 9

SHORT-10L-0.1MM-SM

MIC1_TO_CODEC_N MIC1_TO_CODEC_P

5% 2 6.3V NP0-C0G 01005

1 PCB: PUT XW
AT J7.17

THIS ONE ON MLB ---> 516S1032 PLUG 516S1031 RCPT (USED ON FLEX)

BB_TO_LAT_SW2_CTL BB_TO_LAT_SW1_CTL
1

23

ANTENNA: LAT SW CTRL

105847038102829
3.3K 2 1

J7

23

R107

M-ST-SM 39 40 1 2 4

C188
56PF

1

C206
56PF

C

9

HPHONE_TO_CODEC_DET

HPHONE: HS3/HS4 CTRL, HPDET

5% 1/32W

MF 01005 1

01005 150OHM-25%-200MA-0.7DCR
3

FL69
1

C242
56PF

NOTE: RSVD ANTENNA HPHONE_TO_CODEC_DET_CONN CODEC_TO_HPHONE_L_CONN CODEC_TO_HPHONE_HS3_REF_CONN BUTTON_TO_AP_MENU_KEY_CONN_L

3 5 7 9 11 13 15 17 19 21 23

AP_TO_HEADSET_HS3_CTRL

2

01005 150OHM-25%-200MA-0.7DCR
3

FL68

5% 2 6.3V NP0-C0G 01005

AP_TO_HEADSET_HS4_CTRL_CONN CODEC_TO_HPHONE_HS3_CONN 17 6 CODEC_TO_HPHONE_HS4_REF_CONN 8 CODEC_TO_HPHONE_R_CONN 10 BATTERY_NTC_CONN
12 14 16 18 20 22 24 26 28 30 32 34 36 38 42
22 22 22

17

5% 6.3V 2 NP0-C0G 01005

5% 6.3V 2 NP0-C0G 01005

C
C4
1

17 22

AP_TO_HEADSET_HS3_CTRL_CONN AP_TO_HEADSET_HS4_CTRL_CONN

17

17 22

AP_TO_HEADSET_HS4_CTRL

1

2

6.8V-100PF
01005 2 2

DZ9

1

1

DZ10
01005

6.8V-100PF

90_TRISTAR_BI_E75_PAIR1_CONN_P 90_TRISTAR_BI_E75_PAIR1_CONN_N 90_TRISTAR_BI_E75_PAIR2_CONN_N 90_TRISTAR_BI_E75_PAIR2_CONN_P E75_TO_PMU_ACC_DETECT_CONN PP_E75_TO_TRISTAR_ACC1_CONN PP_E75_TO_TRISTAR_ACC2_CONN
17 22

10% 10V X7R-CERM 2 01005

220PF

EXTMIC_TO_CODEC_N EXTMIC_TO_CODEC_P

9 9

NOSTUFF
1

NO_XBET_CONNECTION=TRUE

PP_LDO14_2P65_CONN

25 27 29

FL16
CODEC_TO_HPHONE_HS3_REF_CONN 1

01005

120-OHM-210MA
2 01005 2

0.00

R151
0% 1/32W MF 01005 2

NO_XBET_CONNECTION=TRUE

R50

HS3/HS4 REF EXTMIC

01005 150OHM-25%-200MA-0.7DCR
23

FL495
1

31 33 35 37 1

PP_LDO14_2P65

2

17 22

CODEC_TO_HPHONE_HS4_REF_CONN 120-OHM-210MA
1

FL17

0% 1/32W MF 2 01005

0.00

CODEC_TO_HPHONE_HS3_REF 9 CODEC_TO_HPHONE_HS4_REF 9

ANTENNA: PAC VDD (2.65V)

C855
56PF
PCB: PLACE THESE XW LINKS AT DOCK CONNECTOR

6.8V-100PF
41 SM 1
17 22

DZ11 1
01005 2

1

DZ12
01005

6.8V-100PF

5% 6.3V 2 NP0-C0G 01005

2

XW21 2 XW22 2
SM

PP5V0_USB_CONN

1

B
12

5% 6.3V NP0-C0G 2 01005

56PF

C70 1
TO DO: REMOVE L20, L22 TO OPEN USB EYE? (SEE EUGENE)

CSD75202W15
CSP

Q2

CSD75202W15
CSP

Q2

R617
0.002

1

B

(2 OF 2) PP5V0_USB_PROT
A2 A3 D1 S B1 1 A1 B1

(1 OF 2)
B2 S D2 C2 C3
22 17

PP5V0_USB_CONN

PCB: PLACE NEAR J7 (DESENSE CAPS)

VBUS

B3 G1

C153
1.0UF
C1

G2

1

C119

16

FROM TRISTAR TRISTAR_TO_PMU_OVP_SW_EN_L

15.00K 2 1
1% 1/32W MF 01005

R58

20% 10V 2 X5R-CERM 0201-1

REVERSE_GATE
1

R73
1% 1/20W MF 201

1

0.01UF

C368

10% 2 25V X5R-CERM 0201

100PF 5% 16V 0.01UFNP0-C0G
01005

C12 1
2

5% 6.3V NP0-C0G 2 01005

56PF

C71 1
NOSTUFFTCM0605-1
1
SYM_VER-2

MF

1% 0201 1/20W

90-OHM-50MA 4

L20

R618
1 MF

0.00 2
1% 0201 1/20W

C240 1
USB_CONN_SNUB

2 2

3 3

90_TRISTAR_BI_E75_PAIR1_P 90_TRISTAR_BI_E75_PAIR1_N 90_TRISTAR_BI_E75_PAIR2_N 90_TRISTAR_BI_E75_PAIR2_P

16 22 16 22

E75 DIFFPAIRS

OVP_GATE

2

100K 1

R74

16

PP5V0_USB_RPROT TO TRISTAR

5% 1/20W MF 2 201

5.1K

10% 25V 2 X5R-CERM 0201

100PF

C13 1 C879
56PF
5% 16V NP0-C0G 01005 1 1

5% 16V NP0-C0G 2 01005

C878
56PF

5% 16V NP0-C0G 2 01005

27PF

16 22 16 22

2

5% 16V 2 NP0-C0G 01005

4 TCM0605-1 NOSTUFF 90-OHM-50MA

1

SYM_VER-2

R619 1 0.00 2
MF 1% 0201 1/20W

L22

R1301 1.00K 2
01005 5% MF

R620 1 0.00 2
1/32W MF 1% 0201 1/20W

E75_TO_PMU_ACC_DETECT 13

16

C913
100PF
NOSTUFF

FL60
1 1

10-OHM-750MA
1

C914
100PF
5% 16V NP0-C0G 01005

2 01005-1

PP_E75_TO_TRISTAR_ACC1 16

5% 16V NP0-C0G 2 01005

2

FL53
2

ACCESSORY: DETECT, ID, PWR

10-OHM-750MA
1 01005-1

NOSTUFF

PP_E75_TO_TRISTAR_ACC2 16

A
SPEAKER: SPEAKER LEADS VSENSE,
SPEAKER_TO_SPKAMP_VSENSE_P SPEAKER_TO_SPKAMP_VSENSE_N

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

DOCKFLEX B2B
DRAWING NUMBER

Apple Inc.
R

051-9584 2.0.0

SIZE

D

15 15

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
SPKAMP_TO_SPEAKER_OUT_CONN_P SPKAMP_TO_SPEAKER_OUT_CONN_N
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

22 15 22 15

17 OF 23 17 OF 46

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8

7

6

5

4

3

2

1

8

7

6
19 18

5
PP_SAGE_TO_TOUCH_VCPL
1

4

3
-12V

2

1

D404 (B2B,DRIVER ICS)
D

SAGE2 C0
C381
0.1UF
1

343S0628: B0 APN FOR PROTO1 343S0645: C0 APN FOR EVT1

C306
0.1UF

1

C315
1UF

1

C324
1UF

1

C331
1UF

C365 1
10% 16V X5R-CERM 2 0201

10% 16V 2 X5R-CERM 0201

10% 16V 2 X5R-CERM 0201

10% 16V 2 X6S-CERM 0402

10% 16V 2 X6S-CERM 0402

10% 16V 2 X6S-CERM 0402

0.1UF

18

PP_SAGE_TO_TOUCH_VCPH
13.5V

C170
0.1UF

1

PP_SAGE_VCPL_F 18

XW79 SM
19 14

10% 16V X5R-CERM 2 0201

C163
0.1UF

3.5V

1

PN5V7_SAGE_AVDDN

1

2 1

PN5V7_SAGE_AVDDN_FILT

10% 6.3V 2 X5R 201

D
PP1V8
2 3 4 5 6 7 10 11 12 14 19 20 21

AVDDL1 H5

VCPH A1

VCPL F1

VCPL_F E2

TO CLAMP THE NEGATIVE RAIL

343S0574

OMIT_TABLE SAGE_PANEL_IN IS SENSITIVE KEEP THESE NETS FROM XTALK TOUCH_TO_SAGE_SENSE_IN<4> TOUCH_TO_SAGE_SENSE_IN<3> TOUCH_TO_SAGE_SENSE_IN<5> TOUCH_TO_SAGE_SENSE_IN<0> TOUCH_TO_SAGE_SENSE_IN<12> TOUCH_TO_SAGE_SENSE_IN<7> TOUCH_TO_SAGE_SENSE_IN<10> TOUCH_TO_SAGE_SENSE_IN<1> TOUCH_TO_SAGE_SENSE_IN<11> TOUCH_TO_SAGE_SENSE_IN<2> TOUCH_TO_SAGE_SENSE_IN<13> TOUCH_TO_SAGE_SENSE_IN<14> TOUCH_TO_SAGE_SENSE_IN<8> TOUCH_TO_SAGE_SENSE_IN<9> TOUCH_TO_SAGE_SENSE_IN<6>

20% 10V X5R-CERM 2 0402-1

AVDDH1 AVDDH2 AVDDH3 AVDDH4

20% 2 10V X5R-CERM 0402-1

GDZ-0201

VDDIO C3

CUMULUS C0
(TURN ON LATER THAN PP1V8_GRAPE) (TURN OFF SAME TIME AS PP1V8_GRAPE)
14

C149
10UF

A

D2 A3 F3 F6

GDZT2R6.2B
K

DZ4

18 14

PP5V7_SAGE_AVDDH
1

5.45-5.98V

C156 1
10UF

C165
0.1UF

20% 2 4V X5R 01005

XW36 SM
18

SAGE2-C06
E4 D4 C4 B4 A4 A6 B6 C6 D6 E6 E8 D8 C8 B8 A8 G1 H1 J1 K1 L1 G2 H2 J2 K2 L2 L3 K3 J3 H3 G3 L4 K4 J4 H4 G4 D3 A2 F2 SNS_IN0 SNS_IN1 SNS_IN2 SNS_IN3 SNS_IN4 SNS_IN5 SNS_IN6 SNS_IN7 SNS_IN8 SNS_IN9 SNS_IN10 SNS_IN11 SNS_IN12 SNS_IN13 SNS_IN14 DRV_IN0 DRV_IN1 DRV_IN2 DRV_IN3 DRV_IN4 DRV_IN5 DRV_IN6 DRV_IN7 DRV_IN8 DRV_IN9 DRV_IN10 DRV_IN11 DRV_IN12 DRV_IN13 DRV_IN14 DRV_IN15 DRV_IN16 DRV_IN17 DRV_IN18 DRV_IN19 VBIAS VCPH_REF/EN VCPL_REF/EN VBST_OUTH VBST_OUTL AGND1 AGND2 AGND3 AGND4 AGND5 AGND6 L_X L_Y CSP SNS_OUT0 SNS_OUT1 SNS_OUT2 SNS_OUT3 SNS_OUT4 SNS_OUT5 SNS_OUT6 SNS_OUT7 SNS_OUT8 SNS_OUT9 SNS_OUT10 SNS_OUT11 SNS_OUT12 SNS_OUT13 SNS_OUT14 DRV_OUT0 DRV_OUT1 DRV_OUT2 DRV_OUT3 DRV_OUT4 DRV_OUT5 DRV_OUT6 DRV_OUT7 DRV_OUT8 DRV_OUT9 DRV_OUT10 DRV_OUT11 DRV_OUT12 DRV_OUT13 DRV_OUT14 DRV_OUT15 DRV_OUT16 DRV_OUT17 DRV_OUT18 DRV_OUT19 E5 D5 C5 B5 A5 A7 B7 C7 D7 E7 E9 D9 C9 B9 A9 G6 H6 J6 K6 L6 G7 H7 J7 K7 L7 L8 K8 J8 H8 G8 L9 K9 J9 H9 G9

U15

CUMULUS_IN IS SENSITIVE KEEP THESE NETS FROM XTALK SAGE_TO_CUMULUS_IN<4> 18 SAGE_TO_CUMULUS_IN<3> 18 SAGE_TO_CUMULUS_IN<5> 18 SAGE_TO_CUMULUS_IN<0> 18 SAGE_TO_CUMULUS_IN<12> 18 SAGE_TO_CUMULUS_IN<7> 18 SAGE_TO_CUMULUS_IN<10> 18 SAGE_TO_CUMULUS_IN<1> 18 SAGE_TO_CUMULUS_IN<11> 18 SAGE_TO_CUMULUS_IN<2> 18 SAGE_TO_CUMULUS_IN<13> 18 SAGE_TO_CUMULUS_IN<14> 18 SAGE_TO_CUMULUS_IN<8> 18 SAGE_TO_CUMULUS_IN<9> 18 SAGE_TO_CUMULUS_IN<6> 18 SAGE_TO_TOUCH_VSTM_OUT<8> SAGE_TO_TOUCH_VSTM_OUT<6> SAGE_TO_TOUCH_VSTM_OUT<12> SAGE_TO_TOUCH_VSTM_OUT<1> SAGE_TO_TOUCH_VSTM_OUT<7> SAGE_TO_TOUCH_VSTM_OUT<15> SAGE_TO_TOUCH_VSTM_OUT<14> SAGE_TO_TOUCH_VSTM_OUT<18> SAGE_TO_TOUCH_VSTM_OUT<5> SAGE_TO_TOUCH_VSTM_OUT<9> SAGE_TO_TOUCH_VSTM_OUT<10> SAGE_TO_TOUCH_VSTM_OUT<4> SAGE_TO_TOUCH_VSTM_OUT<19> SAGE_TO_TOUCH_VSTM_OUT<13> SAGE_TO_TOUCH_VSTM_OUT<16> SAGE_TO_TOUCH_VSTM_OUT<3> SAGE_TO_TOUCH_VSTM_OUT<2> SAGE_TO_TOUCH_VSTM_OUT<0> SAGE_TO_TOUCH_VSTM_OUT<11> SAGE_TO_TOUCH_VSTM_OUT<17> LCM_TO_AP_HIFA_BSYNC
3 18 19 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18

18

PP5V1_GRAPE_VDDH PP_CUMULUS_VDDCORE
1

PP1V8_CUMULUS_VDDLDO
1

1

2

PP1V8_GRAPE

12 18

18 18

C372
1.0UF

18 18 18 18

C369
10UF
1

20% 10V 2 X5R-CERM 0402-1

PP_CUMULUS_VDDANA

20% 6.3V 2 X5R 0201-1

C370
4.7UF

1

C371
4.7UF
VDDANA B1 VDDCORE C1 VDDH C8 C5 F4 VDDLDO A1

SAGE_VBIAS_DRAIN
3

18 18 18

20% 2 6.3V X5R-CERM1 402

20% 2 6.3V X5R-CERM1 402

220K 2 1
5% 1/32W MF 01005

R86

18

D

VDDIO

Q6
RV1C002UN
SM

C366
0.1UF
2 1

18 18 18 18

45_PROX_TO_CUMULUS_RX

11

CUMULUS_IN IS SENSITIVE SAGE_TO_CUMULUS_IN<2> 18 SAGE_TO_CUMULUS_IN<1> 18 SAGE_TO_CUMULUS_IN<6> 18 SAGE_TO_CUMULUS_IN<7> 18 SAGE_TO_CUMULUS_IN<4> 18 SAGE_TO_CUMULUS_IN<8> 18 SAGE_TO_CUMULUS_IN<3> 18 SAGE_TO_CUMULUS_IN<5> 18 SAGE_TO_CUMULUS_IN<9> 18 SAGE_TO_CUMULUS_IN<0> 18 SAGE_TO_CUMULUS_IN<14> 18 SAGE_TO_CUMULUS_IN<10> 18 SAGE_TO_CUMULUS_IN<13> 18 SAGE_TO_CUMULUS_IN<11> 18 SAGE_TO_CUMULUS_IN<12> 45_PROX_TO_CUMULUS_RX_IN
18

G S
1

2

SAGE_DUMP_GATE

C

1000PF
1 2

C79

45_PROX_TO_CUMULUS_RX_FILT

10% 6.3V X5R-CERM 01005

1 1% 1/32W

22.1K

R26

2 MF 01005

C130 1
5% 16V NP0-C0G 2 01005

27PF

PP7 P4MM SM PP PP8 P4MM SM PP
3

1 1

B9 B8 A9 B7 B6 A8 B5 B4 A7 B3 A6 A3 A5 A4 B2 A2 E4 F1 D3 D2 E1

IN0_0 IN1_0 IN2_0 IN3_0 IN4_0 IN5_0 IN6_0 IN7_0 IN8_0 IN9_0 IN10_0 IN11_0 IN12_0 IN13_0 IN14_0 IN14_1 H_CS* H_INT* H_SCLK H_SDI H_SDO JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS

CUMULUS-C0
WLBGA

U12

AP_TO_TOUCH_SPI1_CS_L 3 TOUCH_TO_AP_INT_L 3 AP_TO_TOUCH_SPI1_CLK 3 AP_TO_TOUCH_SPI1_MOSI
3

VSTM_0 VSTM_1 VSTM_2 VSTM_3 VSTM_4 VSTM_5 VSTM_6 VSTM_7 VSTM_8 VSTM_9 VSTM_10 VSTM_11 VSTM_12 VSTM_13 VSTM_14 VSTM_15 VSTM_16 VSTM_17 VSTM_18 VSTM_19

E9 E5 F7 E6 E7 F8 G9 D6 D7 D8 F9 D5 F6 F5 G4 E8 G8 G7 G6 G5 G1 D4 F2 F3

CUMULUS_TO_SAGE_VSTM_OUT<2> 18 CUMULUS_TO_SAGE_VSTM_OUT<5> 18 CUMULUS_TO_SAGE_VSTM_OUT<16> 18 CUMULUS_TO_SAGE_VSTM_OUT<18> 18 CUMULUS_TO_SAGE_VSTM_OUT<17> 18 CUMULUS_TO_SAGE_VSTM_OUT<11> 18 CUMULUS_TO_SAGE_VSTM_OUT<13> 18 CUMULUS_TO_SAGE_VSTM_OUT<7> 18 CUMULUS_TO_SAGE_VSTM_OUT<3> 18 CUMULUS_TO_SAGE_VSTM_OUT<9> CUMULUS_TO_SAGE_VSTM_OUT<10> CUMULUS_TO_SAGE_VSTM_OUT<1> 18 CUMULUS_TO_SAGE_VSTM_OUT<4> 18 CUMULUS_TO_SAGE_VSTM_OUT<8> 18 CUMULUS_TO_SAGE_VSTM_OUT<12> 18 CUMULUS_TO_SAGE_VSTM_OUT<0> 18 CUMULUS_TO_SAGE_VSTM_OUT<15> 18 CUMULUS_TO_SAGE_VSTM_OUT<19> 18 CUMULUS_TO_SAGE_VSTM_OUT<14> 18 CUMULUS_TO_SAGE_VSTM_OUT<6> 18 NOTE: LCM_TO_AP_HIFA_BSYNC_BUFF CUMULUS_TO_SAGE_BOOST_EN 18 1 U12_GPIO_3 PP P4MM SM CUMULUS_TO_SAGE_GCM_SEL 18 CUMULUS_TO_PROX_RX_EN_1V8
1

R1211
1.00M
5% 1/32W MF 01005 2

10% 16V X5R-CERM 0201

CUMULUS_TO_SAGE_VSTM_OUT<8> CUMULUS_TO_SAGE_VSTM_OUT<6> 18 CUMULUS_TO_SAGE_VSTM_OUT<12> 18 CUMULUS_TO_SAGE_VSTM_OUT<1> 18 CUMULUS_TO_SAGE_VSTM_OUT<7> 18 CUMULUS_TO_SAGE_VSTM_OUT<15> 18 CUMULUS_TO_SAGE_VSTM_OUT<14> 18 CUMULUS_TO_SAGE_VSTM_OUT<18> 18 CUMULUS_TO_SAGE_VSTM_OUT<5>
18 18

C

THESE ARE ROUTED TOGETHER SPECIAL - CANNOT SWAP SPECIAL - CANNOT SWAP

2

18

PP_SAGE_VCPL_F
A

XW37 SM
1

DSF01S30SC
NOSTUFF

D2 SM-201

K

CUMULUS_TO_SAGE_VSTM_OUT<4> 18 CUMULUS_TO_SAGE_VSTM_OUT<19> 18 CUMULUS_TO_SAGE_VSTM_OUT<13> 18 CUMULUS_TO_SAGE_VSTM_OUT<16> 18 CUMULUS_TO_SAGE_VSTM_OUT<3> 18 CUMULUS_TO_SAGE_VSTM_OUT<2> 18 CUMULUS_TO_SAGE_VSTM_OUT<0> 18 CUMULUS_TO_SAGE_VSTM_OUT<11> 18 CUMULUS_TO_SAGE_VSTM_OUT<17>
18

TOUCH_TO_AP_SPI1_MISO

MF 01005

R136 1 2
10.2

1% 1/32W

TOUCH_TO_AP_SPI1_MISO_R C4 C3 E2 C6

GPIO_1/CK GPIO_2/SD GPIO_3 GPIO_4

SAGE_VBIAS
18 18

BSYNC K5 GCM_TEST F9 GO F7 VCM_IN J5 I2C_SCL F5 I2C_SDA G5 BOOST_EN B2

PP11 P4MM
1
SM PP

PP9
11

SAGE_TO_TOUCH_VCPH_REF SAGE_TO_TOUCH_VCPL_REF

CUMULUS_TO_SAGE_GCM_SEL 18

0.01UF
TM_ACS* C2 TM_OVR G3

C150

1

B
3 45_AP_TO_TOUCH_CLK32K_RESET_L (ALSO A RESET IF CLOCK STOPS)

18

PP1V8_CUMULUS_VDDLDO
18

10% 6.3V X5R 2 01005

0.01UF

C147

1

C137 1
0.1UF
10% 6.3V X5R 2 201

10% 6.3V X5R 2 01005

PP_SAGE_VBST_OUTH B1 PP_SAGE_VBST_OUTL E1 PP_SAGE_LX C1 PP_SAGE_LY D1

TOUCH_TO_SAGE_VCM_IN

18

CUMULUS_TO_PROX_TX_EN_1V8_L AP_TO_TOUCH_GRAPE_RESET_L

3

E3 BCFG_RTCK D1 CLKIN/RESET* D9 RSTOVR* GND C7 C9 G2

R79

B
CUMULUS_TO_SAGE_BOOST_EN

5% 1/32W MF 2 01005

100K
1

PP18 P4MM
18

1

PP1V8_GRAPE

12 18

0.33UF

C321 1
20% 20V 2 TANT 0402

1000PF

C328

1

PP12
ON MLB ---> 516S1061 PLUG 516S1060 RCPT (ON FLEX)

P4MM
SM

PP

1

10% 25V X7R-CERM 2 0201

1000PF

C349 1

10% 25V X7R-CERM 2 0201 2

L21

10UH-0.32A-1.56OHM
PSB12101T-SM

504459-4210
M-ST-SM 43 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 44

J4

18 14

PP5V7_SAGE_AVDDH

TOUCH B2B
XW7
18

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42

XW13

18

A

SAGE_TO_TOUCH_VSTM_OUT<17> SAGE_TO_TOUCH_VSTM_OUT<16> SAGE_TO_TOUCH_VSTM_OUT<15> SAGE_TO_TOUCH_VSTM_OUT<14> SAGE_TO_TOUCH_VSTM_OUT<13> SAGE_TO_TOUCH_VSTM_OUT<12> SAGE_TO_TOUCH_VSTM_OUT<11> SAGE_TO_TOUCH_VSTM_OUT<0> SAGE_TO_TOUCH_VSTM_OUT<18> SAGE_TO_TOUCH_VSTM_OUT<19>

18 18 18 18 18 18 18 18 18 18

R17 R16 R15 R14 R13 R12 R11

NO_XNET_CONNECTION=TRUE

XW18 SM
18

5

TOUCH_TO_SAGE_VCM_IN_CONN

1

2

TOUCH_TO_SAGE_VCM_IN

18

NO_XNET_CONNECTION=TRUE

XW19 SM
19 18 18 19

74AUP2G3404GN SOT1115
14

1 2 PP_SAGE_TO_TOUCH_VCPL_CONN PP_SAGE_TO_TOUCH_VCPL R0_RIGHT NO_XNET_CONNECTION=TRUE R18 R19

LCM_TO_AP_HIFA_BSYNC_BUFF CUMULUS_TO_PROX_TX_EN_BUFF

6 1Y 4 2Y GND 2

XW23 SM

100K
18

R361
5% 1/32W MF 01005 2

11

18

PP_SAGE_TO_TOUCH_VCPH_CONN

1

2

PP_SAGE_TO_TOUCH_VCPH

8

7

6

5

4

1

C320

1UF

2

C5 C4 C0 C3 GS1 C2 C1 GS0 VGL 19 VGH R10 R7 R1 R5 R6 R8 R9 R4 R3 R2 R0_LEFT

TOUCH_TO_SAGE_SENSE_IN<5> TOUCH_TO_SAGE_SENSE_IN<4> TOUCH_TO_SAGE_SENSE_IN<0> 18 TOUCH_TO_SAGE_SENSE_IN<3> 18 TOUCH_TO_SAGE_SENSE_IN<11> 18 TOUCH_TO_SAGE_SENSE_IN<2> 18 TOUCH_TO_SAGE_SENSE_IN<1> 18 TOUCH_TO_SAGE_SENSE_IN<10> 18 PP_SAGE_TO_TOUCH_VCPL_CONN 18 PP_SAGE_TO_TOUCH_VCPH_CONN 18 SAGE_TO_TOUCH_VSTM_OUT<10> 18 SAGE_TO_TOUCH_VSTM_OUT<7> 18 SAGE_TO_TOUCH_VSTM_OUT<1> 18 SAGE_TO_TOUCH_VSTM_OUT<5> 18 SAGE_TO_TOUCH_VSTM_OUT<6> 18 SAGE_TO_TOUCH_VSTM_OUT<8> 18 SAGE_TO_TOUCH_VSTM_OUT<9> 18 SAGE_TO_TOUCH_VSTM_OUT<4> 18 SAGE_TO_TOUCH_VSTM_OUT<3> 18 SAGE_TO_TOUCH_VSTM_OUT<2> 18 SAGE_TO_TOUCH_VSTM_OUT<0>
18 18 18

2 4 6

TOUCH_TO_SAGE_SENSE_IN<6> 18 TOUCH_TO_SAGE_SENSE_IN<13> 18 TOUCH_TO_SAGE_SENSE_IN<7> 18 SAGE_TO_TOUCH_VCPH_REF_CONN 18 SAGE_TO_TOUCH_VCPL_REF_CONN 18 TOUCH_TO_SAGE_VCM_IN_CONN 18 TOUCH_TO_SAGE_SENSE_IN<12> 18 TOUCH_TO_SAGE_SENSE_IN<9> 18 TOUCH_TO_SAGE_SENSE_IN<8> 18 TOUCH_TO_SAGE_SENSE_IN<14> 18

C6 GS3 C7 NO_XNET_CONNECTION=TRUE VGH_REF VGL_REF SM 2 SAGE_TO_TOUCH_VCPH_REF VCOM 18 SAGE_TO_TOUCH_VCPH_REF_CONN 1 GS2 NO_XNET_CONNECTION=TRUE C9 C8 SM 1 2 SAGE_TO_TOUCH_VCPL_REF GS4 18 SAGE_TO_TOUCH_VCPL_REF_CONN

0603-LLP TANT 25V 20%

1000PF

C346

1

10% 25V X7R-CERM 2 0201

1000PF

C364 1

10% 25V X7R-CERM 2 0201

C2 B3 F4 F8 E3 L5

SM PP

PP1V8_GRAPE
1

12 18

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

U5

VCC

R2

1A 1 2A 3

5% 1/32W MF 2 01005

100K
LCM_TO_AP_HIFA_BSYNC

D404 (TOUCH B2B, DRIVER ICS)
DRAWING NUMBER

Apple Inc.
3 18 19 R 18

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

CUMULUS_TO_PROX_TX_EN_1V8_L

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

18 OF 23 18 OF 46

SHEET

3

2

1

8

7

6

5

4

3

2

1

LCM B2B
2

120-OHM-210MA
1 01005

FL25

PN5V7_SAGE_AVDDN

14 18

D
1 1

80-OHM-0.2A-0.4-OHM
2 0201-1 1

FL18

D

C610
56PF

PP1V8 2

3 4 5 6 7 10 11 12 14 18 19 20 21

NO_XNET_CONNECTIO=TRUE

5% 16V 2 NP0-C0G 01005

C42

1

5% 6.3V 2 NP0-C0G 01005

56PF

C46

10% 6.3V 2 X5R 201

0.1UF

80-OHM-0.2A-0.4-OHM
1 0201-1 1 2

FL26

PP5V7_TO_LCD_AVDDH

14

C30

LCM CONNECTOR
THIS ONE ON MLB ---> 516S1066 PLUG 516S1065 RCPT (FLEX)

5% 16V 2 NP0-C0G 01005

56PF

20% 6.3V X5R-CERM 2 0402

2.2UF

C43 1

20% 6.3V X5R-CERM 2 0402

2.2UF

C48

1

20% 6.3V X5R-CERM 2 0402

2.2UF

C49 1

20% 6.3V X5R-CERM 2 0402

2.2UF

C59

1

120-OHM-210MA
1 01005 1 2

FL27

SPECIAL Z = 0.33 MM LCD_PWR_EN
1
13 14

R932

C40

C

18

PP_SAGE_TO_TOUCH_VCPL
90-OHM-50MA TCM0605-1
SYM_VER-2

L2

1 1/32W

0.00 2
0% MF 01005

18

PP_SAGE_TO_TOUCH_VCPL_CONN

M-ST-SM 30 29

AA22LB-P

J5

5% 2 6.3V NP0-C0G 01005

56PF

R971
100K

1% 1/32W MF 2 01005

C

BOMOPTION=NOSTUFF PN5V7_LCM_AVDDN_CONN PP5V7_LCD_AVDDH_CONN PP1V8_LCM_CONN LCD_PWR_EN_CONN LCD_RESET_L_CONN LCD_HIFA_BSYNC_CONN LCD_PANIC_L_CONN LCD_PIFA 22 LCD_BL_CA_CONN
22 22

1
7 7

4

90_AP_TO_LCM_MIPI_DATA0_P 90_AP_TO_LCM_MIPI_DATA0_N

90_LCM_MIPI_DATA0_CONN_P 90_LCM_MIPI_DATA0_CONN_N
90-OHM-50MA TCM0605-1
SYM_VER-2

2 4 6 8 10

1 3 5 7 9 11 13 15 17 19 21 23 25 27 31

2

3

L9

1
7 7

4

1

1.00K 2
5% 1/32W MF 01005

R4

LCM_TO_AP_PIFA 3 NOSTUFF

90_AP_TO_LCM_MIPI_DATA1_P 90_AP_TO_LCM_MIPI_DATA1_N
90-OHM-50MA TCM0605-1
SYM_VER-2

90_LCM_MIPI_DATA1_CONN_P 90_LCM_MIPI_DATA1_CONN_N

12 14 16 18 20

L8

2

3

1
7 7

4

90_AP_TO_LCM_MIPI_CLK_P 90_AP_TO_LCM_MIPI_CLK_N

90_LCM_MIPI_CLK_CONN_P 90_LCM_MIPI_CLK_CONN_N
90-OHM-50MA TCM0605-1
SYM_VER-2

22 24 26 28

LCD_BL_CC1_CONN LCD_BL_CC2_CONN

1

C24

2

3 1

L10

5% 6.3V 2 NP0-C0G 01005

56PF

120-OHM-210MA
1 2 01005 1

FL34

4

7 7

90_AP_TO_LCM_MIPI_DATA2_P 90_AP_TO_LCM_MIPI_DATA2_N
1

L1 90-OHM-50MA
TCM0605-1
SYM_VER-2

90_LCM_MIPI_DATA2_CONN_P 90_LCM_MIPI_DATA2_CONN_N

LCM_TO_AP_HIFA_BSYNC

3 18

32

2 4

3

C19

7 7

90_AP_TO_LCM_MIPI_DATA3_N 90_AP_TO_LCM_MIPI_DATA3_P

90_LCM_MIPI_DATA3_CONN_N 90_LCM_MIPI_DATA3_CONN_P
20 18 12 10 6 4 2 3 5 7 11 14 19 21

5% 2 6.3V NP0-C0G 01005 1

56PF

2

3

100K 2
5% 1/32W MF 01005

R32

PP1V8 2

3 4 5 6 7 10 11 12 14 18 19 20 21

B

PP1V8
1

150OHM-25%-200MA-0.7DCR

FL37
01005

B
RESET_1V8_L
2 12 13 14 16 22 23

R62

1

2

NOSTUFF

1% 1/32W MF 2 01005 1

100K

NOSTUFF

120-OHM-210MA
1 2 01005 1 1

FL61

0.00 2
0% 1/32W MF 01005

R75

PMU_AP_TO_LCM_RESET_L

13

R31

1% 1/32W MF 2 01005

100K

C41

5% 6.3V 2 NP0-C0G 01005 1

56PF

NOSTUFF

REFER TO RADAR 12410499. THIS IS PART OF BUILD MATRIX TO POTENTIALLY IMPLEMENT LCD PANIC FUNCTION AP_TO_LCM_RESET_L
3

FL35
2 0201-1

PP_LCM_BL_CAT2 14

240-OHM-0.2A-0.8-OHM

FL24
0201-1

1

2

PP_LCM_BL_CAT1 14

1

C10

1

5% 2 16V NP0-C0G 01005

56PF

C15

240-OHM-0.2A-0.8-OHM

5% 16V 2 NP0-C0G 01005 1

56PF

FL36
2 0201-1

A
LCD_DESENSE_CONN

PP_LCM_BL_ANODE 14

1

C14

240-OHM-0.2A-0.8-OHM

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

5% 16V 2 NP0-C0G 01005 1

56PF

LCM CONNECTOR
DRAWING NUMBER

C18

Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

5% 16V 2 NP0-C0G 01005

56PF

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

19 OF 23 19 OF 46

SHEET

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

SENSORS
THIS PART OUTSIDE OF SHIELD
D
FL38
01005

THESE PARTS INSIDE OF SHIELD

COMPASS DEVICE: 338S1014 COMPASS INTERPOSER: 998-5120
20 12

COMPASS
20

GYRO
AP3GDL20H, APN 338S1158
PP3V0_IMU
1

D
PP1V8
2 3 4 5 6 7 10 11 12 14 18 19 20 21

150OHM-25%-200MA-0.7DCR
20 12

150OHM-25%-200MA-0.7DCR
PP1V8_COMP
1 2 01005 1

FL39

PP3V0_IMU

1

2

PP3V0_COMP B1
1

PP1V8

C298
1.0UF

OMIT_TABLE

C300
0.1UF

AK8963C
CSP D1 CAD0 D2 CAD1 C2 TST1 B3 RSV C3 TRG SCL/SK A3 SDA/SI A4
CSB* A2

15 VDD 16

20% 6.3V 2 X5R 0201-1

VDD VID

C4

21 19 14 11 6 7 2 3 4 5 10 12 18 20

C345
0.1UF

1

20% 4V 2 X5R 01005

20% 6.3V 2 X5R 0201-1

1.0UF

C347

C344
0.1UF

1

20% 4V X5R 2 01005

U16

20% 4V 2 X5R 01005

PWRTERM2GND

FL751
I2C_SCL_COMP I2C_SDA_COMP
1

120-OHM-210MA
2

RES/VDD AP_TO_I2C1_SCL
3 20

OMIT_TABLE VDD_IO

01005

FL752
1

120-OHM-210MA
2

AP3GDL20HAA18 LGA AP_BI_I2C1_SDA
3 20 19 18 14 12 11 10 7 6 5 4 3 2 21 20 3

U8

SO B4 DRDY A1 COMP_INT2

01005

PP1V8 GYRO_TO_AP_INT2

FL753
1

120-OHM-210MA
2

NO CAMERA VSYNC PIN
3 3

5 CS 6 DRDY/ INT2 8 DEN 7 INT1

SCL/SPC 2 SDA/SDI/SDO 3 SDO/SA0 4 RES0 9 RES1 10 RES2 11 13 GND 12 GND
CAP 14

1

AP_TO_I2C0_SCL AP_BI_I2C0_SDA

3 13 14 15 16 3 13 14 15 16

COMPASS_TO_AP_INT_2

01005
20

GYRO_TO_AP_INT1

PP1V8_COMP

D4 RST*

VSS C1

C

11V CHARGE PUMP GYRO_CP
1

TO DO: ADD ALTERNATE AICHI COMPASS (APN 338S1133)

C11

C

10% 25V 2 X5R-CERM 0201

0.01UF

ACCELEROMETER
AP2DHAA, APN 338S1114
20 12

PP3V0_IMU

PP1V8

2 3 4 5 6 7 10 11 12 14 18 19 20 21

C334 1
1.0UF

B

20% 6.3V 2 X5R 0201-1

0.01UF

C336

1

10% 6.3V 2 X5R 01005

C997
0.1UF
8 7

1

20% 4V X5R 2 01005

B

VDD VDD_IO

U18
AP2DHAA24
LGA 4 CS SCL/SPC 1 SDA/SDI/SDO 2 SDO/SA0 3 AP_TO_I2C1_SCL AP_BI_I2C1_SDA
3 20 3 20

NEED TO CHECK CONNECTION

12 RES 11 RES 10 RES 6 INT1 5 INT2

3 3

ACCEL_TO_AP_INT1 ACCEL_TO_AP_INT2

RES 13 RES 14 GND 9

NEED TO CHECK CONNECTION

TO DO: VERIFY CONNECTIONS ON ACCEL (CS, SDO PINS)

A

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

OSCAR + SENSORS
DRAWING NUMBER

Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

20 OF 23 20 OF 46

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7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

CAM0: MAIN CAMERA CONNECTOR
D
120-OHM-210MA
7

D
FL22
01005 1

45_AP_TO_CAM_RF_CLK

1

2 1

C31

5% 6.3V 2 NP0-C0G 01005

56PF

C84

5% 6.3V 2 NP0-C0G 01005

56PF

120-OHM-210MA
7

FL28
01005

AP_TO_CAM_RF_SHUTDOWN1

2

120-OHM-210MA
15

FL29
01005

100K

R721
5% 1/32W MF 01005 2

CAM0_TO_LEDDRV_STROBE_EN

1

2

C376 1
5% 6.3V NP0-C0G 2 01005

120-OHM-210MA
15 7

FL30
01005

56PF

THIS ONE ON MLB --->

516S0940 PLUG 516S0939 RCPT (USED ON FLEX)

AP_BI_CAM_RF_SDA

1

2

C
15 7

120-OHM-210MA
AP_TO_CAM_RF_SCL
1 01005 2

FL31

C361
56PF

1

5% 6.3V NP0-C0G 2 01005

BB35-PA
M-ST-SM

J3

1

90-OHM-50MA TCM0605-1
SYM_VER-2

L34

4

C
90_CAM0_TO_AP_MIPI_DATA3_P 90_CAM0_TO_AP_MIPI_DATA3_N
7 7

33

34
2 3

C353 1
5% 6.3V NP0-C0G 2 01005

56PF

10-OHM-750MA
12 11

FL43
01005-1

12

PP2V8_CAM_AVDD

1 1

2

PGND_CAM0_AF_RET PP2V5_CAM0_AF_CONN PP1V2_CAM0_CONN

C82
1.0UF

0.07 OHMS

C287
1.0UF

1

1

C352
56PF

20% 6.3V 2 X5R 0201-1

20% 6.3V 2 X5R 0201-1

5% 2 6.3V NP0-C0G 01005

AP_BI_CAM_RF_SCL_CONN AP_BI_CAM_RF_SDA_CONN CAM0_TO_LEDDRV_STROBE_EN_CONN PP2V8_CAM0_CONN PP1V8_CAM0_CONN AP_TO_CAM_RF_SHUTDOWN_CONN

FERR-22-OHM-1A-0.065-OHM
18 14 12 11 10 7 6 5 4 3 2 21 20 19

L28
0201

PP1V8

1

2

NO_XNET_CONNECTIO=TRUE

C351 1
5% 6.3V NP0-C0G 2 01005

56PF

45_AP_TO_CAM_RF_CLK_CONN

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32

L33 90-OHM-50MA
90_CAM0_MIPI_DATA3_CONN_P 90_CAM0_MIPI_DATA3_CONN_N 90_CAM0_MIPI_DATA2_CONN_P 90_CAM0_MIPI_DATA2_CONN_N 90_CAM0_MIPI_CLK_CONN_P 90_CAM0_MIPI_CLK_CONN_N 90_CAM0_MIPI_DATA1_CONN_P 90_CAM0_MIPI_DATA1_CONN_N 90_CAM0_MIPI_DATA0_CONN_P 90_CAM0_MIPI_DATA0_CONN_N
1 TCM0605-1
SYM_VER-2

4

2

3

90_CAM0_TO_AP_MIPI_DATA2_P 90_CAM0_TO_AP_MIPI_DATA2_N

7 7

L37 90-OHM-50MA
1 TCM0605-1
SYM_VER-2

4

90_CAM0_TO_AP_MIPI_CLK_P 90_CAM0_TO_AP_MIPI_CLK_N
2 3

7 7

CAM0: 4-LANE MIPI

1

90-OHM-50MA TCM0605-1
SYM_VER-2

L38

4

2

3

90_CAM0_TO_AP_MIPI_DATA1_P 90_CAM0_TO_AP_MIPI_DATA1_N

7 7

NO_XNET_CONNECTIO=TRUE

FERR-22-OHM-1A-0.065-OHM
19 18 14 12 11 10 7 6 5 4 3 2 21 20

L29
0201

35

36
1

90-OHM-50MA TCM0605-1
SYM_VER-2

L36

4

PP1V8

1

2

PP1V8_CAM0_REG
2 3

B

C249 1
1.0UF
20% 6.3V 2 X5R 0201-1

90_CAM0_TO_AP_MIPI_DATA0_P 90_CAM0_TO_AP_MIPI_DATA0_N

7 7

B

A1 VIN B1 VEN ROUTING CRITICAL, FOLLOW N41 3 AP_TO_CAM_RF_VDDCORE_EN

LP5908AP-1.28V USMD VOUT A2

U13

C357
GND B2

1

1

1.0UF

C358
56PF

20% 6.3V 2 X5R 0201-1

5% 2 6.3V NP0-C0G 01005

XW29 SM
12

PP2V5_CAM0_AF_COMP

1

2

FERR-22-OHM-1A-0.065-OHM
12

L27
0201

THIS XW LINK AT CONNECTOR PIN
2

PP2V5_CAM0_AF

1

C286
1.0UF

1

C350
1.0UF

1

1

20% 6.3V 2 X5R 0201-1

20% 6.3V 2 X5R 0201-1

C373
56PF

5% 6.3V 2 NP0-C0G 01005

A

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

CAM0 CONNECTOR
DRAWING NUMBER

Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

21 OF 23 21 OF 46

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6

5

4

3

2

1

8

7

6

5

4

3

2

1

BATT CONN, TPS, STANDOFFS/SHIELDS/FIDUCIALS
BATTERY CONN
D
THIS ONE ON MLB ---> 516S1022 RCPT 516S1023 PLUG (USED ON BATTERY PCM)

TESTPOINTS

POWER TP
120-OHM-210MA
1 2 01005

SPKAMP OUTPUT TP
SPKAMP_TO_SPEAKER_OUT_CONN_P

RCPT-BATT-N41
11 8 2
22 23 22 15 12 8

J6

FL11

17 15

TP91 1
TP-P6

17

PP5V0_USB_CONN

TP1 1
TP-P6

A

D

A

F-ST-SM 7 1 3 5 SHORT-10L-0.25MM-SM 9 2 1
22

AP_BI_BATTERY_SWI

VBUS
17 15

3 13

C279
56PF
AP_BI_BATTERY_SWI_CONN

1

SPKAMP_TO_SPEAKER_OUT_CONN_N

TP92 1
TP-P6

AP_BI_BATTERY_SWI_CONN
1

4 6

5% 16V NP0-C0G 2 01005

TP2 1
TP-P6

A

A

POWER GROUND

PP_BATT_VCC

PP_BATT_VCC

8 12 15 22 23 23 22 15 12 8

5% 16V NP0-C0G 2 01005

56PF

C23

5% 16V NP0-C0G 2 01005

56PF

C25 1

10 12

XW12
1

C9

1

5% 16V 2 NP0-C0G 01005

56PF

C275
220PF

1

C22

PP_BATT_VCC

TP3 1

10% 10V 2 X7R-CERM 01005

5% 16V 2 NP0-C0G 01005

56PF

TP-P80

A

VBATT

E75 - USB/UART/ID/POWER
17 16

TP11 1
TP-P6

A

VBATT GROUND POWER GROUND

90_TRISTAR_BI_E75_PAIR1_P

TP21 1
TP-P6

A

TP34 1
BATTERY_TO_PMU_SENSE
TP-P90
12

PCB: PLACE XW12 AT BATT CONN, PIN 7

A

17 16

90_TRISTAR_BI_E75_PAIR1_N

TP22 1
TP-P6

A

22 15 12 8 23

PP_BATT_VCC

TP4 1 TP5 1
TP-P6

TP-P55

A

VBATT BATTERY NTC

17 16

90_TRISTAR_BI_E75_PAIR2_P

TP23 1
TP-P6

A

17 12

BATTERY_TO_PMU_NTC

A

C

FIDUCIALS
FD1
0P5SM1P0SQ-NSP
1

SHIELDS
13

SUPER TP
PMU_AMUX_AY

17 16

90_TRISTAR_BI_E75_PAIR2_N

TP24 1
TP-P6

A

C
ACCESSORY ID AND POWER

17

PP_E75_TO_TRISTAR_ACC1_CONN

TP26 1
TP-P6

TP6 1
TP-P6

A

FID

A

1

ANALOG MUX A OUTPUT
17

SH1
SM

PP_E75_TO_TRISTAR_ACC2_CONN

TP27 1
TP-P6

A

FD2
0P5SM1P0SQ-NSP
1

806-4834
13

FID

PMU_AMUX_BY

TP7 1
TP-P6

SHLD-EMI-UPPER-FRONT
1

A

ANALOG MUX B OUTPUT

TP25 1
TP-P6

A

POWER GROUND

FD3
0P5SM1P0SQ-NSP
1

FID

SH2
SM

806-4228

RESET
23 19 16 14 13 12 2

FD4
0P5SM1P0SQ-NSP
1

SHLD-X145-EMI-LOWER-FRONT
RESET_1V8_L
1

FID

TP8 1
TP-P6

TP32 1
H6P & BB RESET
TP-P6

A

A

POWER GROUND

SH3
SM

FD5
0P5SM1P0SQ-NSP
1

806-4832

FID

SHLD-EMI-UPPER-BACK
1

DFU
3

17

E75_TO_PMU_ACC_DETECT_CONN

TP10 1
TP-P6

A

FOR DIAGS

FD6
0P5SM1P0SQ-NSP
1

FID

SH4
SM

FORCE_DFU

1

TP9

806-4230

TP-P6

A

FORCE DFU

B

SHLD-X145-EMI-LOWER-BACK

HEADPHONE MIC
17 9 17

MIC AUDIO
MIC1_TO_CODEC_P

B
MIC1 POSITIVE

TP15 1
TP-P6

A

CODEC_TO_HPHONE_HS3_REF_CONN

TP28 1
TP-P6

A

HEADPHONE MIC NEG
9 8

MIC2_TO_CODEC_P

TP16 1
TP-P6

(ON NORTH END OF SINGLE_BRD, TO MITIGATE COMPASS RETURN CURRENTS)

AC COUPLED SCREW HOLES + STANDOFFS STANDOFFS
STDOFF-2.7OD1.4ID-1.04H-SM-1

A

MIC2 POSITIVE

17

CODEC_TO_HPHONE_HS4_REF_CONN

TP29 1
TP-P6

A

HEADPHONE MIC POS
11 9

MIC3_TO_CODEC_P

TP17 1
TP-P6

A

MIC3 POSITIVE

SCREW HOLES
PGND_SCREW_HOLE1
1

DRIVE MIC WRT NEAREST GROUND TEST POINT

BS1

LCM BACKLIGHT
19

PGND_STANDOFF1
1

1 1

860-1511 LCD_BL_CC2_CONN

C427
100PF

1

C430
56PF

C432
27PF

1

C433
100PF

1

C435
56PF

C437
27PF

TP18 1
TP-P6

A

LCD BACKLIGHT SINK1

5% 16V 2 NP0-C0G 01005

5% 16V 2 NP0-C0G 01005

5% 16V 2 NP0-C0G 01005

5% 16V 2 NP0-C0G 01005

5% 16V 2 NP0-C0G 01005

5% 16V 2 NP0-C0G 01005
19

LCD_BL_CC1_CONN

TP19 1
TP-P6

A
PGND_STANDOFF2
1 1 1

A

LCD BACKLIGHT SINK2
SYNC_MASTER=N/A SYNC_DATE=N/A
PAGE TITLE

STDOFF-2.7OD1.4ID-1.04H-SM-1
19

BS2

A

LCD_BL_CA_CONN

TP20 1
TP-P6

860-1511

A

LCD BACKLIGHT SOURCE

BATT B2B, TPS, PD FEATURES
DRAWING NUMBER

C434
100PF

1

C436
56PF

C438
27PF
R

Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

051-9584 2.0.0

SIZE

D

5% 16V 2 NP0-C0G 01005

5% 16V 2 NP0-C0G 01005

5% 16V 2 NP0-C0G 01005

REVISION BRANCH PAGE

22 OF 23 22 OF 46

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6

5

4

3

2

1

RADIO_MLB HIERARCHICAL SYMBOL
AP/RADIO INTERFACE

D

RF I612
25 22 15 12 8 46 14 13 12 10 46 16 14 13 12 10 4 3 26 17

IN IN IN OUT IN OUT IN IN OUT IN OUT BI BI IN
25 3 25 3

PP_BATT_VCC PP_VCC_MAIN PP1V8_SDRAM PP_LDO14_2P65 AP_TO_RADIO_ON_L BB_TO_AP_RESET_DET_L PMU_TO_BB_RST_L AP_TO_BB_RST_L RESET_1V8_L 45_PMU_TO_WLAN_CLK32K BB_TO_LEDDRV_GSM_BLANK 90_TRISTAR_BI_BB_USB_N 90_TRISTAR_BI_BB_USB_P PMU_TO_BB_VBUS_DET
IN OUT IN OUT OUT OUT IN IN OUT IN

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

PP_BATT_VCC_CONN PP_VCC_MAIN_WLAN PP_WL_BT_VDDIO_AP PP_LDO14_2V65 RADIO_ON_L RESET_DET_L RESET_PMU_L BB_RST_L RF_RESET_L CLK32K_AP TX_GTR_THRESH 90_BB_USB_D_N 90_BB_USB_D_P BB_USB_VBUS BB_UART_CTS_L BB_UART_RTS_L BB_UART_RXD BB_UART_TXD HOST_WAKE_BB PP_SYNC BB_I2S_CLK RADIO_MLB BB_I2S_RXD BB_I2S_TXD BB_I2S_WS BB_JTAG_TCK BB_JTAG_TDI BB_JTAG_TMS BB_JTAG_TRST_L BB_JTAG_TDO
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

D
AP_TO_BB_JTAG_TCK AP_TO_BB_JTAG_TDI AP_TO_BB_JTAG_TMS AP_TO_BB_JTAG_TRST_L BB_TO_AP_JTAG_TDO
BI BI BI BI BI
3 25 3 25 3 25 3 25 3 25

25 3 25 3 25 13

25 3 25 22 19 16 14 13 12 2

25 13

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

29 15

25 16 25 16 25 13

25 16 3 25 16 3 25 13 29 3 25 3

AP_TO_BB_UART1_RTS_L BB_TO_AP_UART1_CTS_L AP_TO_BB_UART1_TXD BB_TO_AP_UART1_RXD BB_TO_PMU_HOST_WAKE BB_TO_AP_PP_SYNC 45_AP_TO_BB_I2S1_BCLK AP_TO_BB_I2S1_DOUT BB_TO_AP_I2S1_DIN AP_TO_BB_I2S1_LRCLK

C

25 3 25 3 25 3

C

25 13 25 13 25 13 25 13

OUT OUT OUT OUT

RADIO_TO_PMU_ADC_SMPS1_MSMC_1V05 RADIO_TO_PMU_ADC_SMPS3_MSME_1V8 RADIO_TO_PMU_ADC_LDO6_RUIM_1V8 RADIO_TO_PMU_ADC_LVS1

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

ADC_SMPS1_MSMC_1V05 ADC_SMPS3_MSME_1V8 ADC_LDO6_RUIM_1V8 ADC_LVS1

25 13 46 3 46 3 46 13

IN IN OUT OUT

PMU_TO_WLAN_REG_ON AP_TO_WLAN_UART4_TXD WLAN_TO_AP_UART4_RXD WLAN_TO_PMU_HOST_WAKE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

WLAN_REG_ON WLAN_UART_RXD WLAN_UART_TXD HOST_WAKE_WLAN

25 13 46 3 46 3 25 3 25 3

IN IN OUT IN OUT

PMU_TO_BT_REG_ON AP_TO_BT_UART3_RTS_L BT_TO_AP_UART3_CTS_L AP_TO_BT_UART3_TXD BT_TO_AP_UART3_RXD

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

BT_REG_ON BT_UART_CTS_L BT_UART_RTS_L BT_UART_RXD BT_UART_TXD BT_WAKE HOST_WAKE_BT BT_PCM_CLK BT_PCM_IN BT_PCM_OUT BT_PCM_SYNC

25 3 46 13

IN OUT BI BI BI BI

AP_TO_BT_WAKE BT_TO_PMU_HOST_WAKE 45_AP_TO_BT_I2S3_BCLK AP_TO_BT_I2S3_DOUT BT_TO_AP_I2S3_DIN AP_TO_BT_I2S3_LRCLK

46 3 46 3 46 3

B

46 3

B

25 2 25 2 25 3 25 3 29 3 29 3

50_AP_BI_BB_HSIC1_DATA 50_AP_BI_BB_HSIC1_STB BI AP_TO_BB_HSIC1_RDY IN BB_TO_AP_HSIC1_RDY OUT BB_TO_AP_HSIC1_REMOTE_WAKE BI AP_TO_BB_WAKE_MODEM IN
BI BI BI OUT OUT BI OUT OUT

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

50_HSIC_BB_DATA 50_HSIC_BB_STROBE AP_HSIC1_RDY PBL_RUN_BB_HSIC1_RDY BB_HSIC1_REMOTE_WAKE AP_WAKE_MODEM 50_HSIC_WLAN_DATA 50_HSIC_WLAN_STROBE AP_HSIC3_RDY WLAN_HSIC3_DEVICE_RDY WLAN_HSIC3_RESUME LAT_SW1_CTL LAT_SW2_CTL BB_SPI_TO_PAC_CS BB_SPI_TO_PAC_CLK BB_SPI_TO_PAC_DATA_MOSI PAC_TO_BB_SPI_DATA_MISO BB_IPC_GPIO OSCAR_CONTEXT_A OSCAR_CONTEXT_B

25 2 25 2 25 3 25 3 25 3

50_AP_BI_WLAN_HSIC3_DATA 50_AP_BI_WLAN_HSIC3_STB AP_TO_WLAN_HSIC2_RDY WLAN_TO_AP_HSIC2_RDY WLAN_TO_AP_HSIC2_REMOTE_WAKE BB_TO_LAT_SW1_CTL BB_TO_LAT_SW2_CTL

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

25 17 29 17

MAKE_BASE=TRUE MAKE_BASE=TRUE

29 8 29 8 29 8 29

<OUT> BB_TO_LAT_SW3_CTL BB_TO_ANTENNA_PAC_SPI_CS_L OUT BB_TO_ANTENNA_PAC_SPI_SCLK OUT BB_TO_ANTENNA_PAC_SPI_MOSI OUT ANTENNA_PAC_TO_BB_SPI_MISO IN
BI

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

29 3

BB_TO_AP_IPC_GPIO

A
BB_I2S2_CLK BB_I2S2_WS BB_I2S2_RXD BB_I2S_MCLK

SYNC_MASTER=N/A
PAGE TITLE

SYNC_DATE=N/A

A

RADIO_MLB HIERARCH. SYMBOL
DRAWING NUMBER

Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

23 OF 23 23 OF 46

SHEET

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2
REV
2

1
ECN
0001669557

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

DESCRIPTION OF REVISION
ENGINEERING RELEASED

CK APPD DATE
2012-10-14

D

X155 RADIO_MLB SUBDESIGN - PROTO1 10/3/2012
PDF PAGE
TABLE_TABLEOFCONTENTS_HEAD

D

CONTENTS AP INTERFACE & DEBUG CONNECTORS CELLULAR PMU: (1 OF 2) CELLULAR PMU: (2 OF 2) CELLULAR BASEBAND: (1 OF 2) CELLULAR BASEBAND: (2 OF 2) CELLULAR RF TRANSCEIVER: (1 OF 2) CELLULAR RF TRANSCEIVER: (2 OF 2) CELLULAR FRONT END: TX AND RX MATCHING CELLULAR FRONT END: SAW BANKS CELLULAR FRONT END: BAND 1/4 PAT CELLULAR FRONT END: BAND 2/3 PAD CELLULAR FRONT END: BAND 20 PAD CELLULAR FRONT END: BAND 5/8 PAD CELLULAR FRONT END: BAND 13/17 PAD CELLULAR FRONT END: PA DCDC CONVERTER CELLULAR FRONT END: 2G FEM CELLULAR FRONT END: RX DIVERSITY CELLULAR FRONT END: GPS LNA CELLULAR FRONT END: ANTENNA FEEDS FRONT END LOGIC TABLE (1 OF 2) FRONT END LOGIC TABLE (2 OF 2) WIFI/BT: MODULE AND FRONT END

2
TABLE_TABLEOFCONTENTS_ITEM

3
TABLE_TABLEOFCONTENTS_ITEM

4
TABLE_TABLEOFCONTENTS_ITEM

5
TABLE_TABLEOFCONTENTS_ITEM

6
TABLE_TABLEOFCONTENTS_ITEM

7
TABLE_TABLEOFCONTENTS_ITEM

8
TABLE_TABLEOFCONTENTS_ITEM

C

9
TABLE_TABLEOFCONTENTS_ITEM

BOARD_ID BOM OPTIONS
TABLE_5_HEAD

10
TABLE_TABLEOFCONTENTS_ITEM

PART# 118S0621 118S0732 117S0159 118S0626 118S0626 118S0726 118S0626 118S0623 118S0659 118S0626 118S0689 118S0626 118S0626 118S0650 118S0732 118S0621

QTY 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

DESCRIPTION 1.00M 1% 01005 50K 1% 01005 470K 5% 01005 100K 1% 01005 100K 1% 01005 162K 1% 01005 100K 1% 01005 267K 1% 01005 255K 1% 01005 100K 1% 01005 147K 1% 01005 100K 1% 01005 100K 1% 01005 499K 1% 01005 50K 1% 01005 1.00M 1% 01005

REFERENCE DESIGNATOR(S) R25_RF R26_RF R25_RF R26_RF R25_RF R26_RF R25_RF R26_RF R25_RF R26_RF R25_RF R26_RF R25_RF R26_RF R25_RF R26_RF

CRITICAL Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y

BOM OPTION
TABLE_5_ITEM

C

N51_CFG_A
TABLE_5_ITEM

11
TABLE_TABLEOFCONTENTS_ITEM

N51_CFG_A
TABLE_5_ITEM

12
TABLE_TABLEOFCONTENTS_ITEM

N51_CFG_B
TABLE_5_ITEM

N51_CFG_B
TABLE_5_ITEM

13
TABLE_TABLEOFCONTENTS_ITEM

N53_CFG_A
TABLE_5_ITEM

N53_CFG_A
TABLE_5_ITEM

14
TABLE_TABLEOFCONTENTS_ITEM

N53_CFG_B
TABLE_5_ITEM

15
TABLE_TABLEOFCONTENTS_ITEM

N53_CFG_B
TABLE_5_ITEM

N48_CFG_A
TABLE_5_ITEM

16
TABLE_TABLEOFCONTENTS_ITEM

N48_CFG_A
TABLE_5_ITEM

N48_CFG_B
TABLE_5_ITEM

17
TABLE_TABLEOFCONTENTS_ITEM

N48_CFG_B
TABLE_5_ITEM

18
TABLE_TABLEOFCONTENTS_ITEM

N49_CFG_A
TABLE_5_ITEM

N49_CFG_A
TABLE_5_ITEM

19
TABLE_TABLEOFCONTENTS_ITEM

N49_CFG_B
TABLE_5_ITEM

N49_CFG_B

B

20
TABLE_TABLEOFCONTENTS_ITEM

B

21
TABLE_TABLEOFCONTENTS_ITEM

22
TABLE_TABLEOFCONTENTS_ITEM

23
TABLE_TABLEOFCONTENTS_ITEM

A

SCH :951-2446 BOM :939-0308 BOARD :920-2148
PART# 951-2446 825-2029 QTY 1 1 DESCRIPTION X145_RADIO_MLB EEE FOR 939-0308 REFERENCE DESIGNATOR(S) SCH EEEE_???? CRITICAL Y BOM OPTION Y NA

DRAWING TITLE

A
DRAWING NUMBER

X155 RADIO_MLB SCHEMATIC
Apple Inc. 051-9584 2.0.0
SIZE

TABLE_5_HEAD

D

TABLE_5_ITEM

REVISION BRANCH PAGE SHEET

R
TABLE_5_ITEM

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

1 OF 23 24 OF 46

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

AP INTERFACE & DEBUG CONNECTORS
DEBUG CONNECTOR AP CONNECTIONS PROBE POINTS
PP1_RF
OUT OUT OUT IN OUT IN IN OUT OUT OUT OUT OUT IN IO IO OUT OUT IN OUT IN IN IO IO IN IN OUT IN OUT IN IN IN OUT IN OUT OUT IN IO IO OUT IN OUT IN OUT IN IN IO IO IO IO OUT OUT
27 28 2523 2523

PP_BATT_VCC_CONN

D

IN = FROM AP OUT = TO AP
17 16 15 14 13 12 11 3 2

IN

232526 34 35 36 37 38 39

40

C

PP_BATT_VCC_CONN PP_VCC_MAIN_WLAN 6 TX_GTR_THRESH 4 2 BB_RST_L 6 2 RESET_DET_L 4 2 RADIO_ON_L 4 2 RESET_PMU_L 6 2 HOST_WAKE_BB 2 RF_RESET_L 6 2 PBL_RUN_BB_HSIC1_RDY 23 2 WLAN_HSIC3_RESUME 6 AP_WAKE_MODEM 6 2 AP_HSIC1_RDY 5 2 50_HSIC_BB_DATA 5 2 50_HSIC_BB_STROBE 6 BB_HSIC1_REMOTE_WAKE 6 2 BB_UART_TXD 6 2 BB_UART_RXD 6 2 BB_UART_RTS_L 6 2 BB_UART_CTS_L 5 2 BB_USB_VBUS 5 2 90_BB_USB_D_P 5 2 90_BB_USB_D_N 6 2 BB_I2S_CLK 6 2 BB_I2S_WS 6 2 BB_I2S_TXD 6 2 BB_I2S_RXD 6 PP_SYNC 23 PP_WL_BT_VDDIO_AP 23 2 CLK32K_AP 23 2 WLAN_REG_ON 23 WLAN_UART_TXD 23 WLAN_UART_RXD 23 HOST_WAKE_WLAN 23 2 WLAN_HSIC3_DEVICE_RDY 23 2 AP_HSIC3_RDY 23 2 50_HSIC_WLAN_DATA 23 2 50_HSIC_WLAN_STROBE 23 HOST_WAKE_BT 23 2 BT_WAKE 23 2 BT_UART_TXD 23 2 BT_UART_RXD 23 BT_UART_RTS_L 23 BT_UART_CTS_L 23 2 BT_REG_ON 23 BT_PCM_CLK 23 BT_PCM_SYNC 23 BT_PCM_OUT 23 BT_PCM_IN 6 2 LAT_SW1_CTL 6 LAT_SW2_CTL
23 20 6 20 6 20 20

P4MM SM 1 BB_ERROR_FLAG
PP

6

PP2_RF
PP

P4MM SM 1 SLEEP_CLK_32K P4MM SM 1 PMIC_SSBI
PP

J1_RF AXE654124
56 M-ST-SM 55 1 3 5 7 9 11 13 15 17 19 NC 21 NC 23 25 NC 27 29 31 33 35 NC 37 39 41 43 45 47 49 51 GPIO54/BOOT_CONFIG_0 53 GPIO48/BOOT_CONFIG_6 57

NOSTUFF

D

4 5

PP3_RF

4 5

OUT OUT OUT OUT BI BI OUT OUT OUT IN OUT OUT OUT OUT IN OUT IN OUT IN OUT OUT

P4MM-NSM SM 1 19P2M_MDM
PP

PP10_RF

27

DEBUG_RST_L RESET_PMU_L RADIO_ON_L BB_USB_VBUS 90_BB_USB_D_N 90_BB_USB_D_P RF_RESET_L BB_JTAG_TCK BB_JTAG_TMS BB_JTAG_TDO BB_JTAG_TDI BB_JTAG_TRST_L BB_JTAG_RTCLK PS_HOLD_PMIC BB_UART_TXD BB_UART_RXD BB_UART_RTS_L BB_UART_CTS_L GPIO_DEBUG_LED GPIO_51 2G_FEM_S4

4 5 28 28 28 2 23 25 28 28 2 23 28 28 28 2 23 28 2523 2523 2523 23 2523 2523 2523 2523 2523

PP11_RF
PP

P4MM SM 1 CLK32K_AP P4MM SM 1 AP_HSIC3_RDY
PP

PP14_RF

PP15_RF
PP

P4MM SM 1 WLAN_HSIC3_DEVICE_RDY P4MM SM 1 WLAN_HSIC3_RESUME
PP

PP18_RF

27 2 23 29 29 29 6 7 29 2523 29 29 6 7 41 40 29 2523 2523 2523

P4MM-NSM SM 1 WTR_SSBI_TX_GPS
PP

PP19_RF

P4MM-NSM SM 1 WTR_SSBI_PRX_DRX
PP

PP20_RF

GPIO51/BOOT_CONFIG_3 GPIO53/BOOT_CONFIG_1

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 58

PP_SMPS3_MSME_1V8 BT_WAKE PP_LDO6_RUIM_1V8 WLAN_REG_ON

IN OUT IN OUT

252628 2931 2325 46

252628 2325 46

PMIC_RESOUT_L

IN

2728

AP_HSIC1_RDY BT_REG_ON HOST_WAKE_BB RESET_DET_L SIMCRD_CLK_CONN SIMCRD_IO_CONN SIM_TRAY_DETECT BB_RST_L SIMCRD_RST_CONN PBL_RUN_BB_HSIC1_RDY 2G_FEM_S1 LAT_SW1_CTL

IN IN IN IN IN BI OUT OUT IN IN OUT OUT

2325 2325 2325

29 46 29

2325 2529 2529 2529 2325 2529 2325 2940 2325

29

C
27 29 29

PP21_RF
PP

P4MM SM 1 WTR_RX_ON P4MM SM 1 WTR_RF_ON
PP

6 7

PP22_RF

6 7

GPIO/BOOT_CONFIG CONFIGURATION

PP40_RF
PP

P4MM SM 1 WLAN_COEX_TXD P4MM SM 1 LTE_COEX_TXD
PP

23

BOOT OPTIONS BOOT_DEFAULT_OPTION

BOOT_CONFIG SW REGISTER VALUE 0X00 0X01 0X02 0X03 0X08

6

5

4

3

2

1

0

47 48 49 50 X X X X X 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0

51 52 53 54 55 0 0 0 0 1 0 0 0 0 0 0 0 1 1 X 0 1 0 1 X X X X X X

PP41_RF

6 23

BOOT_NAND_OPTION BOOT_HSIC_OPTION

PP42_RF
PP

P4MM SM 1 50_HSIC_BB_STROBE P4MM SM 1 50_HSIC_BB_DATA
PP

2 5

BOOT_USB_OPTION ENABLE SAHARA PROTOCOL

PP43_RF

2 5

PP44_RF
PP

B

P4MM SM 1 50_HSIC_WLAN_STROBE P4MM SM 1 50_HSIC_WLAN_DATA
PP

PP4_RF
2 23

P4MM SM 1 BB_I2S_CLK
PP

MM4829-2702
2 6

J2_RF

F-ST-SM

20 18 17 10 5 5 5 5 5

23 23

BB_SPI_TO_PAC_CS BB_SPI_TO_PAC_DATA_MOSI 6 BB_SPI_TO_PAC_CLK 6 PAC_TO_BB_SPI_DATA_MISO 3 PP_LDO14_2V65 2 BB_JTAG_TCK 2 BB_JTAG_TDI 2 BB_JTAG_TMS 2 BB_JTAG_TRST_L 2 BB_JTAG_TDO 2 ADC_SMPS1_MSMC_1V05 2 ADC_SMPS3_MSME_1V8 2 ADC_LDO6_RUIM_1V8 2 ADC_LVS1 6 BB_IPC_GPIO 6 OSCAR_CONTEXT_A 6 OSCAR_CONTEXT_B

OUT OUT OUT IN OUT IN IN IN IN OUT

PP45_RF

PP5_RF
2 23

NOSTUFF

1

50_HSIC_BB_DATA

2 5

B

2

3

PP46_RF
PP

P4MM SM 1 BT_UART_TXD P4MM SM 1 BT_UART_RXD
PP

PP6_RF
2 23

P4MM SM 1 BB_I2S_RXD
PP

2 6

PP47_RF

PP7_RF
2 23

P4MM SM 1 BB_I2S_TXD
PP

MM4829-2702
F-ST-SM
2 6

J3_RF

NOSTUFF

4

P4MM SM 1 BB_I2S_WS
PP

2 6

1

50_HSIC_BB_STROBE

2 5

2

3

OUT OUT OUT OUT IN IN

SIM CARD CONNECTOR
BB_I2S2_CLK BB_I2S2_WS 6 BB_I2S_MCLK 6 BB_I2S2_RXD
6 6

OUT OUT OUT IN
5 3 2

PP_LDO6_RUIM_1V8
1

R3_RF

1

A
5 3

VCC SIMCRD_RST_CONN SIMCRD_CLK_CONN 2 RST SIM-CARD-N48 I/O 7 F-ST-SM 3 CLK GND 8 9 10 11 13 5 DETECT 12 SWP 6

J11_RF

1% 1/32W MF 2 01005

15.00K

SIM CARD ESD PROTECTION
PAGE TITLE BI OUT
25 29

4

OUT

A
DRAWING NUMBER

PP_SMPS1_MSMC_1V05

SHORT-10L-0.1MM-SM ADC_SMPS1_MSMC_1V05 1 2 SHORT-10L-0.1MM-SM ADC_SMPS3_MSME_1V8 1 2 SHORT-10L-0.1MM-SM ADC_LDO6_RUIM_1V8 1 2 SHORT-10L-0.1MM-SM ADC_LVS1 1 2

XW12_RF XW13_RF XW14_RF XW15_RF

2925

IN IN

SIMCRD_IO_CONN SIM_TRAY_DETECT
1

U5_RF TPD4E101DPWR
SON4 PP_LDO6_RUIM_1V8
1
2 3 5 6 2

AP INTERFACE & DEBUG CONNECTORS
SIM_TRAY_DETECT
2 6 R

2

2925

2529

SIMCRD_IO_CONN

1

4

Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE SHEET

8 6 5 3 2

PP_SMPS3_MSME_1V8

2

C177_RF

5 3 2

PP_LDO6_RUIM_1V8 PP_LVS1

2

5% 6.3V 2 CERM 01005

100PF

C1_RF

12V-33PF 01005-1
6 2

5 GND

2

SIMCRD_RST_CONN

2

3

SIMCRD_CLK_CONN

2 6

2 OF 23 25 OF 46

5 3

2

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

PMU (1 OF 2)
PP_LVS1 PP_VREG
OUT
2528

INTERNAL USE ONLY

D
2.2UH-20%-1.2A-0.15OHM
1 0806 2

1

C12_RF

L1_RF

20% 6.3V 2 X5R 0201-1

1.0UF

D
OUT
2528

PP_SMPS1_MSMC_1V05
1

C55_RF

20% 6.3V 2 X5R-CERM-1 603

22UF

2.2UH-20%-1.2A-0.15OHM
1 0806 2 1

L4_RF

S1_GND 3

4

PP_SMPS2_RF1_1V3 C56_RF

OUT

2831

20% 6.3V 2 X5R-CERM-1 603

22UF

REF_BYP
1

C50_RF

PM8018-0
BGA VREG (SYM 5 OF 5) 28 REF_BYP 34 REF_GND VOUT_LVS1 53 VREG_RFCLK 13 104 VDD_S1 VSW_S1 92 97 79 90 102 83 42 48 100 12 81 87 105 82 88 76

U2_RF

2.2UH-20%-1.2A-0.15OHM
1 0806 1 2

L2_RF

S2_GND

3 4

PP_SMPS3_MSME_1V8 C57_RF
1

OUT

2526282931

SHORT-10L-0.1MM-SM 1 2

XW17_RF
NOSTUFF

20% 4V 2 X5R 01005

0.1UF

C60_RF

REF_GND

20% 2 6.3V X5R-CERM 0603-3

22UF

20% 4V 2 X5R 01005
3 4

0.1UF

C

40 39 38 37 36 35 34 25 23

IN

PP_BATT_VCC_CONN
1

PP_VSW_S1

2.2UH-20%-1.2A-0.15OHM
1 2 0806 1

L3_RF

S3_GND

NOSTUFF

C
OUT
2631

C42_RF

1

20% 2 6.3V CERM 0402

10UF

C43_RF

1

20% 2 6.3V CERM 0402

10UF

C44_RF

1

20% 2 6.3V CERM 0402

10UF

C45_RF

PP_SMPS4_RF2_2V05 C58_RF

5% 2 16V NP0-C0G 01005

56PF

VREG_S1 95 VDD_S2 VSW_S2 VREG_S2 6 18 24 VDD_S3 VSW_S3 VSW_S5_2 VREG_S3 VSW_S4 VREG_S4 89 101
1

PP_VSW_S2

PP_VSW_S3

20% 6.3V 2 X5R-CERM 0603-3

22UF

2.2UH-20%-2.3A-0.115OHM
PP_VSW_S4
1 TFA252010-SM 2

L5_RF

S4_GND

3 4

98 VDD_S4

PP_SMPS5_DSP_1V05
1

OUT

26

PP_VSW_S5

C59_RF

VDD_S5

VSW_S5 VREG_S5

C46_RF

1

20% 10V 2 X5R-CERM 0402
4 3

4.7UF

C47_RF

1

20% 10V 2 X5R-CERM 0402
4 3

4.7UF

C48_RF

1

20% 10V 2 X5R-CERM 0402
4 3

4.7UF

C49_RF

1

20% 10V 2 X5R-CERM 0402
4 3

4.7UF

C51_RF

20% 6.3V 2 X5R-CERM-1 603

22UF

20% 10V 2 X5R-CERM 0402

4.7UF

S5_GND 3
20 31 32 84 11 17 23 29 63 54 77 65 55 43
1

4

S1_GND

4 3

S2_GND

S3_GND

S4_GND

S5_GND

8 VDD_XO 44 VDD_L2_L3 78 VDD_L4 5 VDD_L5_L6_L13_L14

B

3126 3129282625

IN IN IN

PP_SMPS4_RF2_2V05 PP_SMPS3_MSME_1V8 PP_SMPS5_DSP_1V05

26

75 58 70 59

VDD_L7 VDD_L8 VDD_L9 VDD_L10_L11

64 VDD_L12

VREG_XO VREG_L2 VREG_L3 VREG_L4 VREG_L5 VREG_L6 VREG_L13 VREG_L14 VREG_L7 VREG_L8 VREG_L9 VREG_L10 VREG_L11 VREG_L12

PP_LDO1 PP_LDO2_XO_HS_1V8 PP_LDO3_AMUX_1V8 PP_LDO4_VDDA_3V3 PP_LDO5_GPS_LNA_2V5 PP_LDO6_RUIM_1V8 PP_LDO13_VDDPX_2V95 PP_LDO14_2V65 PP_LDO7_DAC_1V8 PP_LDO8_VDDPX_1V2 PP_LDO9_PLL_1V05 PP_LDO10_ADSP_1V05 PP_LDO11_MDSP_FW_1V05 PP_LDO12_MDSP_SW_1V05 C2_RF
1

INTERNAL USE ONLY
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
28 2728 28 42 2528 28 2325 33 40 41 28 28 28 28 28 28 43

B

20% 2 6.3V X5R 0201-1

1.0UF

C3_RF

1

20% 2 6.3V X5R 0201-1

1.0UF

C4_RF

20% 2 6.3V X5R 0201-1

1.0UF

1 C6_RF

1

20% 2 6.3V X5R 0201-1

1.0UF

C8_RF

1

20% 2 6.3V CERM 0402

10UF

C10_RF

1

20% 2 6.3V CERM 0402

10UF

C13_RF

20% 2 6.3V CERM 0402

10UF

1

C52_RF

20% 2 6.3V X5R 0201-1

1.0UF

1

C53_RF

1

20% 6.3V 2 X5R 0201-1

1.0UF

C54_RF

1

20% 6.3V 2 X5R 0201-1

1.0UF

C5_RF

1

20% 6.3V 2 X5R 0201-1

1.0UF

C7_RF

1

20% 6.3V 2 X5R 0201-1

1.0UF

C9_RF

1

20% 6.3V 2 CERM 0402

10UF

C11_RF

20% 6.3V 2 CERM 0402

10UF

A
PAGE TITLE

A
DRAWING NUMBER

CELLULAR PMU: (1 OF 2)
Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE SHEET

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

3 OF 23 26 OF 46

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

PMU (2 OF 2)
282726

IN

PP_LDO3_AMUX_1V8
1 1

D

BOARD_ID 0.7V 0.9V 1.1V 1.3V 1.5V 1.7V

REVISION PROTO1 PROTO2 EVT1 EVT2 DVT PVT

R23_RF

R25_RF

1% 1/32W MF 2 01005

100K

1% 1/32W MF 2 01005

102K

BOARD_ID
1

PA_ID
1

NOSTUFF

PA_ID > 1.00V FOR MAV7 PA_ID < 1.00V FOR MAV8

D

R24_RF

R26_RF

1% 1/32W MF 2 01005

61.9K

1% 1/32W MF 2 01005

15.8K

NOSTUFF

BGA MPP MISC (SYM 4 OF 5) 85 67 66 72 NC NC 73 80 MPP_01 MPP_02 MPP_03 MPP_04 MPP_05 MPP_06

PM8018-0
GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 33 38 50 60 71 49 NC NC NC NC NC NC

U2_RF

28

OUT

VDDPX_BIAS

29

IN

VREF_DAC_BIAS

R21_RF
25 23

IN

BB_RST_L

1

1.00K2
5% 1/32W MF 01005

R20_RF
29

C

IN

PS_HOLD

1

20.0K2

2

PS_HOLD_PMIC

BGA CONTROL (SYM 1 OF 5) 47 PS_HOLD LED_DRV_N 86

PM8018-0

U2_RF

PA THERMISTOR REMOVED TO MATCH N41, AP SECTION NEEDS ITS OWN THERMISTOR PLACED NEAR THE PA’S.

NC

25 25

23 23

5% 1/32W MF 01005 RADIO_ON_L IN IN

C
69 KPD_PWR* 16 PM_RESIN_N NC 62 OPT_1 NC 74 OPT_2 PON_RESET* 4 PMIC_RESOUT_L
OUT OUT OUT
2528

RESET_PMU_L

PM_USR_INT_N 21 PM_USR_IRQ_L PM_MDM_INT_N 14 PM_MDM_IRQ_L

29 29

2825

BI

PMIC_SSBI

68 SSBI

PON_TRIG 41 BAT_ID 35

GND NEEDS TO BE CLEARED UNDER THIS CRYSTAL TO MINIMIZE THERMAL DRIFT

19.200MHZ
2.0X1.6-SM 1 3 4 2 19P2M_XTAL_IN

Y1_RF

19P2M_XTAL_OUT
282726

B

IN

PP_LDO3_AMUX_1V8
1

BGA CLOCKS (SYM 2 OF 5) 1 XTAL_19M_IN 2 XTAL_19M_OUT XO_OUT_A0 19 XO_OUT_D0 25

PM8018-0

U2_RF

19P2M_WTR 19P2M_MDM

OUT OUT

30 2528

PM8018-0
BGA INPUT PWR (SYM 3 OF 5) 91 GND_S1 103 GND_S2 96 30 GND_S3 36 93 GND_S4 99 GND_S5 94 39 51 61 56 46 52 40
3

U2_RF

SHORT-10L-0.25MM-SM 1 2

XW1_RF

R22_RF

NOSTUFF S1_GND
SHORT-10L-0.25MM-SM 1 2

XW2_RF
NOSTUFF

1% 1/32W MF 2 01005

100K

3 XTAL_32K_IN NC 15 XTAL_32K_OUT 45 GND1 27 GND0 10 XO_THERM 22 XOADC_GND

XO_OUT_A1 37 NC XO_OUT_D0_EN 9 19P2M_CLK_EN
IN
28

B
SLEEP_CLK_32K

S2_GND 3 S3_GND
3 3

SHORT-10L-0.25MM-SM 1 2

XW3_RF

SLEEP_CLK 26

XO_THERM_Y1
1

OUT

2528

C127_RF

NOSTUFF S4_GND S5_GND
SHORT-10L-0.25MM-SM 1 2

XW4_RF

10% 6.3V 2 X5R-CERM 01005

1000PF

RSVD 7

3

NOSTUFF
SHORT-10L-0.25MM-SM 1 2

XW16_RF
NOSTUFF

XO_GND
2

NC 57 VCOIN GND

XW10_RF
1

SHORT-10L-0.1MM-SM

A
PAGE TITLE

A
DRAWING NUMBER

CELLULAR PMU: (2 OF 2)
Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE SHEET

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

4 OF 23 27 OF 46

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

BASEBAND (1 OF 2)
282625

IN

PP_SMPS1_MSMC_1V05
1

MDM9615M
1

U1_RF
BGA (6 OF 6) GND

C15_RF

20% 6.3V 2 X5R 0201-1

1.0UF

C18_RF

1

20% 6.3V 2 X5R 0201-1

1.0UF

C20_RF

1

20% 6.3V 2 X5R 0201-1

1.0UF

C23_RF

1

20% 6.3V 2 X5R 0201-1

1.0UF

C26_RF

20% 6.3V 2 X5R 0201-1

1.0UF

D
2826

IN

PP_LDO9_PLL_1V05
1

2826

IN

PP_LDO10_ADSP_1V05
1

2826

C16_RF

1

20% 6.3V 2 X5R 0201-1

1.0UF

C19_RF

1

20% 6.3V 2 X5R 0201-1

1.0UF

C21_RF

1

20% 6.3V 2 X5R 0201-1

1.0UF

C24_RF

20% 6.3V 2 X5R 0201-1

1.0UF

C27_RF

1

IN

PP_LDO11_MDSP_FW_1V05
1

C30_RF

20% 6.3V 2 X5R 0201-1

1.0UF

20% 6.3V 2 X5R 0201-1

1.0UF

C34_RF

1

20% 6.3V 2 X5R 0201-1

1.0UF

C35_RF

1

20% 6.3V 2 X5R 0201-1

1.0UF

C36_RF

20% 6.3V 2 X5R 0201-1

1.0UF

3129 282625

IN

PP_SMPS3_MSME_1V8
1

31292826 25

IN

PP_SMPS3_MSME_1V8
1

2826

IN

PP_LDO12_MDSP_SW_1V05
1

C14_RF

1

20% 2 6.3V X5R 0201-1

1.0UF

C17_RF

20% 2 6.3V X5R 0201-1

1.0UF

C22_RF

1

20% 2 6.3V X5R 0201-1

1.0UF

C25_RF

20% 2 6.3V X5R 0201-1

1.0UF

C28_RF

1

20% 2 6.3V X5R 0201-1

1.0UF

C29_RF

1

20% 2 6.3V X5R 0201-1

1.0UF

C32_RF

20% 2 6.3V X5R 0201-1

1.0UF

MDM9615M
282625

U1_RF
BGA (5 OF 6) PWR

IN IN

PP_SMPS1_MSMC_1V05

C

282625

PP_SMPS1_MSMC_1V05
1

C68_RF

20% 6.3V 2 X5R 0201-1

1.0UF

B

F8 F9 F12 F13 F14 G9 G12 H9 H12 J8 J9 J12 J13 K8 K9 K12 K13 L8 L9 L12 L13 M8 M9 M12 M13 N8 N9 N12 N13 P9 P12 R9 R12 T8 T9 C17 C18 E17 F17 G7 G8 G13 G14 H7 H8 H13 H14 P7 P8 P13 P14 R7 R8 R13 R14 A14 A19 F21 M1 M21

VDD_DDR

AA20 B19 F20 M20 C5 C6 E6 E7 F5 T15 T16 T17 U14 U15 U16 U17 U19 T19 N15 N16 N17 N19 P15 P16 P17 P19

PP_SMPS3_MSME_1V8

IN

25262829 31

PP_LDO10_ADSP_1V05

IN

2628

VDD_ADSP

PP_LDO11_MDSP_FW_1V05

IN

2628

VDD_MDSP_FW VDD_CORE

PP_LDO12_MDSP_SW_1V05

IN

2628

A21 AA1 AA21 B2 B7 B11 B14 B15 C19 F6 F7 F10 F15 F16 F19 G2 G6 G10 G11 G15 G16 G17 G20 H6 H10 H11 H15 H16 J6 J7 J10 J11 J14 J15 K6 K7 K10 K11 K14 K15 K20 L2 L6 L7 L10 L11 L14 L15 M6 M7 M10 M11

GND

GND

M14 M15 M16 M17 M19 N6 N7 N10 N11 N14 P6 P10 P11 R6 R10 R11 R15 R16 R17 R19 T10 T12 T13 T14 U2 V19 F11 J16 K16 L16 T6 T7 T11 U9 U12 W7 W14 Y7 Y11 Y15 Y18 U13 W13

D
U1_RF
BGA (2 OF 6) EBI1_EBI2

MDM9615M
R10_RF
EBI1_CAL C21 EBI1_CAL EBI2_AD_0 EBI2_AD_1 EBI2_AD_2 EBI2_AD_3 EBI2_AD_4 EBI2_AD_5 EBI2_AD_6 EBI2_AD_7 J20 J19 G19 H20 J21 H19 H21 E21 NC NC NC NC NC NC NC NC
1

240

2

NC NC NC NC

D21 E19 D20 D19

EBI2_NAND_CS* EBI2_OE* EBI2_WE* EBI2_BUSY*

1% 1/32W MF 01005

NC NC

C20 EBI2_CLE* E20 EBI2_ALE*

C

GND_ANA

PP_LVS1
1

VDD_MDSP_SW

IN

2526

R6_RF

5% 1/32W MF 2 01005

470K

MDM9615M
2725

U1_RF
BGA (1 OF 6) DIGITAL

B
RESOUT* U20 NC

VDD_QFUSE_PRG B13 VDD_USB_1P8 E12 VDD_USB_3P3 E10 PP_LDO4_VDDA_3V3 VDD_HVPAD_BIAS E16 PP_LDO2_XO_HS_1V8
IN
26

IN

26 25 2725

IN IN IN IN IN IN IN

1 IN 1
27

C71_RF

VDDPX_BIAS

2826

IN

PP_LDO9_PLL_1V05

K17 VDD_PLL1 L17 VDD_PLL2 W12

20% 6.3V 2 X5R 0201-1

1.0UF

PMIC_RESOUT_L DEBUG_RST_L SLEEP_CLK_32K BB_JTAG_TCK BB_JTAG_TDI BB_JTAG_TMS BB_JTAG_TRST_L

Y20 RESIN* Y4 SRST* AA19 SLEEP_CLK Y3 AA2 W4 AA4 TCK TDI TMS TRST*

25 23 25 23 25 23 25 23

PP_LDO9_PLL_1V05 IN PP_LDO3_AMUX_1V8
IN IN

C31_RF

TDO AA3 BB_JTAG_TDO RTCK Y2 BB_JTAG_RTCLK HSIC_CAL A8 HSIC_DATA C7 HSIC_STB B8 50_HSIC_CAL 50_HSIC_BB_DATA 50_HSIC_BB_STROBE

OUT OUT

23 25 25

26 28 26 27

20% 4V 2 X5R 01005

0.1UF

R9_RF
1

240

2

PP_LDO7_DAC_1V8 VDD_A2 U6 VDD_A2 U7 GND AA11 GND AA18 VDD_MEM VDD_A1 W9 VDD_A1 AA7 GND AA15 A15 G1 G21 L1 U1 W19

NOSTUFF

26

W20 MODE_0 NC Y19 MODE_1 NC
IN
2631 2725 27 27 25

BI BI

23 25 23 25

1% 1/32W MF 01005

PP_SMPS2_RF1_1V3
1

IN OUT BI BI BI

19P2M_MDM 19P2M_CLK_EN PMIC_SSBI 90_BB_USB_D_P 90_BB_USB_D_N RREFEXT ID IS NC
25 23

C70_RF

1

20% 6.3V 2 X5R 0201-1

1.0UF

C33_RF

20% 6.3V 2 X5R 0201-1

1.0UF

V20 CXO U21 CXO_EN Y21 SSBI_PMIC C11 E11 A12 C12 B12 C10 USB_HS_DP USB_HS_DM USB_HS_REXT USB_HS_ID USB_HS_SYSCLK USB_HS_VBUS E8 C8 B9 A9 NC NC NC NC

25 25

23 23

DNC

PP_SMPS3_MSME_1V8
1

IN

252628 2931

C69_RF

A
3129 282625

VDD_P3

20% 6.3V 2 X5R 0201-1

1.0UF

IN

BB_USB_VBUS

1 IN

DNC

PP_SMPS3_MSME_1V8

VDD_P1

VDD_P4 VDD_P5 VDD_P6 VDD_P7

A2 PP_LDO6_RUIM_1V8 A3 PP_SMPS3_MSME_1V8 A7 PP_LDO8_VDDPX_1V2 A11 PP_SMPS3_MSME_1V8

R7_RF

IN IN IN IN

2526 252628 2931 26 252628 2931

1% 1/32W MF 2 01005

200

E9 C9 B10 A10

NC NC NC NC

CELLULAR BASEBAND: (1 OF 2)
DRAWING NUMBER

PAGE TITLE

A
Apple Inc.
R

SDC1_CMD K19 NC SDC1_CLK L21 NC SDC1_DATA0 SDC1_DATA1 SDC1_DATA2 SDC1_DATA3 L19 L20 N20 N21 NC NC NC NC

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE SHEET

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

26

IN

PP_LDO13_VDDPX_2V95

K21 VDD_P2

5 OF 23 28 OF 46

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

BASEBAND (2 OF 2)
D D

MDM9615M
BGA (4 OF 6) ANALOG DAC0_VREF W5
1
30 30 30 30

U1_RF

VREF_DAC_BIAS

OUT

27

IN IN IN IN IN IN IN IN

PRX_BB_I_P PRX_BB_I_N PRX_BB_Q_P PRX_BB_Q_N DRX_BB_I_P DRX_BB_I_N DRX_BB_Q_P DRX_BB_Q_N NC NC NC NC

U8 W8 Y8 AA8 Y10 AA10 Y9 AA9 W17 W18 W15 W16

C62_RF

BBRX_IP_CH0 BBRX_IM_CH0 BBRX_QP_CH0 BBRX_QM_CH0 BBRX_IP_CH1 BBRX_IM_CH1 BBRX_QP_CH1 BBRX_QM_CH1 BBRX_IP_CH2 BBRX_IM_CH2 BBRX_QP_CH2 BBRX_QM_CH2

TX_DAC1_QP Y13 NC TX_DAC1_QM AA13 NC TX_DAC0_IP TX_DAC0_IM TX_DAC0_QP TX_DAC0_QM TX_DAC0_IREF Y6 AA6 Y5 AA5 W6

20% 2 4V X5R 01005

0.1UF

8 6 5 3 2

PP_SMPS3_MSME_1V8
1

R4_RF

30 30 30 30

TX_BB_I_P TX_BB_I_N TX_BB_Q_P TX_BB_Q_N WTR_BB_TX_DAC_IREF

BI OUT OUT OUT OUT

30 30 30 30 30 25

1% 1/32W MF 2 01005 IN

100K

25 OUT 25 OUT 25

C

TX_DAC1_IP Y14 NC TX_DAC1_IM AA14 NC

BI

43 43 43 43

25 23 OUT 25 23 OUT 25 23 OUT 25 23 OUT 29 OUT 29 OUT 29

H17 J17
30 30 30 30

NC NC NC NC NC NC NC NC NC NC

IN IN IN IN

GPS_BB_I_P GPS_BB_I_N GPS_BB_Q_P GPS_BB_Q_N

W10 U10 W11 U11

GNSS_BB_IP GNSS_BB_IM GNSS_BB_QP GNSS_BB_QM

DNC

V21 W21 Y12 Y16 Y17 AA12 AA16 AA17

IN

29 OUT 25 23 OUT

25 23 25

IN IN IN IN BI BI

23 OUT

25 23

46 25 25 23

25 OUT 25 25 25 25 23

23 OUT 23

23 OUT 25 OUT 25 OUT 25 OUT 25

IN

B
70-OHM-300MA
3129282625

FL4_RF
01005-1

35 34

OUT OUT OUT OUT OUT OUT

IN

PP_SMPS3_MSME_1V8

1

2

PP_SPI_NOR_1V8
37

1

C61_RF

20% 4V 2 X5R 01005

0.1UF

36 38 38 37 35 34

3025 OUT 3025 OUT

B6 A6 A5 B5 C4 B3 B4 A4 A16 A13 E14 E13 C14 C13 E15 A18 NC C15 B16 OSCAR_CONTEXT_A B18 AP_WAKE_MODEM C16 GPIO_DEBUG_LED A17 BB_I2S_CLK B21 BB_I2S_WS B20 BB_I2S_RXD A20 BB_I2S_TXD B17 BB_I2S_MCLK P21 BB_I2S2_CLK R21 BB_I2S2_WS P20 BB_I2S2_RXD NC R20 T20 I2C_SCL T21 I2C_SDA U5 GSM_PA_LB_EN V2 GSM_PA_HB_EN V1 PA_ON_B2_B3 U3 PA_ON_B1_B4 T3 NC T1 PA_ON_B5_B8 T5 PA_ON_B20 R5 PA_ON_B13_B17 R3 PA_BS T2 NC R2 WTR_RX_ON P5 WTR_RF_ON P1 PA_R0 SIM_TRAY_DETECT SIMCRD_RST_CONN SIMCRD_CLK_CONN SIMCRD_IO_CONN BB_SPI_TO_PAC_CLK BB_SPI_TO_PAC_CS PAC_TO_BB_SPI_DATA_MISO BB_SPI_TO_PAC_DATA_MOSI SPI_CLK SPI_CS_L SPI_DATA_MISO SPI_DATA_MOSI BB_UART_RTS_L BB_UART_CTS_L BB_UART_RXD BB_UART_TXD

B2

BGA (3 OF 6) GPIO GPIO_0 GRFC_14 GPIO_44 GPIO_1 GRFC_15 GPIO_45 GPIO_2 GRFC_18,SW GPIO_46 GPIO_3 GRFC_19,SW GPIO_47 GPIO_4 GRFC_20 GPIO_48 GPIO_5 GRFC_21 GPIO_49 GPIO_6 GRFC_22 GPIO_50 GPIO_7 GRFC_23 GPIO_51 GPIO_8 GRFC_24,SW GPIO_52 GPIO_9 GRFC_25,SW GPIO_53 GPIO_10 GRFC_26,SW GPIO_54 GPIO_11 GRFC_27,SW GPIO_55 GPIO_12 GRFC_28,SW GPIO_56 GPIO_13 GRFC_29,SW GPIO_57 GPIO_14 GRFC_30,SW GPIO_58 GPIO_15 GRFC_31 GPIO_59 GPIO_16 GRFC_32 GPIO_60 GPIO_17 GRFC_33 GPIO_61 GPIO_18 GRFC_34 GPIO_62 GPIO_19 GRFC_35,SW GPIO_63 GPIO_20 GRFC_36 GPIO_64 GPIO_21 GRFC_37 GPIO_65 GPIO_22 GRFC_38 GPIO_66 GPIO_23 GRFC_39 GPIO_67 GPIO_24 GPIO_68 GPIO_25 GPIO_69 GPIO_26 GPIO_70 GPIO_27 GPIO_71 GPIO_28 GPIO_72 GPIO_29 GPIO_73 GPIO_30 GPIO_74 GPIO_31 GRFC_0,PA_ON GPIO_75 GPIO_32 GRFC_1,PA_ON GPIO_76 GPIO_33 GRFC_2,PA_ON GPIO_77 GPIO_34 GRFC_3,PA_ON GPIO_78 GPIO_35 GRFC_4,PA_ON GPIO_79 GPIO_36 GRFC_5,PA_ON GPIO_80 GPIO_37 GRFC_6,PA_ON GPIO_81 GPIO_38 GRFC_7,PA_ON GPIO_82 GPIO_39 GRFC_8,PA_ON GPIO_83 GPIO_40 GRFC_9,SW GPIO_84 GPIO_41 GRFC_10 GPIO_85 GPIO_42 GRFC_11 GPIO_86 GPIO_43 GRFC_13 GPIO_87

MDM9615M

U1_RF

P3 R1 N5 N3 P2 M2 N1 N2 M3 L3 M5 L5 K1 K5 K3 K2 J2 J5 J1 J3 H3 H5 G5 H1 H2 F3 F1 G3 V3 W3 W2 W1 Y1 F2 E2 E3 D1 E1 D2 D3 C1 B1 C2 C3

PA_R1

OUT

34 35 36 37 38

NC, SECOND TRANSCEIVER RF_ON CONTROL LAT_SW3_CTL 2G_FEM_S6 OUT BOOT_CONFIG_6 LAT_SW1_CTL OUT TX_GTR_THRESH BOOT_CONFIG_5 OUT BOOT_CONFIG_4 NC, ELNA CONTROL BOOT_CONFIG_3 GPIO_51 IN 2G_FEM_S5 BOOT_CONFIG_2 OUT BOOT_CONFIG_1 2G_FEM_S4 OUT BOOT_CONFIG_0 2G_FEM_S1
OUT OUT OUT OUT OUT OUT OUT

33 40 41 23 25 23 25

C

25 40 41 2540 41 2540 40

2G_FEM_S0 NC 2G_FEM_S2 2G_FEM_S3 LAT_SW2_CTL DCDC_EN DCDC_MODE

33 40 33 40 41 23 25 39 39

NC, APT_BYPASS NC BB_PDM LTE_COEX_RXD LTE_COEX_TXD LTE_ACTIVE BB_HSIC1_REMOTE_WAKE BB_IPC_GPIO WTR_SSBI_PRX_DRX WTR_SSBI_TX_GPS NC BB_ERROR_FLAG WTR_GP_DATA0 GPH WTR_GP_DATA1 GPH

OUT IN OUT OUT OUT BI BI BI OUT OUT OUT IN IN OUT IN OUT OUT OUT OUT OUT OUT

39 29 46 2529 46 46 23 25 23 25 25 30 25 30

25 30 30

B

NC, WTR_GP_DATA2 WLAN_TX_BLANK OSCAR_CONTEXT_B PBL_RUN_BB_HSIC1_RDY AP_HSIC1_RDY PM_MDM_IRQ_L RESET_DET_L PS_HOLD NC PP_SYNC HOST_WAKE_BB PM_USR_IRQ_L

46 25 46 23 25 23 25 27 23 25 27

23 25 23 25 27

VCC

SERIAL-SPI-2MX8-1.8V
WLCSP MX25U1635EBAI-10G
D3
29

U6_RF

WP*/SIO2 SI/SIO0

CS*

B3 C3

SPI_CS_L SPI_DATA_MISO

IN OUT

29

IN IN

SPI_DATA_MOSI SPI_CLK

E2

SO/SIO1

29

29

D2 SCLK C2 NC/SIO3

A4 NC

LTE_WLAN_PRIORITY LTE_FRAME_SYNC

ALIAS ALIAS

LTE_COEX_RXD LTE_COEX_TXD

IN OUT

2946 252946

NC GND E3

F1 NC F4 NC

A

CELLULAR BASEBAND: (2 OF 2)
DRAWING NUMBER

PAGE TITLE

A
Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE SHEET

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

6 OF 23 29 OF 46

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

RF TRANSCEIVER (1 OF 4)
PRX TRANSCEIVER RF AND IQ PORTS TRANSCEIVER PHASE CONTROL, TX RF & IQ PORTS WTR1605
SM
PRX_BB_IP 84 PRX_BB_IM 92 PRX_BB_QP 91 PRX_BB_QM 82 DNC 86 PRX_BB_I_P PRX_BB_I_N PRX_BB_Q_P PRX_BB_Q_N
OUT OUT OUT OUT
29 29 29 29

D
33 33

WTR1605
SM
IN IN IN IN IN IN IN IN IN IN IN IN IN IN

U3_RF

U3_RF

D
TX_LB1 TX_LB2 TX_LB3 TX_LB4 TX_MB1 TX_MB2 TX_MB3 TX_MB4 140 132 141 133 126 119 112 95 50_XCVR_B13_B17_B20_TX 50_XCVR_2G_LB_TX 50_XCVR_B8_TX 50_XCVR_B5_B18_TX 50_XCVR_B2_B25_TX 50_XCVR_2G_HB_TX 50_XCVR_B3_B4_TX 50_XCVR_B1_TX
OUT OUT OUT OUT OUT OUT OUT OUT
33 40 33 33

100_XCVR_B13_B17_B20_PRX_P 100_XCVR_B13_B17_B20_PRX_N 100_XCVR_B8_PRX_N 100_XCVR_B8_PRX_P 100_XCVR_B5_B18_PRX_P 100_XCVR_B5_B18_PRX_N 100_XCVR_B2_B25_PRX_P 100_XCVR_B2_B25_PRX_N 100_XCVR_B3_PRX_P 100_XCVR_B3_PRX_N 100_XCVR_DCS_PCS_PRX_N 100_XCVR_DCS_PCS_PRX_P 100_XCVR_B1_B4_PRX_P 100_XCVR_B1_B4_PRX_N

78 69 61 54 48 43 36 30 23 17 8 16 7 15

PRX_LB1_INP PRX_LB1_INM PRX_LB2_INP PRX_LB2_INM PRX_LB3_INP PRX_LB3_INM PRX_MB1_INP PRX_MB1_INM PRX_MB2_INP PRX_MB2_INM PRX_MB3_INP PRX_MB3_INM PRX_HB_INP PRX_HB_INM

SYM 3 OF 5 PRX

IN IN IN IN IN IN IN

TX_BB_I_P TX_BB_I_N TX_BB_Q_P TX_BB_Q_N WTR_BB_TX_DAC_IREF

130 138 131 139 109

SYM 2 OF 5 TX TX_BB_IP TX_BB_IM TX_BB_QP TX_BB_QM DAC_REF GP_DATA0 GP_DATA1 GP_DATA2 DNC DNC DNC RBIAS VTUNE_PRX RX_ON RF_ON SSBI_TX_GNSS SSBI_PRX_DRX GND XO_IN

32 32

29 29

29 29

32 40 32 32

32 32

NC

29

29 29

32 32

32 32

WTR_GP_DATA0 GPH 105 WTR_GP_DATA1 GPH 121 88 WTR_GP_DATA2, NC 114 NC 96

TX_HB 103NC DNC 93

NC

NC
50_PDET_IN

C248_RF
56PF
1 2

R27_RF
1

33 33

4.75K2
1% 1/32W MF 01005

NC
WTR_RBIAS

90 60

PDET_IN 101

50_PDET_PAD_OUT
1

1

R29_RF 47
5% 1/32W MF 01005

2

50_PDET_PAD_IN

IN

40

32 32

WTR_VTUNE
29 25 29 25 2925

79

5% 16V NP0-C0G 01005

IN IN BI BI

DRX TRANSCEIVER RF AND IQ PORTS

2925

WTR_RX_ON WTR_RF_ON WTR_SSBI_TX_GPS WTR_SSBI_PRX_DRX

45 100 89 80 134

DC-BLOCK NEEDED FOR SELF CAL

1% 1/32W MF 2 01005

R28_RF 130

1

1% 1/32W MF 2 01005

R30_RF 130

C
41 41

WTR1605
IN IN IN IN IN IN IN IN IN IN

U3_RF

7 DB ATTENUATOR

100_XCVR_B8_B20_DRX_P 100_XCVR_B8_B20_DRX_N 100_XCVR_B5_B18_B13_B17_DRX_P 100_XCVR_B5_B18_B13_B17_DRX_N 100_XCVR_B2_B25_B3_DRX_P 100_XCVR_B2_B25_B3_DRX_N 100_XCVR_B1_B4_DRX_P 100_XCVR_B1_B4_DRX_N 100_XCVR_GPS_RX_P 100_XCVR_GPS_RX_N

5 14 4 13 3 12 2 11 10 18

SYM 1 OF 5 DRX_GPS DRX_LB1_INP DRX_LB1_INM DRX_LB2_INP DRX_LB2_INM DRX_MB_INP DRX_MB_INM DRX_HB_INP DRX_HB_INM GNSS_INP GNSS_INM

SM

27

IN

19P2M_WTR

C128_RF 100PF 1 2 19P2M_WTR_IN 5% 16V NP0-C0G 01005

120

C

DRX_BB_IP 63 DRX_BB_IM 72 DRX_BB_QP 50 DRX_BB_QM 57

DRX_BB_I_P DRX_BB_I_N DRX_BB_Q_P DRX_BB_Q_N

OUT OUT OUT OUT

29 29

41 41

29 29

1 C182_RF 10PF 5% 2 16V CERM 01005 NOSTUFF

41 41

41 41

41 41

GNSS_BB_IP 56 GNSS_BB_IM 62 GNSS_BB_QP 70 GNSS_BB_QM 71 GND 1

GPS_BB_I_P GPS_BB_I_N GPS_BB_Q_P GPS_BB_Q_N

OUT OUT OUT OUT

29 29

29 29

TRANSCEIVER GROUND CONNECTIONS

B
46 77 47 68 29 22 27 21 20 33 6 75 38 41 58 74 59 52 39 73 34 64 81 35 142 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

WTR1605
SM
SYM 5 OF 5 GND GND 125 GND 124 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 123 110 102 99 129 94 115 137 122 107 106 135 128 104 113

U3_RF

B

A

GND 19 GND 32 GND 49
PAGE TITLE

A
DRAWING NUMBER

GND 9

CELLULAR RF TRANSCEIVER: (1 OF 2)
Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE SHEET

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

7 OF 23 30 OF 46

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

RF TRANSCEIVER (2 OF 2)
RF1_1V3
R53_RF
5 3

PP_SMPS2_RF1_1V3

1

0

2

STAR ROUTING 8 PP_SMPS2_RF1_1V3_FILT
1

STAR ROUTING
ALIAS

RF1_1V3
PP_RF1_1V3_PRX_PLL
1
8 8

STAR ROUTING

STAR ROUTING
ALIAS

R19_RF
PP_RF1_1V3_GPS_LNA
8 3

RF2_2V05
STAR ROUTING PP_SMPS4_RF2_2V05_FILT
1
ALIAS

PP_SMPS2_RF1_1V3_FILT
1

PP_SMPS4_RF2_2V05

1

0

2

PP_RF2_2V05_DRX_BB

8

D

5% 1/20W MF 201

C72_RF

C73_RF

20% 2 6.3V CERM 0402

10UF

20% 6.3V 2 X5R-CERM 01005

0.1UF

C85_RF

PLACE NEAR U3.66

20% 6.3V 2 X5R-CERM 01005

0.1UF

ALIAS

PP_RF1_1V3_GPS_DIG

8

5% 1/20W MF 201

C88_RF

PLACE NEAR U3.24 AND U3.31 STAR ROUTING

20% 6.3V 2 CERM 0402

10UF

ALIAS

PP_RF2_2V05_TX_DA

8

D

ALIAS

PP_RF1_1V3_SHDR_PLL
1

8

ALIAS

PP_RF1_1V3_GPS_VCO PP_RF1_1V3_GPS_PLL

8

1 C244_RF 100PF 5% 16V 2 NP0-C0G 01005 PLACE NEAR U3.111 STAR ROUTING
ALIAS

C74_RF

1

C86_RF

20% 2 6.3V X5R-CERM 01005

0.1UF

20% 6.3V 2 X5R-CERM 01005

0.1UF

ALIAS

8

PP_RF2_2V05_PRX_BB
8

PLACE NEAR U3.65
8

PLACE NEAR U3.37 AND U3.55
ALIAS

PP_RF2_2V05_TX_BB

8

ALIAS

PP_RF1_1V3_PRX_VCO
1

C75_RF

20% 6.3V 2 X5R-CERM 01005

0.1UF

RF1_1V8
6 5 3 2

STAR ROUTING
ALIAS

PP_RF2_2V05_PRX_VCO
1

8

PP_SMPS3_MSME_1V8

ALIAS

PP_RF1_1V8_DIG
1

C89_RF

8

PLACE NEAR U3.76

C87_RF

ALIAS

PP_RF1_1V3_SHDR_VCO
1

8

20% 6.3V 2 X5R 0201-1

1.0UF

20% 2 6.3V X5R-CERM 01005

0.1UF

PLACE NEAR U3.67
8

PP_RF2_2V05_SHDR_VCO
ALIAS

C76_RF

PLACE NEAR U3.87

20% 2 6.3V X5R-CERM 01005

0.1UF

1

C90_RF

PLACE NEAR U3.40

20% 6.3V 2 X5R-CERM 01005

0.1UF

C

PLACE NEAR U3.51

ALIAS

PP_RF1_1V3_TX_DA
1

8

PP_RF2_2V05_TX_VCO
ALIAS
8

C

C77_RF

20% 6.3V 2 X5R-CERM 01005

0.1UF

1

C91_RF

PLACE NEAR U3.118 NOSTUFF

STAR ROUTING
ALIAS

20% 6.3V 2 X5R-CERM 01005
8

0.1UF

PLACE NEAR U3.136

PP_RF1_1V3_TX_SYNTH
1

ALIAS

PP_RF2_2V05_TX_PLL

8

C78_RF

20% 2 6.3V X5R-CERM 01005

0.1UF

ALIAS

PP_RF2_2V05_XO_FILT
1

8

PLACE NEAR U3.98

C92_RF

ALIAS

PP_RF1_1V3_TX_LO
1

8

20% 6.3V 2 X5R-CERM 01005

0.1UF

C79_RF

PLACE NEAR U3.127

20% 6.3V 2 X5R-CERM 01005

0.1UF

PLACE NEAR U3.116
8

ALIAS

PP_RF1_1V3_TX_UPCONVERTER
1

TRANSCEIVER POWER CONNECTIONS WTR1605
SM
SRM 4 OF 5 PWR PP_RF1_1V3_PRX_FELO1 PP_RF1_1V3_PRX_FELO1 PP_RF1_1V3_PRX_FELO2 PP_RF1_1V3_DRX_LBLO 8
8 8

C80_RF

U3_RF

B
STAR ROUTING

5% 16V 2 NP0-C0G 01005

100PF

B
VDD_RF2_T_DA VDD_RF1_T_DA VDD_RF1_T_UPC VDD_RF1_T_LO VDD_RF2_T_BB VDD_RF2_T_VCO VDD_RF2_XO VDD_RF1_T_SYN VDD_RF2_T_PLL VDD_RF1_G_LNA VDD_RF1_G_VCO VDD_RF1_G_PLL VDD_RF1_G_BB 111 118 117 116 108 136 127 98 97 24 37 55 31 PP_RF2_2V05_TX_DA PP_RF1_1V3_TX_DA PP_RF1_1V3_TX_UPCONVERTER PP_RF1_1V3_TX_LO PP_RF2_2V05_TX_BB PP_RF2_2V05_TX_VCO PP_RF2_2V05_XO_FILT PP_RF1_1V3_TX_SYNTH PP_RF2_2V05_TX_PLL PP_RF1_1V3_GPS_LNA PP_RF1_1V3_GPS_VCO PP_RF1_1V3_GPS_PLL PP_RF1_1V3_GPS_DIG PP_RF1_1V8_DIG
8 8 8 8 8

PLACE NEAR U3.117 STAR ROUTING
ALIAS

8

1

C81_RF

20% 2 6.3V X5R-CERM 01005

0.1UF

ALIAS

PP_RF1_1V3_DRX_FE

8

PP_RF1_1V3_DRX_FE PP_RF1_1V3_DRX_MBLO 8 PP_RF1_1V3_JAM_DET 8
8

PLACE NEAR U3.53 AND U3.26 PP_RF1_1V3_PRX_FELO2

PP_RF2_2V05_PRX_BB 8 PP_RF2_2V05_DRX_BB
8 8

53 42 28 26 25 85 83 44 67 76 66 51 40 65

VDD_RF1_P_FELO VDD_RF1_P_FELO VDD_RF1_D_LBLO VDD_RF1_D_FE VDD_RF1_D_MBLO VDD_RF1_JDET VDD_RF2_P_BB VDD_RF2_D_BB VDD_RF2_P_VCO VDD_RF1_P_VCO VDD_RF1_P_PLL VDD_RF2_S_VCO VDD_RF1_S_VCO VDD_RF1_S_PLL

8 8 8 8

ALIAS

PP_RF2_2V05_PRX_VCO PP_RF1_1V3_PRX_VCO 8
8

1

C82_RF

PP_RF1_1V3_PRX_PLL 8 PP_RF2_2V05_SHDR_VCO 8 PP_RF1_1V3_SHDR_VCO PP_RF1_1V3_SHDR_PLL 8
8

8 8 8 8

20% 2 6.3V X5R-CERM 01005

0.1UF

PLACE NEAR U3.42 STAR ROUTING
ALIAS

VDD_DIO 87 PP_RF1_1V3_DRX_LBLO
8

8

1

C83_RF

A
ALIAS

20% 6.3V 2 X5R-CERM 01005

0.1UF

ALIAS

PP_RF1_1V3_DRX_MBLO

8

PLACE NEAR U3.25 AND U3.28 PP_RF1_1V3_JAM_DET
PAGE TITLE

A
DRAWING NUMBER

8

CELLULAR RF TRANSCEIVER: (2 OF 2)
Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE SHEET

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8 OF 23 31 OF 46

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

TRANSCEIVER TX AND RX MATCHING
TX MATCHING NETWORKS

D

R46_RF
30

IN

50_XCVR_B1_TX

1

0.00 2
0% 1/32W MF 01005

50_B1_TX_SAW_IN

D
OUT
33

R47_RF
30

IN

50_XCVR_B3_B4_TX1

0.00 2
0% 1/32W MF 01005

50_B3_B4_TX_SAW_IN

OUT

33

R48_RF
30

IN

50_XCVR_B2_B25_TX 1

0.00 2
0% 1/32W MF 01005

50_B2_B25_TX_SAW_IN

OUT

33

C

C

RX MATCHING NETWORKS
0.6NH+/-0.1NH-0.85A
34

L47_RF
0201

IN

100_B1_B4_DUPLX_RX_P
1

100_XCVR_B1_B4_PRX_N

OUT

30

C185_RF

0.6PF
1 2

35

IN

50_B2_DUPLX_RX
1

100_XCVR_B2_B25_PRX_N
1

OUT

30

L44_RF
0201

+/-0.1PF 16V NP0-C0G 01005

3.1NH+/-0.1NH-0.45A-025OHM 0.6NH+/-0.1NH-0.85A
1 0201 2

L36_RF
0201DS

8.2NH-5%-0.34A-0.27OHM
C186_RF

L38_RF
0201DS

2
34

L48_RF

6.7NH-5%-0.46A-0.15OHM

IN

100_B1_B4_DUPLX_RX_N

100_XCVR_B1_B4_PRX_P

OUT

30

2

27PF
2

2

50_B2_RX_BALUN 1

100_XCVR_B2_B25_PRX_P

B
1

OUT

30 37

10NH-3%-250MA
IN

L49_RF
0201

C183_RF

5% 16V NP0-C0G 01005

100_B5_B18_DUPLX_RX_N
1

100_XCVR_B5_B18_PRX_N

OUT

30

B

+/-0.1PF 2 16V NP0-C0G 01005

1.1PF

L45_RF
C187_RF
0201

22NH-150MA 10NH-3%-250MA
1 0201 2

0.7PF
1 2

35

IN

50_B3_DUPLX_RX
1

100_XCVR_B3_PRX_N
1

OUT

30 37

2 IN

L50_RF

+/-0.1PF 16V NP0-C0G 01005

100_B5_B18_DUPLX_RX_P

100_XCVR_B5_B18_PRX_P

OUT

30

L37_RF
0201 2

5.1NH-3%-0.35A
C188_RF
2

L39_RF
0201

5.1NH-3%-0.35A
37

10NH-3%-250MA
IN

L51_RF
0201

100_B8_DUPLX_RX_P
1

100_XCVR_B8_PRX_P

OUT

30

27PF
2

50_B3_RX_BALUN 1

100_XCVR_B3_PRX_P

OUT

30

1

C184_RF

5% 16V NP0-C0G 01005 2
37

L46_RF
0201

18NH+/-3%-0.2A-0.8OHM 10NH-3%-250MA
1 0201 2

+/-0.1PF 16V 2 NP0-C0G 01005

1.2PF

L52_RF

IN

100_B8_DUPLX_RX_N

100_XCVR_B8_PRX_N

OUT

30

A
PAGE TITLE DRAWING NUMBER

A
Apple Inc.
R

CELLULAR FRONT END: TX AND RX MATCHING
051-9584 2.0.0
SIZE

D

REVISION BRANCH PAGE SHEET

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

9 OF 23 32 OF 46

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

SAW BANKS
D D

HB TX SAW BANK + B13/B17/B20 DP6T SWITCH AND MATCHING
41 40 29 41 40 29 40 29 43 41 40 26 2523

IN IN IN IN

2G_FEM_S6 2G_FEM_S3 2G_FEM_S2 PP_LDO14_2V65

LB TX SAW BANK
LMTPFJGA-E50
LGA
6 7 8 9 VDD V1 V2 V3
30

FL2_RF

IN IN IN

50_XCVR_B5_B18_TX 50_XCVR_B8_TX 50_XCVR_B13_B17_B20_TX

1 B5/18/BC10_TX_IN 2 B8_TX_IN 3 B13/17/20_TX_IN

50_B5_TX_SAW_OUT B5/18/BC10_TX_OUT 11 B8_TX_OUT 10 50_B8_TX_SAW_OUT B13_TX_OUT 9 50_B13_TX_SAW_OUT B17_TX_OUT 8 50_B17_TX_SAW_OUT GND B20_TX_OUT 7 50_B20_TX_SAW_OUT

OUT OUT OUT OUT OUT

37

C
32

HFQSMXXFA
IN IN IN

U9_RF
LGA

30

37

50_B1_TX_SAW_IN 50_B2_B25_TX_SAW_IN 50_B3_B4_TX_SAW_IN

3 B1TXIN 5 B25_TXIN 4 B3/4_TXIN

50_B1_TX_SAW_OUT BAND1TXOUT 14 50_B2_TX_SAW_OUT B25TXOUT 11 50_B3_TX_SAW_OUT B3TXOUT 12 50_B4_TX_SAW_OUT BAND4TXOUT 13

30

38

C

OUT OUT OUT OUT

34

38

35

32

36

35

34

38 38

IN IN IN IN IN IN

100_B13_DUPLX_RX_N 100_B13_DUPLX_RX_P 100_B17_DUPLX_RX_P 100_B17_DUPLX_RX_N 100_B20_DUPLX_RX_P 100_B20_DUPLX_RX_N

15 16 17 18 19 20

B13_RXIN B13_RXIN B17_RXIN B17_RXIN B20_RXIN B20_RXIN

B13_17_20_RXOUT0 1 100_XCVR_B13_B17_B20_PRX_N OUT B13_17_20_RXOUT1 2 100_XCVR_B13_B17_B20_PRX_P
OUT

30 30

38 38

36 36

GND 10

THRM

PAD

2.5NH+/-0.1NH-500MA
40

L64_RF
0201

DCS/PCS 2-IN-1 RX FILTER
2

21 22

23

4 5 6 12 13

32

1.1NH+/-0.1NH
1 0201 1 2

L54_RF

100_XCVR_DCS_PCS_PRX_P

B

BAND B3 TX B4 TX B13 RX B17 RX B20 RX

S6 HIGH LOW X X X

S3 X X HIGH HIGH LOW

S2 X X HIGH LOW HIGH

IN

50_PCS_RX

1

50_PCS_RX_MATCH

FL6_RF SAWFD1G84BU0F57 FILTER
LGA-1
1 UNBAL_PORT_1960MHZ 4 UNBAL_PORT_1842.5MHZ BAL_PORT_1842.5MHZ/1960MHZ 6 BAL_PORT_1842.5MHZ/1960MHZ 9

OUT

30

100_DCS_PCS_RX_FILTER_P 100_DCS_PCS_RX_FILTER_N
2

2.5NH+/-0.1NH-500MA
40

L65_RF
0201

L53_RF
0201

4.3NH-3%-0.35A 1.1NH+/-0.1NH
1 0201 2

IN

50_DCS_RX

1

2

50_DCS_RX_MATCH GND 2 3 5 7 8 10
1

L55_RF

B
100_XCVR_DCS_PCS_PRX_N
OUT
30

C245_RF 1 C246_RF
1.3PF
+/-0.05PF 25V 2 C0G-CERM 0201

+/-0.05PF 25V 2 C0G-CERM 0201

1.4PF

A
PAGE TITLE DRAWING NUMBER

A
Apple Inc.
R

CELLULAR FRONT END: SAW BANKS
051-9584 2.0.0
SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

10 OF 23 33 OF 46

SHEET

8

7

6

5

4

3

2

1

BAND 1/4 PAT
D

8

7

6

5

4

3

2

1

D

40 39 38 37 36 35 40 39 38 37 36 35 26 2523

IN IN

PP_PA PP_BATT_VCC_CONN
1

PA_ON_B1_B4 PA_BS PA_R1
1 1 1 C165_RF C208_RF 1 1 C237_RF 1 C238_RF C236_RF

IN IN IN

29 2935 37 38 2935 36 37 38

C164_RF

C
C191_RF
56PF
1 2 1
33

20% 2 6.3V X5R-CERM 01005

0.1UF

10% 2 6.3V X5R-CERM 01005

1000PF

20% 2 6.3V X5R 0201-1

1.0UF

C209_RF
27PF

5% 2 25V NP0-C0G 201

5% 16V 2 NP0-C0G 01005

56PF

5% 16V 2 NP0-C0G 01005

56PF

5% 16V 2 NP0-C0G 01005

56PF

C

NOSTUFF
VBATT 29 VEN_B1_B4 24 BS 25
VCC 22

IN

50_B1_TX_SAW_OUT
1

5% 16V C162_RF NP0-C0G 1.2PF 01005 +/-0.1PF 16V 2 NP0-C0G 01005

C258_RF

VMODE 30

NOSTUFF

+/-0.1PF 16V 2 NP0-C0G 01005

1.2PF

NOSTUFF

50_B1_TX_PAD_IN 50_B4_TX_PAD_IN

U14_RF
28 RFIN_B1 26 RFIN_B4 9 RX_P_B1_B4 8 RX_N_B1_B4 LGA

TRIPLEXER-BAND1-4

CPL_IN 4 CPL_OUT 20

1.2NH+/-0.1NH-0.75A
50_B1_B4_DPLX_ANT
1 0201 2

L70_RF

50_B1_B4_ANT

BI

40

C192_RF
56PF
1 2
33

IN

50_B4_TX_SAW_OUT
1

ANT_B1_B4 16 GND THRM_PAD
17 18 19 21 23 27

1

C249_RF
0.5PF

1

C167_RF
27PF
NOSTUFF

C163_RF

+/-0.1PF 2 16V NP0-C0G 01005

1 2 3 5 6 7 10 11 12 13 14 15

NOSTUFF

100_B1_B4_DUPLX_RX_N 100_B1_B4_DUPLX_RX_P

OUT OUT

32 32

31 32 33 34 35 36 37 38 39 40 41 42

1.2PF

5% 16V NP0-C0G 01005

+/-0.05PF 25V 2 COG-CERM 0201

5% 25V 2 NP0-C0G 201

B

B

A

BAND PA POWER MODE PA_BS PA_ON_B1_B4 PA_R1 ============================================================ POWER DOWN X 0 0 0 STANDBY X X 0 X B4 HPM 0 1 0 B4 LPM 0 1 1 B1 HPM 1 1 0 B1 LPM 1 1 1
8 7 6 5 4 3

CELLULAR FRONT END: BAND 1/4 PAT
DRAWING NUMBER

PAGE TITLE

A
Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

11 OF 23 34 OF 46

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SHEET

2

1

BAND 2/3 PAD
D

8

7

6

5

4

3

2

1

D

40 39 38 37 36 34 40 39 38 37 36 34 26 2523

IN IN

PP_PA PP_BATT_VCC_CONN
1

PA_ON_B2_B3
1

IN IN IN

29 2934 37 38

C148_RF

C
C193_RF
56PF
1 2
33

20% 6.3V 2 X5R-CERM 01005

0.1UF

C210_RFC149_RF
1

1

10% 6.3V 2 X5R-CERM 01005

1000PF

20% 6.3V 2 X5R 0201-1

1.0UF

C211_RF
27PF

PA_BS PA_R1

5% 25V 2 NP0-C0G 201

2934 36 37 38

NOSTUFF

C
VEN_B2_B3 30 BS 29 VMODE 24
VCC 2

IN

50_B3_TX_SAW_OUT
1

C146_RF

+/-0.1PF 16V 2 NP0-C0G 01005

1.2PF

5% 16V NP0-C0G 01005

VBATT 25

NOSTUFF

50_B3_TX_PAD_IN 50_B2_TX_PAD_IN

26 RFIN_B3 28 RFIN_B2 13 RX_B3 14 GND 11 RX_B2 10 GND

DUPLEXER-BAND2-3
LGA

U23_RF

CPL_IN 4 CPL_OUT 20

2.4NH+/-0.1NH-0.50A
NC NC
50_B3_DPLX_ANT
1 0201 1 2

L71_RF

50_B3_ANT

BI

40

C194_RF
56PF
1 2 1
33

IN

50_B2_TX_SAW_OUT
1

ANT_B3 16 ANT_B2 8 GND
22 23 27

C250_RF
1.1PF
1

C147_RF

+/-0.1PF 2 16V NP0-C0G 01005

1 3 5 6 7 9 12 15 17 18 19 21

31 32 33 34 35 36 37 38 39 40 41 42

1.2PF

5% 16V NP0-C0G 01005

C259_RF

THRM_PAD

+/-0.1PF 2 25V CERM 0201

C152_RF

NOSTUFF

+/-0.1PF 2 16V NP0-C0G 01005

1.2PF

5% 25V 2 NP0-C0G 0201

27PF

NOSTUFF

NOSTUFF

1.3NH+/-0.1NH-600MA
50_B2_DPLX_ANT 50_B2_DUPLX_RX 50_B3_DUPLX_RX
OUT OUT
32 32

L72_RF
0201

1

2

50_B2_ANT

BI

40

B

1

C251_RF
0.9PF
1

+/-0.05PF 25V 2 C0G-CERM 0201

C153_RF
27PF
NOSTUFF

B

5% 2 25V NP0-C0G 201

A

BAND PA POWER MODE PA_BS PA_ON_B2_B3 PA_R1 ============================================================ POWER DOWN X 0 0 0 STANDBY X X 0 X B3 HPM 0 1 0 B3 LPM 0 1 1 B2 HPM 1 1 0 B2 LPM 1 1 1
8 7 6 5 4 3

CELLULAR FRONT END: BAND 2/3 PAD
DRAWING NUMBER

PAGE TITLE

A
Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

12 OF 23 35 OF 46

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SHEET

2

1

8

7

6

5

4

3

2

1

BAND 20 PAD
D D

40 39 38 37 35 34 40 39 38 37 35 34 26 25 23

IN IN

PP_PA BULK BYPASSING SHARED WITH B1/4 PAT PP_PA PP_BATT_VCC_CONN
1

PA_ON_B20

IN

29

C156_RF

1

C
C195_RF
56PF
1 2 1
33

20% 6.3V 2 X5R-CERM 01005

0.1UF

C233_RF
1000PF

1

C234_RF
27PF
1 5% 16V 2 NP0-C0G 01005

PA_R1
1 C240_RF C239_RF

IN

2934 35 37 38

10% 6.3V 2 X5R-CERM 01005

5% 25V 2 NP0-C0G 201

NOSTUFF

56PF

5% 16V 2 NP0-C0G 01005

56PF

C

VBATT 25

VEN_B20_B7 30 BS 29

IN

50_B20_TX_SAW_OUT
1

C154_RF

+/-0.1PF 16V 2 NP0-C0G 01005

1.2PF

5% 16V NP0-C0G 01005

VMODE 24

VCC 2

C84_RF

NOSTUFF

+/-0.1PF 16V 2 NP0-C0G 01005

1.2PF

NOSTUFF

50_B20_TX_PAD_IN 26 RFIN_B20 28 RFIN_B7 12 RX_P_B20 13 RX_N_B20 11 RX_B7 10 GND

DUPLEXER-BAND7-20
LGA

U207_RF

6.2NH-0.30A
CPL_IN 4 CPL_OUT 20

L73_RF
0201

NC NC

50_B20_DPLX_ANT
1

1

2

50_B20_ANT

BI

40

C39_RF
2.4PF
1

ANT_B20 16 ANT_B7 8 GND
22 23 27

+/-0.1PF 25V 2 NP0-C0G 201

C160_RF

THRM_PAD 31 32 33 34 35 36 37 38 39 40 41 42

1 3 5 6 7 9 14 15 17 18 19 21

+/-0.05PF 25V 2 C0G-CERM 0201

3.6PF

NOSTUFF

B

100_B20_DUPLX_RX_P 100_B20_DUPLX_RX_N

OUT OUT

33

B

33

A

BAND PA POWER MODE PA_ON_B20 PA_R1 ===================================================== POWER DOWN LPM 0 0 STANDBY X 0 X B20 HPM 1 0 B20 LPM 1 1
8 7 6 5 4 3

CELLULAR FRONT END: BAND 20 PAD
DRAWING NUMBER

PAGE TITLE

A
Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

13 OF 23 36 OF 46

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SHEET

2

1

8

7

6

5

4

3

2

1

BAND 5/8 PAD
D D

40 39 38 36 35 34 40 39 38 36 35 34 26 2523

IN IN

PP_PA PP_BATT_VCC_CONN
1

PA_ON_B5_B8 PA_BS
1 1 C119_RF C212_RF 1

IN IN IN

29

C118_RF

C
2.7NH+/-0.1NH-200MA
33

20% 6.3V 2 X5R-CERM 01005

0.1UF

10% 6.3V 2 X5R-CERM 01005

1000PF

20% 6.3V 2 X5R 0201-1

1.0UF

C213_RF
27PF

2934 35 38

PA_R1
1

2934 35 36 38

5% 25V 2 NP0-C0G 201

1 C215_RF 1 C216_RF C214_RF

NOSTUFF

5% 16V 2 NP0-C0G 01005

56PF

5% 16V 2 NP0-C0G 01005

56PF

5% 16V 2 NP0-C0G 01005

56PF

C

VBATT 29

VEN_B5_B8 24 BS 25

IN

50_B5_TX_SAW_OUT
1

1 01005

2 1

VMODE 30

VCC 2

L7_RF

C116_RF

+/-0.1PF 16V 2 NP0-C0G 01005

1.2PF

C256_RF

NOSTUFF

+/-0.1PF 16V 2 NP0-C0G 01005

0.7PF

50_B5_TX_PAD_IN 50_B8_TX_PAD_IN

26 28 13 14 11 10

RFIN_B5 RFIN_B8 RX_P_B5 RX_N_B5 RX_P_B8 RX_N_B8

DUPLEXER-BAND5-8
LGA

U58_RF

6.2NH-0.30A
CPL_IN 4 CPL_OUT 20

L74_RF
0201

NC NC

50_B5_DPLX_ANT

1

2

50_B5_ANT

BI

40

2.2NH+/-0.1NH-200MA
33

L10_RF
01005

IN

50_B8_TX_SAW_OUT
1

1

2 1

ANT_B5 16 ANT_B8 8 GND
22 23 27

1

C252_RF
4.8PF

1

C117_RF

+/-0.1PF 2 16V NP0-C0G 01005

1 3 5 6 7 9 12 15 17 18 19 21

NOSTUFF

31 32 33 34 35 36 37 38 39 40 41 42

1.2PF

C257_RF

THRM_PAD

+/-0.1PF 2 16V NP0-C0G 01005

0.7PF

+/-0.05PF 25V 2 C0G-CERM 0201

C122_RF
27PF
NOSTUFF

5% 25V 2 NP0-C0G 201

4.3NH-3%-0.35A
100_B8_DUPLX_RX_N 50_B8_DPLX_ANT
OUT OUT OUT OUT
32

L75_RF
0201

1

2

50_B8_ANT

BI

40

B

100_B8_DUPLX_RX_P

32

1

100_B5_B18_DUPLX_RX_N 100_B5_B18_DUPLX_RX_P

C253_RF
1.9PF
1

32

32

+/-0.05PF 25V 2 C0G-CERM 0201

C123_RF

B

5% 2 25V NP0-C0G 0201

27PF

NOSTUFF

A

BAND PA POWER MODE PA_BS PA_ON_B5_B8 PA_R1 ============================================================ POWER DOWN X 0 0 0 STANDBY X X 0 X B5 HPM 0 1 0 B5 LPM 0 1 1 B8 HPM 1 1 0 B8 LPM 1 1 1
8 7 6 5 4 3

CELLULAR FRONT END: BAND 5/8 PAD
DRAWING NUMBER

PAGE TITLE

A
Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

14 OF 23 37 OF 46

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SHEET

2

1

8

7

6

5

4

3

2

1

BAND 13/17 PAD
D D

40 39 37 36 35 34 40 39 37 36 35 34 26 2523

IN IN

PP_PA PP_BATT_VCC_CONN
1

PA_ON_B13_B17 PA_BS
1

IN IN IN

29

2934 35 37

C110_RF

C
C198_RF

20% 6.3V 2 X5R-CERM 01005

0.1UF

C217_RF

1

10% 6.3V 2 X5R-CERM 01005

1000PF

C111_RF

1

20% 6.3V 2 X5R 0201-1

1.0UF

C235_RF

5% 25V 2 NP0-C0G 201

27PF

PA_R1

2934 35 36 37

C

NOSTUFF
VBATT 25 VEN_B13_B17 30 BS 29
VCC 22

56PF
1 2

33

IN

50_B13_TX_SAW_OUT

5% 16V NP0-C0G 01005

1

C108_RF

VMODE 24

+/-0.1PF 16V 2 NP0-C0G 01005

1.2PF

L76_RF
CPL_IN 4 CPL_OUT 20

NOSTUFF

50_B13_TX_PAD_IN 26 RFIN_B13 50_B17_TX_PAD_IN 28 RFIN_B17 13 RX_P_B13 14 RX_N_B13 11 RX_P_B17 10 RX_N_B17

U1317_RF

18PF
1 2

50_B13_DPLX_ANT
1

50_B13_LPF_IN

LFL0Q766MTM1D497 2 INPUT OUTPUT 1 GND 3 4

BAND13-50OHM

FL3_RF

50_B13_ANT

DUPLEXER-BAND13-17
LGA

BI

40

C199_RF

C113_RF

56PF
1 2

33

IN

50_B17_TX_SAW_OUT

ANT_B13 16 ANT_B17 8 GND
21 23 27

1 2 3 5 6 7 9 12 15 17 18 19

31 32 33 34 35 36 37 38 39 40 41 42

5% 16V NP0-C0G 01005

+/-0.05PF 25V 2 C0G-CERM 0201

2.2PF

2% 25V C0H-CERM 0201 1

C114_RF

1

C109_RF

THRM_PAD

NOSTUFF

+/-0.1PF 2 16V NP0-C0G 01005

1.2PF

5% 2 25V NP0-C0G 0201

27PF

NOSTUFF

NOSTUFF

6.8NH-3%-140MA
100_B17_DUPLX_RX_N 50_B17_DPLX_ANT
OUT OUT OUT OUT
33

L77_RF

1 01005

2

50_B17_ANT

BI

40

B

100_B17_DUPLX_RX_P 100_B13_DUPLX_RX_N 100_B13_DUPLX_RX_P

1
33

C254_RF

33

+/-0.1PF 16V 2 NP0-C0G 01005-1

2.2PF

B
1

C115_RF

33

5% 2 16V NP0-C0G 01005

56PF

NOSTUFF

A

BAND PA POWER MODE PA_BS PA_ON_B13_B17 PA_R1 ============================================================ POWER DOWN X 0 0 0 STANDBY X X 0 X B17 HPM 0 1 0 B17 LPM 0 1 1 B13 HPM 1 1 0 B13 LPM 1 1 1
8 7 6 5 4 3

CELLULAR FRONT END: BAND 13/17 PAD
DRAWING NUMBER

PAGE TITLE

A
Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

15 OF 23 38 OF 46

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SHEET

2

1

8

7

6

5

4

3

2

1

PA DC/DC CONVERTER
D D

40

38 37 36 35 34 26 25 23

IN

PP_BATT_VCC_CONN

SHORT-10L-0.25MM-SM 1 2

XW47_RF

PP_BATT_VCC_PA_DCDC

C

1

1 C1214_RF 1 C1201_RF C189_RF

1 1

5% 16V 2 NP0-C0G 01005

56PF

10% 6.3V 2 X5R 01005

0.01UF

20% 6.3V 2 CERM 0402

10UF

C169_RF
0.01UF

C1215_RF

C

20% 6.3V 2 X5R 0201-1

1.0UF

10% 6.3V 2 X5R 01005

16

DCDC_PGND IN1 B2 IN2 C2

DCDC_PGND

16

PLACE NEAR U1.H3

PLACE NEAR U11.A2

R33_RF
29

IN

BB_PDM

1

1.00K
1% 1/32W MF 01005

R34_RF
BB_PDM_FILT
1 1

2

1.00K
1% 1/32W MF 01005

2 1

DCDC_ADJ

A2 REFIN B1 EN C1 MODE

C144_RF

A1 AGND

A3 PGND

10% 2 6.3V X5R 01005

6800PF

C145_RF

29

IN IN

DCDC_EN DCDC_MODE

U11_RF MAX77100
WLP

OUT C3
1

2.2UH-20%-1.5A-0.160OHM
LX B3 DCDC_OUT
2 MAKK2016-SM

L21_RF

10% 2 6.3V X5R 01005

4700PF

PP_PA

29

OUT

34 35 36 37 38 40

1

C41_RF
4.7UF

1

C168_RF

16

SHORT-10L-0.25MM-SM 2 DCDC_PGND 1

XW6_RF

20% 2 6.3V X5R 402

10% 2 6.3V X5R-CERM 01005
16

1000PF

NOSTUFF
SHORT-10L-0.25MM-SM 1 2

XW8_RF

DCDC_PGND

PLACE C41 CLOSE TO L21

NOSTUFF

B

B

A
PAGE TITLE DRAWING NUMBER

A
CELLULAR FRONT END: PA DCDC CONVERTER
Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

16 OF 23 39 OF 46

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SHEET

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

2G FEM
D D

43 26 2523 41 33 39 38 35 34 37 36

IN IN

PP_LDO14_2V65 PP_PA

70-OHM-300MA
39 37 36 26 25 23 35 34 38

FL1_RF
01005-1

IN

PP_BATT_VCC_CONN
1

1

2 PP_BATT_VCC_2G_FEM 1

C202_RF
56PF

C65_RF

1

5% 16V 2 NP0-C0G 01005

20% 6.3V 2 X5R-CERM 01005

0.1UF

C66_RF

1

20% 6.3V 2 CERM 0402

10UF

C190_RF

1

20% 6.3V 2 X5R-CERM 01005

0.1UF

C242_RF 1
0.01UF

C67_RF

1

10% 6.3V 2 X5R 01005

20% 6.3V 2 X5R-CERM 01005

0.1UF

1 C203_RF C243_RF

10% 6.3V 2 X5R 01005

0.01UF

5% 16V 2 NP0-C0G 01005

56PF

C
R54_RF
30

2G_FEM_S6 2G_FEM_S5 2G_FEM_S4 2G_FEM_S3 2G_FEM_S2 2G_FEM_S1 2G_FEM_S0
1

IN IN IN IN IN IN IN

2933 41 2941 252941 2933 41 2933 2529 29

C

C200_RF
50_XCVR_2G_LB_TX_MATCH
1

IN

50_XCVR_2G_LB_TX 1

0.00 2
0% 1/32W MF 01005

56PF
1 2

C226_RF C227_RF C228_RF C229_RF C230_RF C231_RF C232_RF
1 1 1 1 1 1

C63_RF

29

34

27

NOSTUFF

1 38

6

5

4 3

2

+/-0.1PF 16V 2 NP0-C0G 01005

1.5PF

5% 16V NP0-C0G 01005

5% 2 16V NP0-C0G 01005

56PF

5% 2 16V NP0-C0G 01005

56PF

5% 2 16V NP0-C0G 01005

56PF

5% 2 16V NP0-C0G 01005

56PF

5% 2 16V NP0-C0G 01005

56PF

5% 2 16V NP0-C0G 01005

56PF

5% 2 16V NP0-C0G 01005

56PF

VDD_SWITCH

VBATT

VCC

30

IN

0.00 2 1 50_XCVR_2G_HB_TX
0% 1/32W MF 01005

R55_RF
1

C201_RF
50_XCVR_2G_HB_TX_MATCH

S6 S5

S4 S3

S2

S1 S0

FIL-COUPLER+LPF-BROADBAND

FL10_RF
0805-6SM

56PF
1 2

50_2G_LB_PA_IN 50_2G_HB_PA_IN
34 37 37

32 LBRF_IN 36 HBRF_IN 25 TRX1 24 TRX2 23 TRX3 22 TRX4 21 TRX5 11 TRX6 10 TRX7 9 TRX8 8 TRX9 7 TRX10

T1 T2

13 50_DRX_ANT 19 50_B3_ANT

LDJ21832M22HC033
OUT BI
41 35

3 4

IN

MAIN OUT

6 1
1

50_LAT_TEST

BI

43

C64_RF

+/-0.1PF 2 16V NP0-C0G 01005

1.5PF

5% 16V NP0-C0G 01005

BI BI BI BI BI BI BI BI BI

50_B1_B4_ANT 50_B8_ANT 50_B5_ANT 50_B2_ANT 50_DCS_RX 50_PCS_RX 50_B20_ANT 50_B17_ANT 50_B13_ANT

U2000_RF
FEM-2G-TX
LGA
ANT1 ANT2 15 17

COUPLE OUT GND

TERMINATE

2 5

NOSTUFF
35 33 33 36 38 38

50_LAT_ASM 50_UAT_ASM

30 OUT

50_PDET_PAD_IN

L56_RF
50_LAT_COUPLER_IN IN
40

15NH-250MA
NOSTUFF
0201

2.4NH+/-0.1NH-0.50A
GND THRM_PAD
30 31 33 35 37 39 40 41 42 43 44 45 46 47 48 49 50
1 0201 2 50_UAT_LPF

L78_RF

FL9_RF
FIL-COUPLER+LPF-BROADBAND

2

LDJ21832M22HB042
1 6 0805-6SM
IN MAIN OUT

3 4 50_COUPLER_TERM

50_UAT_TEST

BI

43

12

14

16 18

20

26 28

B

1

C207_RF
0.4PF
50_LAT_COUPLER_IN

COUPLE OUT GND

TERMINATE

1

B
L57_RF
15NH-250MA
NOSTUFF
0201

+/-0.05PF 25V 2 C0G 40 OUT 201

2 5

1

R35_RF

1% 1/32W MF 2 01005

49.9

2

A
PAGE TITLE

A
DRAWING NUMBER

CELLULAR FRONT END: 2G FEM
Apple Inc. 051-9584 2.0.0
SIZE

D

REVISION BRANCH PAGE

SEE PGS. 21-22 FOR 2G FEM LOGIC TABLE
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

R

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

17 OF 23 40 OF 46

SHEET

8

7

6

5

4

3

2

.

1

8

7

6

5

4

3

2

1

RX DIVERSITY
D D

43

40 33 26 2523

IN

PP_LDO14_2V65

100PF BYPASS INCLUDED IN MODULE

2G_FEM_S3 2G_FEM_S4 2G_FEM_S5 2G_FEM_S6

IN IN IN IN

2933 40 252940 2940 2933 40

C
4 VDD

C
U16_RF
LGA
50_DIVERSITY_SWITCH_MATCH
1

3.3NH+/-0.2NH-0.45A
40

L79_RF
0201

HFQSWXXUA
2

IN

50_DRX_ANT

1

1

V1 V2 V3 V4

5 6 7 8

ANT

GPS/GNSS_OUT_P 12

GPS/GNSS_OUT_N 13

100_XCVR_GPS_RX_N 100_XCVR_GPS_RX_P 100_XCVR_B1_B4_DRX_P 100_XCVR_B1_B4_DRX_N 100_XCVR_B5_B18_B13_B17_DRX_P 100_XCVR_B5_B18_B13_B17_DRX_N 100_XCVR_B8_B20_DRX_P 100_XCVR_B8_B20_DRX_N 100_XCVR_B2_B25_B3_DRX_P 100_XCVR_B2_B25_B3_DRX_N

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

30 30

C255_RF
1.0PF
42

+/-0.1PF 25V 2 C0G 201

IN

50_GPS_LNA_OUT

10

GPS/GNSSIN

BAND1/4_OUT_P 15 BAND1/4_OUT_N 16 B5/18/13/17_OUT_P 19 B5/18/13/17_OUT_N 20 B8/20_OUT_P 21 B8/20_OUT_N 22 B25/3_OUT_P 17 B25/3_OUT_N 18 GND THRM PAD 27 28

30 30

30 30

30 30

30 30

2 3 9 11 14 23 24 25 26

B

B

A

BAND S6 S5 S4 S3 B1/B4 LOW LOW LOW LOW B2/25 LOW HIGH LOW LOW B3 HIGH LOW LOW LOW B5/6/18 LOW LOW HIGH LOW B8 LOW LOW LOW HIGH B13/17 LOW HIGH HIGH HIGH B20 LOW HIGH HIGH LOW OFF LOW LOW HIGH HIGH SWITCH IS TERMINATED IN ALL OTHER POSSIBLE STATES

CELLULAR FRONT END: RX DIVERSITY
DRAWING NUMBER

PAGE TITLE

A
Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

18 OF 23 41 OF 46

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SHEET

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

GPS
D D

C
PP_LDO5_GPS_LNA_2V5
IN
26

C
BYPASSING INCLUDED IN MODULE

GPS FEED
20

9.1NH-5%-250MA
1 0201 2

F-RT-SM

50_UPPER_ANT_FEED

50_GPS_ANT_CONN

2

C221_RF
3.9PF
1 2 1

R GND 3

C

1

50_GPS_ANT_FEED

5 RFIN

SKY65716-11
LGA

U20_RF

7 VDD

L62_RF

MM8830-2600B

J12_RF

RFOUT 9

50_GPS_LNA_OUT

OUT

41

NOTE: ADD SP2 BACK FOR EVT

1 2 3 4 6 8 10 11 12

10NH-3%-250MA
NOSTUFF
0201

2

13

L11_RF

+/-0.05PF 25V C0G-CERM 0201

GND

THRM_PAD

B

B

A
CELLULAR FRONT END: GPS LNA
DRAWING NUMBER PAGE TITLE

A
Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

19 OF 23 42 OF 46

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SHEET

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

ANTENNA FEEDS
D D

UAT1 FEED
1.6X1.21MM
SM-NSP 1
19

SP1_RF

FL1701_RF FLTR-GPS-0603
LFE18832MHC1D449
1
IN NC OUT

50_UPPER_ANT_FEED

3

50_NTCH_FILT_OUT

R1_RF
1 1% 1/20W MF 0201

0.00 2

4.7NH+/-0.2NH-0.44A
50_UPPER_MCH_2
1 1 2 03015

L1732_RF

50_UPPER_MCH_1 PP_LDO14_PAC_2V65

5.6NH-3%-140MA
1 01005 1 1 C99_RF C247_RF 2

L69_RF

2

C1726_RF
0.8PF

PP_LDO14_2V65
IN

232526 33 40

41

NC
L6_RF
01005

+/-0.1PF 25V 2 NP0-C0G 201-HF

VDD 9

5% 16V 2 NP0-C0G 01005

56PF

10% 6.3V 2 X5R 01005

0.01UF

5.6NH-3%-140MA
29 2523

IN

PAC_TO_BB_SPI_DATA_MISO

1

2

PAC_TO_BB_SPI_DATA_MISO_FILT 8 MISO

U7_RF
RF1112
WLCSP 3 RF1 7 CS 5 MOSI 6 SCLK RF2 10 1 12 NC 13 14 GND 2 4 11 50_UAT_COAX_DOWN

UAT1 COAX
TP1_RF 1
A
TP-P6
1

5.6NH-3%-140MA
29 2523

L66_RF
01005

MM5829-2700 MM5829-2700
F-ST-SM F-ST-SM 1

J6_RF

J5_RF

50_UAT_TEST

IN

BB_SPI_TO_PAC_CS

1

2

BB_SPI_TO_PAC_CS_FILT

BI

40

C

5.6NH-3%-140MA
29 2523

L67_RF
01005

IN

BB_SPI_TO_PAC_DATA_MOSI

1

2

BB_SPI_TO_PAC_DATA_MOSI_FILT

NC NC NC NC

4 3

2

2 3

L8_RF
03015

4

1

6.8NH-+/-0.2NH-440MA

C

5.6NH-3%-140MA
29 2523

L68_RF
01005

2

IN

BB_SPI_TO_PAC_CLK

1

2 1

BB_SPI_TO_PAC_CLK_FILT

C96_RF

1

5% 16V 2 NP0-C0G 01005

56PF

C97_RF

1

5% 16V 2 NP0-C0G 01005

56PF

C98_RF

1

5% 16V 2 NP0-C0G 01005

56PF

C38_RF

5% 16V 2 NP0-C0G 01005

56PF

B

LAT
MM5829-2700
F-ST-SM 1

MM8930-2600B
F-RT-SM

J9_RF

B
50_LAT_TEST
BI
40

J4_RF

R11_RF
50_LAT_COAX
1 1

0

2

50_LAT_MATCH

2

C94_RF

5% 1/20W MF 201

R GND 6 5 4 3

C

1

2

3

4

+/-0.1PF 2 25V NP0-C0G 201

1.0PF

1

C95_RF

NOSTUFF

+/-0.1PF 25V 2 NP0-C0G 201

1.0PF

NOSTUFF

A
PAGE TITLE DRAWING NUMBER

A
Apple Inc.
R

CELLULAR FRONT END: ANTENNA FEEDS
051-9584 2.0.0
SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

20 OF 23 43 OF 46

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SHEET

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

FRONT END LOGIC TABLE (1 S2 OF S1 2) BAND S6 S5 S4 S3
D

C

B

LB TX, IDLE, LAT LB TX, IDLE, UAT LB TX, LAT, HPM LB TX, UAT, HPM LB TX, LAT, LPM LB TX, UAT, LPM LB TX, HIGH Z, LAT, LB TX, HIGH Z, UAT, LB TX, HIGH Z, LAT, LB TX, HIGH Z, UAT, HB TX, IDLE, LAT HB TX, IDLE, UAT HB TX, LAT, HPM HB TX, UAT, HPM HB TX, LAT, LPM HB TX, UAT, LPM HB TX, HIGH Z, LAT, HB TX, HIGH Z, UAT, HB TX, HIGH Z, LAT, HB TX, HIGH Z, UAT, GSM850 RX, LAT GSM850 RX, UAT GSM900 RX, LAT GSM900 RX, UAT GSM1900 RX, LAT GSM1900 RX, UAT GSM1800 RX, LAT GSM1800 RX, UAT TERMINATED, UAT TERMINATED, LAT LAT = LOWER ANTENNA UAT = UPPER ANTENNA

HPM HPM LPM LPM

HPM HPM LPM LPM

HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH LOW LOW HIGH HIGH HIGH HIGH

HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH LOW LOW LOW LOW HIGH HIGH LOW LOW LOW LOW

HIGH HIGH HIGH HIGH HIGH HIGH LOW LOW LOW LOW HIGH HIGH HIGH HIGH HIGH HIGH LOW LOW LOW LOW HIGH HIGH HIGH HIGH LOW LOW LOW LOW HIGH HIGH

LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH LOW LOW

LOW LOW HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH LOW LOW HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH LOW LOW HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH

HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW

S0 HIGH HIGH HIGH HIGH LOW LOW HIGH HIGH LOW LOW HIGH HIGH HIGH HIGH LOW LOW HIGH HIGH LOW LOW HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH

TX/PRX PATH LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT UAT LAT

DRX PATH UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT LAT UAT

D

C

B

A
PAGE TITLE DRAWING NUMBER

A
Apple Inc.
R

FRONT END LOGIC TABLE (1 OF 2)
051-9584 2.0.0
SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

21 OF 23 44 OF 46

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SHEET

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

FRONT END LOGIC TABLE - DEV2 (2 S0OF TX/PRX 2)PATH BAND S6 S5 S4 S3 S2 S1
D

C

B

B1/BC6, LAT LOW LOW LOW LOW B1/BC6, UAT LOW LOW LOW LOW B2/B25/BC1, LAT LOW HIGH LOW LOW B2/B25/BC1, UAT LOW HIGH LOW LOW B3, LAT HIGH LOW LOW LOW B3, UAT HIGH LOW LOW LOW B4/BC15, LAT LOW LOW LOW LOW B4/BC15, UAT LOW LOW LOW LOW B5/B6/B18/BC0/BC10, LAT LOW LOW HIGH LOW B5/B6/B18/BC0/BC10, UAT LOW LOW HIGH LOW B8, LAT LOW LOW LOW HIGH B8, UAT LOW LOW LOW HIGH B13, LAT LOW HIGH HIGH HIGH B13, UAT LOW HIGH HIGH HIGH B17, LAT LOW HIGH HIGH HIGH B17, UAT LOW HIGH HIGH HIGH B20, LAT LOW HIGH HIGH LOW B20, UAT LOW HIGH HIGH LOW OFF LOW LOW HIGH HIGH STANDBY LOW LOW LOW LOW LAT = LOWER ANTENNA UAT = UPPER ANTENNA OFF = LOWEST POWER STATE WITHOUT REMOVING LDO14_2V65 POWER STANDBY = ADDED TO SUPPORT EXISTING SW ARCHITECTURE. NOT TO

HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH LOW LOW HIGH HIGH X LOW

HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW X LOW

HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH X LOW

LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT X X

DRX PATH UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT UAT LAT X X

D

C

BE USED AS A LOW POWER STATE.

B

A
PAGE TITLE DRAWING NUMBER

A
Apple Inc.
R

FRONT END LOGIC TABLE (2 OF 2)
051-9584 2.0.0
SIZE

D

REVISION BRANCH PAGE

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

22 OF 23 45 OF 46

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SHEET

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

WLAN/BT
UAT2
MM5829-2700
F-ST-SM

J10_RF

L33_RF

8.2PF
1 2

R13_RF
50_WLAN_ANT_MATCH_T
1 1

2 3

4

D

1

50_WLAN_ANT_FD

0

2 50_WLAN_ANT_MATCH

+/-0.1PF 25V CER 0201

C101_RF

+/-0.1PF 25V 2 COG-CERM 201

0.2PF

5% 1/20W MF 201

D

NOSTUFF

U12_RF DPX205850DT-9038A1SJ
SM 1 HI 3 LO GND COM 5

SHORT-L9-SM 1 2 SHORT-L9-SM 1 2 1

XW20_RF XW9_RF

46

BI BI

50_WLAN_A 50_WLAN_G

46

25

23

IN

PP_VCC_MAIN_WLAN

PP_BATT_VCC_WLAN

C103_RF
10UF

1

C104_RF
27PF

20% 6.3V 2 CERM-X5R 0402-1

5% 16V 2 NP0-C0G 01005

R17_RF
23

PP_WLAN_VDDIO_1V8
1

1

0.00

2

PP_WL_BT_VDDIO_AP

IN

23 25

1

C105_RF
0.01UF

C37_RF
27PF

1

R16_RF
10K
16 BATT_VCC 27 BATT_VCC 28 VBATT_RF_VCC 46 VBATT_RF_VCC 47

10% 6.3V 2 X5R 01005

5% 16V 2 NP0-C0G 01005

0% 1/32W MF 01005

C106_RF

C
25 23

32K INTERFACE TO AP
IN

5% 1/32W MF 2 01005

18PF
1 2

50_WLAN_G
1

2 4 6
BI
46

CLK32K_AP

SHORT-01005 1 2

XW11_RF

VDDIO_1P8V 36 GPIO_6 3 31 CLK32K_AP GPIO_6 VIN_1P2LDO

2% 25V C0H-CERM 0201

C280_RF

C

WLAN_CLK32K

2G_ANT 5G_ANT

43 54

50_WLAN_G_ANT 50_WLAN_A_ANT HOST_WAKE_BT BT_WAKE
OUT
23 25

+/-0.05PF 2 25V COG-CERM 0201

0.2PF

WLAN_BUCK_OUT

HOST_WAKE_BT 41 BT_WAKE 49

C107_RF

NOSTUFF

4.7PF
1 2

IN

23 25

50_WLAN_A

BI

46

25

23

IN IN

WLAN_REG_ON BT_REG_ON
23

51 50 JTAG_SEL 52 30 24 25

WL_REG_ON BT_REG_ON JTAG_SEL SR_VLX WLAN_HSIC_DATA WLAN_HSIC_STROBE SDIO_CLK SDIO_CMD SDIO_DATA0 SDIO_DATA1 SDIO_DATA2 SDIO_DATA3 RF_SW_CTRL_3 RF_SW_CTRL_7 RF_SW_CTRL_8 RF_SW_CTRL_9

U8_RF MOD-WIFI-BT-IMPERIAL
LGA BT_UART_RXD BT_UART_TXD BT_UART_RTS* BT_UART_CTS* BT_PCM_CLK BT_PCM_SYNC BT_PCM_OUT BT_PCM_IN GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_12 GPIO_9 GPIO_10 GPIO_11 GPIO_15 GND 1 23 26 42 44 53

25

23

2.5UH-30%-0.7A-0.24OHM
1 0603
25 25 23 23

L9_RF

2

WLAN_SR_VLX1 50_HSIC_WLAN_DATA 50_HSIC_WLAN_STROBE

39 40 37 38 32 35 33 34 10 5 11 2 4 12 13 8 6 7 9

BT_UART_RXD BT_UART_TXD BT_UART_RTS_L BT_UART_CTS_L BT_PCM_CLK BT_PCM_SYNC BT_PCM_OUT BT_PCM_IN HOST_WAKE_WLAN AP_HSIC3_RDY WLAN_HSIC3_RESUME WLAN_TX_BLANK WLAN_UART_RXD WLAN_UART_TXD WLAN_HSIC3_DEVICE_RDY OSCAR_CONTEXT_A LTE_ACTIVE OSCAR_CONTEXT_B LTE_AGG_PA_ON

IN OUT OUT IN BI BI OUT IN OUT IN OUT OUT IN OUT OUT IN IN IN

23 25 23 25 23 25 23 25

1

+/-0.05PF 25V C0G-CERM 0201

R18_RF
100K

1

C170_RF

1

5% 1/32W MF 2 01005

+/-0.05PF 2 25V COG-CERM 0201

0.2PF

C281_RF

NOSTUFF

+/-0.05PF 25V 2 COG-CERM 0201

0.2PF

NOSTUFF

BI BI

23 25 23 25 23 25 23 25

1

C102_RF
4.7UF
23 23 23 23 2

NC NC
WLAN_COEX_RXD SDIO_DATA_1 SDIO_DATA_2 WLAN_COEX_TXD

20% 2 6.3V X5R-CERM1 402

17 18 20 19 21 22 45 14 15 48

23 25 23 25 23 25 29 23 25 23 25 23 25 2529 29 2529

B

NC NC NC WIFI_SW_CTRL

B

VOUT_3P3 29 THRML_PAD 55 56 57 58 59 60

NC

1

R45_RF
100K

5% 1/32W MF 2 01005

PP_WLAN_VDDIO_1V8
1

23

R14_RF
10K

1

R43_RF
10K

5% 1/32W MF 2 01005

NOSTUFF

5% 1/32W MF 2 01005

R51_RF
6 2

LTE_COEX_TXD

1

0.00 2
0% 1/32W MF 01005

WLAN_COEX_RXD

23

SDIO_DATA_2 JTAG_SEL SDIO_DATA_1

23 23 23

R52_RF
6

LTE_COEX_RXD

1

0.00 2
0% 1/32W MF 01005

WLAN_COEX_TXD

2 23

1

R15_RF
10K

1

R44_RF
10K

A

5% 1/32W MF 2 01005

5% 1/32W MF 2 01005

WIFI/BT: MODULE AND FRONT END
DRAWING NUMBER

PAGE TITLE

A
Apple Inc.
R

051-9584 2.0.0

SIZE

D

REVISION BRANCH PAGE

PULL-UP ON GPIO6, SDIO_DATA_2 & PULL-DOWN ON SDIO_DATA_1 REQUIRED FOR HSIC BOOTSTRAPPING

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

23 OF 23 46 OF 46

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SHEET

8

7

6

5

4

3

2

1


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