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Performance Comparisons Between FLL, PLL and a Novel FLL-Assisted-PLL Carrier Tracking Loop Under RF Interference Conditions

by Phillip W. Ward, Navward GPS Consulting

BIOGRAPHY Mr. Ward is President of Navward GPS Consulting, which he founded in October 1991, in Dallas, Texas. Prior to becoming a consultant, Mr. Ward was Senior Member of the Technical Staff in the Defense Systems & Electronics Group of Texas Instruments Incorporated. Mr. Ward has been involved in the field of navigation since 1958 and with GPS receiver design as a systems engineer since 1976. He was Chair of The Institute of Navigation (ION) Satellite Division (1994-96) and was ION President (1992-93). He is also a Senior Member of the Institute of Electrical and Electronics Engineers, the National Aeronautic Association and is a Registered Professional Engineer in Texas. Mr. Ward received his B.S.E.E. degree from the University of Texas at El Paso and his M.S.E.E. degree from Southern Methodist University in Dallas, TX. He also took postgraduate courses in Computer Science at Massachusetts Institute of Technology. ABSTRACT A well-designed frequency lock loop (FLL) will outperform a well-designed phase lock loop (PLL) tracking threshold under dynamic stress and RF interference (RFI) conditions. However, the PLL will significantly outperform the FLL measurement accuracy. This paper compares the FLL and the PLL tracking thresholds and measurement accuracy. The thresholds are compared under high dynamic stress on the carrier tracking loop and deteriorating signal conditions such as RFI. The comparisons are performed by analytical techniques and by Monte Carlo simulation techniques for several receiver design cases. The results demonstrate the performance advantages of using both the FLL and the PLL. An innovative carrier tracking loop design technique which integrates both the FLL and the PLL characteristics (called an FLL-assisted-PLL) is presented. The FLL-assisted-PLL solves the GPS receiver designer’s dilemma when faced with the need for both the dynamics robustness of FLL plus

the accuracy performance of the PLL. The paper demonstrates that the best overall performance is obtained when the FLL is designed to provide better tracking threshold than the PLL under both high and low dynamic stress. Under RFI conditions, the measure of GPS receiver performance defined here is the tracking threshold under expected maximum line-of-sight dynamic stress conditions. The tracking threshold is then used to predict the jammingto-signal power ratio (J/S) performance of the receiver. The paper also presents a novel approach to comparing dynamic tracking thresholds between the FLL and the PLL as well as comparing measurement accuracy. Analytical techniques are not as reliable as the more sophisticated Monte Carlo simulation techniques in predicting receiver performance, but are an excellent starting point since they require much less computational time and effort. FLL performance is particularly difficult to predict by analysis. The paper provides insight into “rule-of-thumb” assumptions that can be used with analytical techniques in order to more closely compare with the more reliable Monte Carlo simulator results. INTRODUCTION This paper provides both analytical and Monte Carlo simulator performance predictions for the carrier tracking loop of a GPS receiver channel being operated as a frequency lock loop (FLL) or as a phase lock loop (PLL). The tracking loops are subjected to dynamic stress and reduced carrier to noise power ratio (C/N0) caused by RF interference (RFI). The paper also describes and provides Monte Carlo simulator results of a novel combination of these two tracking loops, called an FLL-assisted-PLL. A well-designed code tracking delay lock loop (DLL) will track at considerably lower levels of carrier-to-noise power ratio (C/N0) than the carrier tracking loop in an unaided (stand-alone) GPS receiver. Since both the code and carrier tracking loops must successfully track their respective

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signals in order for the unaided GPS receiver to operate, it suffices to analyze only the (weaker) carrier tracking loop to determine the overall receiver tracking threshold; i.e., the effective C/N0 below which the carrier tracking is no longer successful. In-band RFI on a GPS receiver channel causes the unjammed C/N0 to change to a lower, effective C/N0. When the RFI level produces an effective C/N0 that is equal to the carrier tracking threshold, the change between the unjammed C/N0 and this effective C/N0 is a measure of the jamming-to-signal power ratio (J/S) performance of a GPS receiver. This is the basis for the J/S performance comparisons described in this paper. The dilemma that a GPS receiver tracking loop designer faces is the choice between good dynamic stress performance and precise measurements. This dilemma has been solved for the code tracking loop by the use of a carrier-aided-code DLL. Use of carrier-aided-code tracking puts the dynamic stress burden on the carrier tracking loop. This innovative aiding technique permits the use of a very narrow noise bandwidth code DLL to produce the most precise pseudorange measurements because the DLL does not have to track the full dynamics. The carrier-aided-code technique is a fairly universal GPS receiver design practice. This paper describes an equally innovative aiding technique for the carrier tracking loop called the FLL-assisted-PLL. It is shown in this paper that a well designed FLL can outperform the tracking threshold of a PLL under high dynamic stress as well as under mild dynamic stress. In the first design example, a second order FLL design is less tolerant of the maximum line-of-sight changes in acceleration (jerk stress) between the GPS receiver antenna and the GPS satellite than the third order PLL design, but the FLL design performs better under low jerk stress. In the second design example, the second order FLL is designed so that it outperforms the PLL under both (high and low) dynamic stress conditions. What is often neglected when comparing the FLL to the PLL performance is that the PLL can provide up to two orders of magnitude smaller delta range measurement error than the FLL. Also important to consider is that the dynamic stress is mild most of the time for virtually every GPS receiver application, so that the normal carrier tracking mode should be the PLL mode. It is shown that the FLLassisted-PLL design provides the best features of both tracking techniques when the C/N0 is above the PLL tracking threshold. Below this threshold, the FLL mode should be used. Unfortunately, there are many commercial GPS receivers whose architectures cannot support the FLL or the FLLassisted-PLL modes of operation. As a component-saving measure, which reduces size, weight, power and cost, they do not contain a carrier mixer for the quadra-phase

component. This mixer along with the prompt quadra-phase code correlator plus an integrate and dump accumulator produces a prompt quadra-phase signal (QP) that is essential to the FLL error discriminator design. Only a prompt inphase (IP) signal is generated. The reason is that the QP signal is approximately zero when the receiver is tracking in the PLL mode. In other words, if the receiver can get into the PLL mode and stay there, QP is not required. As a result, the receiver can only support PLL carrier modes. This is a good performance trade-off for receivers which do not require operation in high dynamic environments. However, even under low dynamics, these receivers are vulnerable to false phase lock conditions, which the FLLassisted-PLL design prevents. False phase lock produces very large carrier measurement errors. It would require changes in the custom application specific integrated circuit (ASIC) hardware design to add back the QP component to support FLL modes. This is not a low-cost design change unless a new generation custom ASIC design is in the plans. There are also receivers, typically for military applications, which have been designed for high dynamic environments that support only FLL carrier mode operation. Typically, these receivers can be modified to operate in the FLLassisted-PLL mode with baseband software changes. This is a much lower cost design change than modifying a custom ASIC design. The natural measurement of a GPS carrier tracking loop is the carrier Doppler phase which is an ambiguous range measurement [1]. Usually, two such ambiguous phase measurements are taken separated by a specified interval of time and differenced to form an unambiguous measure of the line-of-sight delta range; i.e., a measure of the average line-of-sight velocity when the delta range measurement is divided by the specified time interval. There are errors in this change in range measurement, primarily due to the reference oscillator frequency offset, so this measurement is sometimes called delta pseudorange. The navigation solution determines the correction required to convert this measurement to a true change in range. Some GPS receiver navigation filters model this measurement as a velocity, but a more accurate model is the total change in range between pseudorange measurements. The error in the delta range over a one-second measurement interval is the basis for accuracy performance comparisons between the FLL and the PLL modes in this paper. TRACKING LOOP DESIGN Figure 1 is a block diagram of two novel FLL-assisted-PLL designs. Figure 1(a) is a first order FLL assisting a second order PLL. Both tracking loops are insensitive to constant velocity stress, but are sensitive to acceleration stress. This paper uses the design in Figure 1(b), which is a second order FLL assisting a third order PLL. This design is

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Frequency error input

70 f

T +

Phase error input

. 702p

a 27 0 p

T

+ +

Σ

.

Z

-1

+ +

Σ

+ 1/2 +

Σ

Velocity accumulator

.

(a) Second order PLL filter with first order FLL assist.

a 2% 0 f

Frequency error input

. %02f . %03p .

a 3% 02p

T + T + +

Z -1

+

Phase error input

Σ

. .

+ +

Σ

+ 1/2 +

Σ

+ T +

Σ

.+

+

Z-1

Σ

+ 1/2 +

Σ

Acceleration accumulator

Velocity accumulator

.

b3% 0p

(b) Third order PLL filter with second order FLL assist.

Figure 1. Block diagram of FLL-assisted-PLL filter design.

insensitive to constant acceleration stress, but is sensitive to jerk stress. The last integrator is not shown in Figure 1 since this function is provided by the numerical controlled oscillator in the receiver design which is usually external to the baseband software implementation of the loop filter. Note that if the PLL error is zeroed, the filter becomes a pure second order FLL design and if the FLL error is zeroed, the filter becomes a pure third order PLL design. When the FLL-assisted-PLL design is used, both an FLL discriminator error and a PLL discriminator error must be implemented and applied to their respective loop filter inputs. Table 1 describes the optimum FLL and PLL error discriminator designs used in the Monte Carlo simulator. Note that two predetection samples must be taken to form the FLL error so that the predetection integration time (PIT) of the FLL must be exactly half that of the PLL. Optimum values are selected so that the FLL PIT is 10 ms and the dddd PLL PIT is 20 ms. The filter is iterated every 20 ms. Reference [2] contains more design detail on carrier loop filters and discriminators. The GPS measurement errors and tracking thresholds are closely related because the receiver loses lock when the measurement errors exceed a certain threshold. Because the code and carrier tracking loops are non-linear, especially near their threshold regions, only Monte Carlo simulator runs of the GPS receiver model under the combined dynamic and C/N0 conditions will determine the true tracking performance. Table 2 summarizes the parameters used for the analysis and Monte Carlo simulator runs. The following is an example of the typical carrier tracking loop design analysis sequence, starting with the FLL.

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Discriminator algorithm Carrier FLL

Characteristics Four-quadrant arctangent. Maximum likelihood estimator. Optimal at high and low SNR. Slope not signal amplitude dependent. Note: IP1 and QP1 are the prompt (or on-time) in-phase and quadra-phase outputs of the integrated and dumped correlation process in the receiver taken during the first predetection integration time sample t1. IP2 and QP2 are the prompt in-phase and quadra-phase outputs of the integrated and dumped correlation process in the receiver taken during the next time sample t2. Two-quadrant arctangent. Optimal (maximum likelihood estimator) at high and low SNR. Slope not signal amplitude dependent. Note: IP and QP are the prompt (or on-time) in-phase and quadra-phase outputs of the integrated and dumped correlation process in the receiver.

ATAN2 (cross, d o t ) (t2 t1 )

where: dot = IP1*IP2 + QP1*QP2 cross = IP1*QP2 - IP2*QP1

Carrier PLL

ATAN (

QP IP

)

Table 1. Discriminators used for Monte Carlo carrier tracking simulations.

Parameter Filter order (FLL/PLL) Filter noise bandwidth (2 cases) Predetection integration time (FLL/PLL) Peak dynamic stress: acceleration, jerk (high dynamics / low dynamics)

Unit dimensionless Hz s G, G/s

Value 2/3 2 / 18 and 4 / 18 0.010 / 0.020 9, 10 / 0.9, 1

Table 2. Parameters used for Monte Carlo carrier tracking simulations.

RULE-OF-THUMB FLL ANALYSIS Rule-of-thumb thresholds can be used along with equations which predict the measurement errors of the tracking loops. Numerous sources of measurement errors are in each type of tracking loop. However, it is sufficient for rule-of-thumb tracking thresholds to analyze only the dominant error sources. The rule-of-thumb tracking threshold for the FLL is that the 3-sigma value of the frequency jitter due to all sources of loop stress must not exceed 90 degrees in one predetection integration time, T, or 90/360T Hz, where T is expressed in units of seconds [2]. The dominant sources of FLL jitter are dddd

due to thermal noise and dynamic stress. Thus, the rule-ofthumb FLL threshold analysis is determined from [2]:

)FLL

where:

= )tFLL + fe/3 0.0833/T (Hz)

(1)

)tFLL

fe T

= 1-sigma thermal noise frequency jitter (Hz) = 3-sigma dynamic stress error (Hz) = predetection integration time (s)

In Equation 1, the thermal noise is a random error while the dynamic stress is treated as a bias error. Therefore, the two sources of error are added. If the dynamic stress for a given application is perceived as random, then the two errors should be root sum squared.

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The FLL jitter due to thermal noise is given by [2]:

)tFLL

4FBn [1 1 1 ] (Hz) T c/no 2%T

c /n o

(2)

based on its relationship to the noise bandwidth also retains the units of s-n, where n = loop filter order. Dividing the numerator by the denominator results in a maximum (3sigma) dynamic stress error of fe = 98 / (0.1903 X 56.96) = 9.04 Hz or a 1-sigma error of 3.01 Hz. Figure 2 illustrates the jerk stress threshold performance of a second order FLL as a function of noise bandwidth with C/N0 as a running parameter. Figure 2 is equally valid for C/A-code or P(Y)-code at L1. The predetection integration time (PIT) is 0.010 s. This is the maximum possible PIT (lowest squaring loss) for the FLL for a 50 Hz navigation data message bit rate (at least two integrated and dumped samples must be taken between data bit transitions). From Equation 1, the 1-sigma FLL jerk stress threshold is: 0.0833 / 0.010 = 8.33 Hz. Equations 2 and 4 are then substituted into 1, and rearranged to solve for the maximum jerk stress at this threshold. Note that, since all curves are at the FLL threshold, F=2 in Equation 2. It may be surprising to observe that, at the lower C/N0 levels, the wider noise bandwidths do not produce the best FLL dynamic stress threshold performance. For example, at 24 dB-Hz, the 4 Hz noise bandwidth appears to be the best and at 28 dB-Hz, the 12 Hz noise bandwidth appears superior. Later it will be observed that this second order FLL presentation technique can be compared “apples-to-apples” with the third order PLL performance using the same presentation technique. Figure 3 illustrates the FLL thermal noise tracking jitter in Hz as a function of C/N0 with the noise bandwidth as a running parameter. A relatively high dynamic stress of 10 G/s is used. The other assumptions are the same as for Figure 2. Equations 2 and 4 are substituted into 1 and solved for the FLL jitter. The results are the same for C/Acode and P(Y)-code at L1. In Figure 3, the PIT is 10 ms for all three design examples, so the threshold is shown as a constant line at 8.33 Hz. However, it should be remembered that the FLL 1-sigma rule-of-thumb threshold changes when the predetection integration time changes. Note that the 2 Hz loop filter appears unable to sustain tracking under the 10 G/s high dynamic stress, so it is selected as a proxy for a poor FLL design for the Monte Carlo simulator. Also note that the 4 Hz loop filter is nearly as robust as the 6 Hz filter under the high dynamic stress. Since the 4 Hz loop filter will outperform the 6 Hz loop filter under low dynamics, it is selected as a proxy for a good FLL design for the Monte Carlo simulator.

)tFLL

4FBn

c /n o

L 1 [1 ] (m / s) T c/no 2%T

(3)

where: F = 1 at high C/N0 = 2 near threshold = carrier loop noise bandwidth (Hz) Bn = carrier- to- noise power ratio (Hz) c/n0

C/N0

T

L

= 10 10 for C/N0 expressed in dB-Hz = predetection integration time (s) = carrier wavelength (m/cycle) = 0.1903 m/cycle for L1 = 0.2442 m/cycle for L2.

Note that Equations 2 and 3 are the same for either C/Acode or P(Y)-code tracking and for any loop order. Equation 2 is the same for either L1 or L2 carrier frequency. Because the FLL tracking loop involves one more integrator than the PLL tracking loop of the same order, the 3-sigma dynamic stress error is [2]:

d nR fe

n

d n 1R

(Hz)

n1 d dt

dt n n dt 360 7 360 70 0

(4)

where: dn+1R/dtn+1 = maximum line-of-sight dynamics (deg/sn+1) n = FLL loop order (dimensionless) 70 = loop filter natural radian frequency (s-1) The second order (n = 2) FLL design of Table 2 with a noise bandwidth of Bn = 4 Hz is used as an example of how the dynamic stress error is computed from Equation 4. If the maximum line-of-sight jerk stress is 10 G/s = 98 m/s3, then, for the L1 carrier frequency (0.1903 m per 360 degree wavelength), the numerator of Equation 4 is: d3R/dt3 = (98 X 360) / 0.1903 degrees/s3. For the second order loop used in this design, Bn = 0.53 70. The denominator of Equation 4 is then: 360 X (4 / 0.53)2 = 360 X 56.96 degrees/cycle-s2. Note that, although the loop filter natural radian frequency, 70, is normally described in units of radians/s, the “radians” term is unit-less in Equation 4. Adjusting this parameter

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220 200 180 160 140 120 100 80 60 40 20 0

Jerk stress (G's / second)

Frequency = 1575.42 MHz F=2 PIT = 0.010 s Loop order = 2

35 dB-Hz

28 dB-Hz 24 dB-Hz 2 4 6 8 10 12 14 16 18

C/No = 24 dB-Hz

Noise bandwidth - Bn (Hz) C/No = 28 dB-Hz C/No = 35 dB-Hz

Figure 2. Second order FLL jerk stress thresholds as a function of noise bandwidth.

25 1-Sigma Jitter (Hz) 20 15 10 5 0 20

Frequency = 1575.42 MHz F=2 PIT = 0.010 s Loop order = 2 22 =24 G/s26 28 30 Jerk 10

6 Hz

2 Hz

4 Hz

31

34

36

38

40

C/No(dB-Hz) Bn = 6 Hz Bn = 4 Hz Bn = 2 Hz Threshold

Figure 3. Second order FLL noise jitter as a function of carrier-to-noise ratio.

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RULE-OF-THUMB PLL ANALYSIS The rule-of-thumb tracking threshold for the PLL is that the 3-sigma value of the jitter due to all sources of loop stress must not exceed 45 degrees [2]. The 1-sigma rule-of-thumb threshold for the PLL tracking loop is therefore [2]:

)PLL

)2 )2 2 PLLt v A e

3

15 (degrees)

(5)

where:

)PLLt )v A e

= PLL thermal noise (degrees) = vibration induced oscillator jitter (degrees) = Allan variance induced oscillator jitter (degrees) = 3-sigma dynamic stress error (degrees)

The third order (n = 3) PLL design of Table 2 with a noise bandwidth of Bn = 18 Hz is used as an example of how the dynamic stress error is computed from Equation 8. If the maximum line-of-sight jerk stress is 10 G/s = 98 m/s3, then, for the L1 carrier frequency (0.1903 m per 360 degree wavelength), the numerator of Equation 8 is: d3R/dt3 = (98 X 360) / 0.1903 = 185391.49 degrees/s3. For the third order loop design used in this paper (minimum mean square error), Bn = 0.7845 70. The denominator of Equation 8 is then: (18 / 0.7845)3 = 12079.21 s-3. Dividing the numerator by the denominator results in a maximum (3-sigma) dynamic stress error of e = 15.35 degrees or a 1-sigma error of 5.12 degrees. Figure 4 illustrates the jerk stress threshold performance of a third order PLL as a function of noise bandwidth with C/N0 as a running parameter. The 20 ms PIT is the maximum possible for the PLL given a 50 Hz navigation data message bit rate. Using Equation 5, the 1-sigma PLL jerk stress threshold is set to 15 degrees. Then Equations 6 and 8 are substituted into 5, and rearranged to solve for the maximum jerk stress at threshold. Note that Figure 4 is equally valid for C/A-code or P(Y)-code at L1. As was the case for the FLL, at the lower C/N0 levels, the wider noise bandwidths do not produce the best PLL dynamic stress threshold performance. For example, at 24 dB-Hz, the 12 Hz noise bandwidth appears to be the best. It is now obvious that the third order PLL dynamic stress performance presentation in Figure 4 can be compared “apples-to-apples” with the second order FLL dynamic performance in Figure 2. Such a comparison reveals that, at the same noise bandwidth, the FLL outperforms the PLL jerk stress tolerance by more than an order of magnitude. However, later it will be seen that the PLL outperforms the FLL accuracy by up to two orders of magnitude and that the FLL noise bandwidth is typically narrower than the PLL noise bandwidth. Figure 5 illustrates the PLL thermal noise tracking jitter in degrees as a function of C/N0 with the noise bandwidth as a running parameter. The same high dynamic stress of 10 G/s is used. The other assumptions are the same as for Figure 4. Equations 6 and 8 are substituted into 5 and solved for the PLL jitter. Again, the results are the same for both C/A-code and P(Y)-code at L1. In Figure 5, the threshold is a constant line at 15 degrees (1-sigma) jitter. Note that the 18 Hz loop filter is the most robust of the three under the 10 G/s high dynamic stress, so it is selected as a proxy for a good PLL design for the Monte Carlo simulator. Past experience has demonstrated that this is about the widest bandwidth for a third order PLL with a 20 ms PIT that remains stable under all signal and dynamics conditions.

In Equation 5, the random phase jitter is the root sum square of every source of uncorrelated phase error such as thermal noise and oscillator noise. Oscillator noise includes jitter induced by vibration and by Allan deviation. The dynamic stress error is treated as a bias which is added to the random jitter. If the dynamic stress for a given application is perceived as random, then all the errors should be root sum squared. In this paper, the PLL thermal noise is treated as the only source of random error, since the oscillator error is considered negligible. Reference [2] describes how to analyze the oscillator errors. This is important for very narrowband (externally aided) PLL applications. Using many of the same variable definitions as for Equations 2 and 3, the formula for the thermal noise jitter in a PLL is defined as [2]:

PLLt

Bn c /n o

[1

1 360 (degree ] 2T c/no 2%

(6)

)PLLt

Bn c /n o

[1

1 ] L (m) 2T c/no 2%

(7)

Note that Equations 6 and 7 are the same for C/A-code or P(Y)-code tracking and for any loop order. Equation 6 is the same for either L1 or L2 carrier frequency. The part of the equation involving the predetection integration time, T, is called the squaring loss. Hence, increasing the predetection integration time reduces the squaring loss, which in turn decreases the thermal noise. The dynamic stress error for the PLL is [2]:

e

d nR/dt n

n 7o

(degrees)

(8)

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22 20 18 16 Jerk stress (G's / sec) 14 12 10 8 6 4 2 0

2 4 6 8 10 12 14 16 18 Freq ue ncy = 15 75 .4 2 M H z P IT = 0 .02 0 s Lo op o rde r = 3

3 5 dB -H z

2 8 dB -H z

2 4 dB -H z

N o is e ba ndwidth - B n (H z) C /N o = 2 4 dB -H z C /N o = 2 8 dB -H z C /N o = 3 5 dB -H z

Figure 4. Third order PLL jerk stress thresholds as a function of noise bandwidth.

20 18 16 14 1-Sigma Jitter (degrees) 16 H z 12 10 8 6 4 2 0 20 22 24 26 28 30 C /N o ( d B - H z ) Bn = 18 H z Bn = 16 H z Bn = 14 H z T h r e s h o ld 32 34 36 38 40

F req u en cy = 1575.42 M H z Jerk = 1 0 G /s P IT = 0 . 0 2 0 s Loop order = 3

14 H z

18 H z

Figure 5. Third order PLL noise jitter as a function of carrier-to-noise power ratio.

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MONTE CARLO SIMULATIONS The design of the Monte Carlo simulator was described in an earlier paper [3]. The GPS receiver design was a C/A-code receiver with the carrier discriminators shown in Table 1 and the baseband design parameters shown in Table 2. There were two FLL designs (2 and 4 Hz) and one PLL design (18 Hz) simulated under both high and low dynamic stress. The two FLL-assisted-PLL design combinations (2/18 and 4/18 Hz) were also simulated under both high and low dynamic stress. The carrier tracking performance was assessed by plotting the number of trials that the receiver successfully tracked for 60 seconds, normalized by the total number of trials. A 60-second run time was chosen because the receiver is subjected to several cycles of the maximum jerk dynamic stress during this interval. A sinusoidal dynamic stress profile was used, so both positive and negative accelerations and velocities were produced and the peak jerk stress occurs twice during each jerk period. The receiver tracking loops were set to steady state tracking conditions at the beginning of each trial. There were 100 trials run for each value of C/N0, each trial with a different random noise seed. The actual tracking threshold of a GPS receiver changes from trial to trial for any given C/N0 that is in the vicinity of the mean threshold. The trials were stopped above C/N0 levels where 100 per cent of the trials were successful and below C/N0 levels where 100 per cent of the trials failed. The C/N0 where 50% of the trials were successful was considered to be the threshold. Tracking failure for the FLL was declared when the 1-sigma frequency error exceeded 0.0833/T (8.33 Hz in these simulations) or when the C/N0 meter was lower than the true C/N0 by more than 3 dB. The frequency error information is not available noise-free in a real world receiver. Normally, the C/N0 meter is used to determine loss of FLL track in a real world receiver, but a filtered variant of the FLL discriminator could be used. Failure criteria for the PLL was the loss of phase lock without recovery. Occasional cycle slips did not constitute a PLL tracking failure for that trial. The phase lock detector used in this assessment was the same design that would be used in a real world receiver. Failure criteria for the FLL-assisted-PLL was a combination of both PLL and FLL threshold conditions simultaneously. The high dynamics threshold results for the 2 Hz FLL, 18 Hz PLL and 2 Hz FLL-assisted-18 Hz PLL are shown in Figure 6. Recall from Figure 3 that the rule-of-thumb threshold analysis predicted that the 2 Hz FLL would not quite track at 10 G/s jerk, but the Monte Carlo simulator results reveal that it will at a high C/N0. Since the 2 Hz FLL does not perform as well as the 18 Hz PLL, it would still not be a good candidate design. The 2 Hz FLL-assisted-18 Hz PLL slightly outperforms the 18 Hz PLL. Figure 7 illustrates the low dynamics results for the same three designs. Note that, without dynamic stress, the 2 Hz FLL significantly outperforms both the 18 Hz PLL and the 2 Hz FLL-assisted-18 Hz PLL. Figures 8 and 9 depict the Monte Carlo simulation

results for the 4 Hz FLL, 18 Hz PLL and 4 Hz FLL-assisted18 Hz PLL designs under high and low dynamics, respectively. Note that the 4 Hz FLL outperforms the other two under both dynamics conditions. Table 3 summarizes the Monte Carlo simulator carrier tracking threshold results. Table 4 compares the threshold performance under high dynamics for the final PLL and FLL designs. The PLL analysis using rule-of-thumb thresholds are more accurate predictions than the FLL comparisons. They are also slightly optimistic. The FLL analysis thresholds are pessimistic; i.e., the Monte Carlo simulator thresholds for FLL are about 1.6 dB lower than the analysis predicts. Table 5 compares the delta range accuracy performance under both high and low dynamics at the unjammed C/N0 of 36 dB-Hz. Reference [3] describes the calculation of the unjammed C/N0 based on typical receiver design assumptions and the minimum received GPS signal level of -160 dBw guaranteed by the space segment. Normally, the received GPS signal will be several dB stronger because the satellite signals are well above the minimum specifications, especially when they are new. Figures 6, 7, 8 and 9 and Table 3 illustrate a very significant tracking threshold characteristic about the FLL-assisted-PLL design: it always outperforms the counterpart PLL-only design, but does not outperform the counterpart FLL-only design if the FLL-only threshold is lower than the PLL-only design. The rule-of-thumb threshold analysis techniques would not provide this design insight. Using this insight, the preferred carrier loop design is for the FLL to outperform the PLL under both high and low dynamic stress, as is the case for the designs of Figures 8 and 9. During initial loop closure tracking conditions, the first carrier tracking mode would be FLL-only, normally with a wider initial noise bandwidth to remove the potentially large frequency uncertainty due to the crude Doppler search process. However, recall from Figure 2 that if the initial FLL bandwidth is selected too wide, it will not perform as well under low C/N0. After initial loop closure in FLL-only, if the C/N0 meter indicates that PLL can be supported and at least three time constants of the FLL-only noise bandwidth have elapsed to allow the tracking loop to settle, the carrier loop transitions into the steady state FLLassisted-PLL mode. An accurate C/N0 meter is used for this transition decision. This technique supports a fail-safe transition from FLL to PLL. A sensitive and accurate phaselock detector determines when the PLL has taken over. The FLL-only mode is also used as a fall-back mode when phase lock is lost. The phase-lock detector is used for this fall-back transition decision. The designs of the phase-lock detector and C/N0 meter will be the subjects of a future paper. When fall back from FLL-assisted-PLL to FLL-only occurs, by design, there is no transient in the tracking loop, so the transition back to the FLL-assisted-PLL mode occurs just as soon as the C/N0 meter indicates that PLL can be supported. An additional benefit of the FLL-assisted-PLL is that the FLL-assist automatically corrects any false phase-lock condition if it occurs in the digital PLL.

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1 0 .9 0 .8 Probabiity of tracking 0 .7 0 .6 0 .5 0 .4 0 .3 0 .2 0 .1 0 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 C /N o ( d B - H z ) F L L /P L L PLL 18H z FLL 2Hz M e a n th r e s h o ld 35 FLL F L L /P L L PLL

Figure 6. High dynamics Monte Carlo simulator results for 2 Hz FLL/18 Hz PLL.

1 0 .9 F L L /P L L 0 .8 Probabiity of tracking 0 .7 0 .6 0 .5 0 .4 0 .3 0 .2 0 .1 0 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 C /N o (dB -H z ) FLL 2Hz F L L /P L L PLL 18H z M e a n thre s ho ld 35 FLL PLL

Figure 7. Low dynamics Monte Carlo simulator results for 2 Hz FLL/18 Hz PLL.

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1 0 .9 0 .8 F L L /P L L Probability of tracking 0 .7 0 .6 0 .5 0 .4 0 .3 0 .2 0 .1 0 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 C /N o (dB -H z) FLL 4Hz F L L /P L L PLL 18H z M e a n thre s ho ld PLL FLL

Figure 8. High dynamics Monte Carlo simulator results for 4 Hz FLL/18 Hz PLL.

1 0 .9 0 .8 Probability of tracking 0 .7 0 .6 0 .5 0 .4 0 .3 0 .2 0 .1 0 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 C /N o (dB -H z) FLL 4Hz F L L /P L L PLL 18H z M e a n thre s ho ld FLL F L L /P L PLL

Figure 9. Low dynamics Monte Carlo simulator results for 4 Hz FLL/18 Hz PLL.

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Parameter Noise bandwidth C/N0 thresholds - 10 G/s C/N0 thresholds - 1 G/s

Units Hz dB-Hz dB-Hz

Initial FLL 2 31.3 20.0

Final FLL 4 23.9 22.5

Initial FLL/PLL 2 / 18 28.0 26.8

Final FLL/PLL 4 / 18 25.8 24.6

PLL 18 28.5 27.5

Table 3. Summary of Monte Carlo simulator tracking threshold results.

Para meter Nois e ba nd width Mo nte Carl o si mulator trac king thr eshol d ( C/N 0 ) - 10 G/s Rule-of thu mb a nalysis tr a ckin g thr eshold ( C/N 0 ) - 10 G/s Differenc e in tr ac king thresh old Mo nte Carl o si mulator pr edicted J/S Rule-of- thu m b analysis pr edicted J/S Differenc e in pr edicted J/S Units Hz d B- H z d B- H z dB dB dB dB FLL 4 23.9 25.5 - 1.6 38.9 37.2 1.7 PLL 18 28.5 28.0 0.5 33.8 34.4 - 0.6

Table 4. Threshold and predicted J/S comparisons at 10 G/s dynamic stress.

Par a meter Nois e b andw idth Pr edetection integr ation time Monte Car lo s imu lator delta r ange er ror - 10 G/s Analys is delta r ange error - 10 G/s Differ ence in delta r ange er ror - 10 G/s Monte Car lo s imu lator delta r ange er ror - 1 G/s Analys is delta r ange error - 1 G/s Differ ence in delta r ange er ror - 1 G/s

Units Hz s m m m m m m

FLL 4 0. 01 0 1. 41 9 0. 76 7 0. 65 2 0. 33 3 0. 25 1 0. 08 2

FLL/PLL 4 / 18 0. 01 0 / 0. 02 0 0. 01 2 N/A N/A 0. 00 8 N/A N/A

PL L 18 0. 02 0 0. 01 1 0. 00 7 0. 00 4 0. 00 7 0. 00 3 0. 00 4

Table 5. Delta range accuracy comparisons at C/N0 = 36 dB-Hz.

Table 5 illustrates that one of the many benefits of a Monte Carlo simulator is that it can compare the error performance of the FLL-only, PLL-only and FLL-assisted-PLL in the same units. Note that the Monte Carlo delta range errors for the PLL modes are more than two orders of magnitude smaller than for FLL-only under high dynamics and more than one order of magnitude smaller under low dynamics.

This is the area where the PLL significantly outperforms the FLL. The motivation for using both the FLL-only and the FLL-assisted-PLL designs now becomes clear: a robust GPS receiver tracking loop can have both the superior dynamic and low C/N0 tracking threshold performance of the FLL and the superior tracking accuracy performance of the PLL. Also note in Table 5 that there is no need to

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further transition into a PLL-only mode since this makes only a minor improvement in the PLL accuracy. Normally, the FLL error prediction by analysis is measured in units of Hertz or meters per second and the PLL error performance is analyzed in units of degrees or meters. A novel way to compare these errors is based on the delta pseudorange measurement that is used by the navigation filter in units of meters. Table 5 also compares the delta pseudorange error predictions for FLL-only and PLL-only by analysis at 36 dB-Hz. The two are compared for a delta pseudorange time interval of one second. Thus, the FLLonly error in meters per second is multiplied by one second assuming that the velocity error is constant over one second. Similarly, the PLL-only error is multiplied by 1.414 assuming that the phase error is the same for the two phase measurements taken one second apart. This is the same as taking the root sum square of the two phase measurement errors. The analysis errors are optimistic and the PLL error by analysis is more accurate than the FLL counterpart. J/S PERFORMANCE COMPARISONS Table 4 also illustrates the predicted J/S performance (assuming a wideband jammer) for the final FLL and PLL designs. The equations used in this paper to compute the predicted J/S performance were shown in reference [3]. The unjammed C/N0 is assumed to be 36 dB-Hz for L1 C/A-code and the equivalent C/N0 is set to the receiver threshold value for each J/S computation. Since the unjammed C/N0 is likely to be much higher, the J/S performance will be better than these worst-case predictions. The Monte Carlo J/S predictions are the most representative and the PLL analysis predictions are more accurate than the FLL analysis predictions. The Monte Carlo simulator predicted J/S performance is about 0.6 dB worse for the PLL and about 1.7 dB better for FLL than their respective rule-of-thumb analysis results predicted. However, the rule-of-thumb analysis results are reasonable starting points for the design and require considerably less computational effort than Monte Carlo simulations. SUMMARY This paper described an analysis approach using rule-ofthumb thresholds and Monte Carlo simulator results to compare the performance of FLL and PLL carrier tracking loops under RFI and dynamic stress conditions. The design of a novel FLL-assisted-PLL tracking loop was also presented and modeled in the Monte Carlo simulator under the same conditions. Two different second order FLL designs (2 Hz and 4 Hz) were presented along with a single third order PLL design (18 Hz) to produce five different carrier tracking loop combinations which were each simulated under both high dynamics (9 G peak acceleration and 10 G/s peak jerk) and low dynamics (0.9 G peak

acceleration and 1 G/s peak jerk). This resulted in a total of 10 Monte Carlo simulator cases. Each case included multiple trials over a range of C/N0 levels which bracketed the level where 50% of the trials were successful. To be statistically significant, there were 100 trials per C/N0 level, each trial with a different random noise seed. The PLL and both FLL designs were analyzed at high dynamics using the rule-of-thumb thresholds. The results show that a welldesigned FLL will significantly outperform the tracking threshold of a well-designed PLL under both high and low dynamics. The improved FLL tracking threshold also improves the J/S performance under RFI conditions. However, the results also show that the PLL is significantly more accurate than the FLL, especially under high dynamics. It was concluded that the FLL-only and the novel FLL-assisted-PLL carrier tracking modes should both be used to obtain the best overall performance. Based on the Monte Carlo simulator results, the transition criteria between these two carrier tracking modes were described. The PLL-only mode was not recommended since there was only a small accuracy improvement compared to the FLLassisted-PLL design. The FLL-assisted-PLL design also prevents all false phase-lock tracking modes in the PLL. ACKNOWLEDGMENTS The author would like to acknowledge Ms. Lorena Sweeney who performed the Monte Carlo simulations. The author also acknowledges that this paper was funded in part by the U.S. Government. However, the analysis and conclusions drawn in this study are those of the author only. REFERENCES [1] Ward, P. W., “The Natural Measurements of a GPS Receiver,” Proceedings of the Institute of Navigation 51st Annual Meeting, pp 67-85, Colorado Springs, CO, June, 1995. [2] Kaplan, E. D., editor, Understanding GPS: Principals and Applications, Chapter 5, P. W. Ward, author, “Satellite Signal Acquisition and Tracking,” pp. 119-208, Artech House Publishers, Boston, MA, 1996. [3] Ward, P. W., “Using a GPS Receiver Monte Carlo Simulator to Predict RF Interference Performance,” Proceedings of The 10th International Technical Meeting of The Satellite Division of The Institute of Navigation, ION GPS-97, pp. 1473-1482, Kansas City, MO, September, 1997.

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