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CDB5571;中文规格书,Datasheet资料


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CS5571

±2.5 V / 5 V, 100 kSps, 16-bit, High-throughput ?Σ ADC
Features & Description
? Single-ended Analog Input ? On-chip Buffers for High Input Impedance ? Conversion Time = 10 ?S ? Settles in One Conversion ? Linearity Error = 0.0008% ? Signal-to-Noise = 92 dB ? S/(N + D) = 91 dB ? DNL = ±0.1 LSB Max. ? Simple three/four-wire serial interface ? Power Supply Configurations:
- Analog: +5V/GND; IO: +1.8V to +3.3V - Analog: ±2.5V; IO: +1.8V to +3.3V

General Description
The CS5571 is a single-channel, 16-bit analog-to-digital converter capable of 100 kSps conversion rate. The input accepts a single-ended analog input signal. On-chip buffers provide high input impedance for both the AIN input and the VREF+ input. This significantly reduces the drive requirements of signal sources and reduces errors due to source impedances. The CS5571 is a delta-sigma converter capable of switching multiple input channels at a high rate with no loss in throughput. The ADC uses a low-latency digital filter architecture. The filter is designed for fast settling and settles to full accuracy in one conversion. The converter's 16-bit data output is in serial format, with the serial port acting as either a master or a slave. The converter is designed to support bipolar, ground-referenced signals when operated from ±2.5V analog supplies. The converter can operate from an analog supply of 0-5V or from ±2.5V. The digital interface supports standard logic operating from 1.8, 2.5, or 3.3 V. ORDERING INFORMATION: See Ordering Information on page 34.

? Power Consumption:
- ADC Input Buffers On: 85 mW - ADC Input Buffers Off: 60 mW

V1+

V2+

VL

CS5571
VREF+ VREFDIGITAL FILTER LOGIC SERIAL INTERFACE SMODE CS SCLK ADC AIN ACOM

SDO RDY

BUFEN DIGITAL CONTROL OSC/CLOCK GENERATOR

DITHER RST CONV BP/UP MCLK

V1-

V2-

TST

DCR

VLR

VLR2

Preliminary Product Information
http://www.cirrus.com

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

Copyright ? Cirrus Logic, Inc. 2008 (All Rights Reserved)

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CS5571
TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ANALOG CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DIGITAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 GUARANTEED LOGIC LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2. OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3. THEORY OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 Output Coding Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6 Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7 AIN & VREF Sampling Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.8 Converter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9 DITHER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10 Digital Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.11 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.11.1 SSC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.11.2 SEC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.12 Power Supplies & Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.13 Using the CS5571 in Multiplexing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.14 Synchronizing Multiple Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4. PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5. PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION . . . . . . . . . . . . . . 34 8. REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

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CS5571
LIST OF FIGURES

Figure 1. SSC Mode - Read Timing, CS remaining low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. SSC Mode - Read Timing, CS falling after RDY falls . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. SEC Mode - Continuous SCLK Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. SEC Mode - Discontinuous SCLK Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. Voltage Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. CS5571 Configured Using ±2.5V Analog Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7. CS5571 Configured for Unipolar Measurement Using a Single 5V Analog Supply . . . . 18 Figure 8. CS5571 Configured for Bipolar Measurement Using a Single 5V Analog Supply . . . . . 19 Figure 9. CS5571 DNL Plot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 10. CS5581 DNL Error Plot with DNL Histogram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 11. Spectral Performance, 0 dB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 12. Spectral Performance, -6 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 13. Spectral Performance, -12 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 14. Spectral Performance, -80 dB Dither On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 15. Spectral Performance, -80 dB Dither Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 16. Spectral Performance, -100 dB Dither On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 17. Spectral Performance, -100 dB Dither Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 18. Spectral Performance, -116.3 dB Dither On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 19. Spectral Plot of Noise with Shorted Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 20. Noise Histogram, 4096 Samples Dither On, Code Center. . . . . . . . . . . . . . . . . . . . . . 24 Figure 21. Noise Histogram, 4096 Samples Dither Off, Code Center. . . . . . . . . . . . . . . . . . . . . . 24 Figure 22. Noise Histogram, 4096 Samples Dither On, Input at Code Boundary . . . . . . . . . . . . . 24 Figure 23. Noise Histogram, 4096 Samples Dither Off, Input at Code Boundary . . . . . . . . . . . . . 24 Figure 24. CS5571 Digital Filter Response (DC to fs/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 25. CS5571 Digital Filter Response (DC to 10 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 26. CS5571 Digital Filter Response (DC to 4fs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 27. Simple Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 28. More Complex Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

LIST OF TABLES
Table 1. Output Coding, Two’s Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 2. Output Coding, Offset Binary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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1. CHARACTERISTICS AND SPECIFICATIONS
? ? ?

CS5571

Min / Max characteristics and specifications are guaranteed over the specified operating conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25°C. VLR = 0 V. All voltages measured with respect to 0 V.

TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 16 MHz; SMODE = VL. DITHER = VL unless otherwise stated; BUFEN = V1+ unless otherwise stated. Connected per Figure 6. Bipolar mode unless otherwise stated. Parameter Accuracy Linearity Error Differential Linearity Error Positive Full-scale Error Negative Full-scale Error Full-scale Drift Bipolar Offset Bipolar Offset Drift Noise Dynamic Performance Peak Harmonic or Spurious Noise Total Harmonic Distortion Signal-to-Noise S/(N + D) Ratio -3 dB Input Bandwidth
1. 2. 3. 4. 5.

ANALOG CHARACTERISTICS

Min (Note 1) (Note 2, 3) (Note 2) (Note 2, 3) (Note 4) 1 kHz, -0.5 dB Input 12 kHz, -0.5 dB Input 1 kHz, -0.5 dB Input -0.5 dB Input, 1 kHz -60 dB Input, 1 kHz (Note 5) 91 -

Typ 0.0008 1.0 1.0 ±1 ±15 ±1 36 -96 -96 -94 92 91 32 84

Max ±0.1 -82 -

Unit ±%FS LSB16 %FS %FS LSB16 LSB16 LSB16 ?Vrms dB dB dB dB dB dB kHz

No missing codes is guaranteed at 16 bits resolution over the specified temperature range. One LSB is equivalent to VREF ÷ 216 or 4.096 ÷ 65536 = 62.5 ?V. Total drift over specified temperature range after reset at power-up, at 25? C. With DITHER off the output will be dominated by quantization. Scales with MCLK.

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ANALOG CHARACTERISTICS (CONTINUED)

CS5571

TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 16 MHz; SMODE = VL. DITHER = VL unless otherwise stated; BUFEN = V1+ unless otherwise stated. Connected per Figure 6. Parameter Analog Input Analog Input Range Input Capacitance CVF Current (Note 6) AIN Buffer On (BUFEN = V+) AIN Buffer Off (BUFEN = V-) ACOM Unipolar Bipolar 0 to +VREF / 2 ±VREF / 2 10 600 130 130 V V pF nA ?A ?A Min Typ Max Unit

Voltage Reference Input Voltage Reference Input Range (VREF+) – (VREF-) Input Capacitance CVF Current VREF+ Buffer On (BUFEN = V+) VREF+ Buffer Off (BUFEN = V-) VREFIV1 IV2 IVL Normal Operation Buffers On Buffers Off (Note 8) V1+ , V2+ Supplies V1-, V2- Supplies (Note 7) 2.4 4.096 10 3 1 1 85 60 80 80 4.2 18 1.8 0.6 101 80 V pF ?A mA mA mA mA mA mW mW dB dB

Power Supplies DC Power Supply Currents

Power Consumption Power Supply Rejection

6. 7. 8.

Measured using an input signal of 1 V DC. For optimum performance, VREF+ should always be less than (V+) - 0.2 volts to prevent saturation of the VREF+ input buffer. Tested with 100 mVp-p on any supply up to 1 kHz. V1+ and V2+ supplies at the same voltage potential, V1- and V2- supplies at the same voltage potential.

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SWITCHING CHARACTERISTICS
TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF. Parameter Master Clock Frequency Master Clock Duty Cycle Reset RST Low Time RST rising to RDY falling Conversion CONV Pulse Width BP/UP setup to CONV falling CONV low to start of conversion Perform Single Conversion (CONV high before RDY falling) Conversion Time
9. 10. 11.

CS5571

Symbol Internal Oscillator External Clock XIN fclk

Min 12 0.5 40

Typ 14 16 120 1536 -

Max 16 16.2 60 2 164

Unit MHz MHz % ?s ?s MCLKs MCLKs ns MCLKs MCLKs MCLKs

(Note 9) Internal Oscillator External Clock

tres twup

1 4 0 20 -

tcpw (Note 10) tscn tscn tbus tbuh

(Note 11) Start of Conversion to RDY falling

Reset must not be released until the power supplies and the voltage reference are within specification. BP/UP can be changed coincident to CONV falling. BP/UP must remain stable until RDY falls. If CONV is held low continuously, conversions occur every 160 MCLK cycles. If RDY is tied to CONV, conversions will occur every 162 MCLKs. If CONV is operated asynchronously to MCLK, a conversion may take up to 164 MCLKs. RDY falls at the end of conversion.

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SWITCHING CHARACTERISTICS (CONTINUED)
TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF. Parameter Serial Port Timing in SSC Mode (SMODE = VL) RDY falling to MSB stable Data hold time after SCLK rising Serial Clock (Out) (Note 12, 13) RDY rising after last SCLK rising
12.

CS5571

Symbol t1 t2 Pulse Width (low) Pulse Width (high) t3 t4 t5

Min 50 50 -

Typ -2 10 8

Max -

Unit MCLKs ns ns ns MCLKs

SDO and SCLK will be high impedance when CS is high. In some systems SCLK and SDO may require pull-down resistors. 13. SCLK = MCLK/2.

MCLK

RDY t1 CS t2 SCLK(o) t3 t4 t5

SDO

MSB

MSB–1

LSB+1

LSB

Figure 1. SSC Mode - Read Timing, CS remaining low (Not to Scale)

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SWITCHING CHARACTERISTICS (CONTINUED)
TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF. Parameter Serial Port Timing in SSC Mode (SMODE = VL) Data hold time after SCLK rising Serial Clock (Out) (Note 14, 15) RDY rising after last SCLK rising CS falling to MSB stable First SCLK rising after CS falling CS hold time (low) after SCLK rising SCLK, SDO tri-state after CS rising
14.

CS5571

Symbol t7 Pulse Width (low) Pulse Width (high) t8 t9 t10 t11 t12 t13 t14

Min 50 50 10 -

Typ 10 8 10 8 5

Max -

Unit ns ns ns MCLKs ns MCLKs ns ns

SDO and SCLK will be high impedance when CS is high. In some systems SCLK and SDO may require pull-down resistors. 15. SCLK = MCLK/2.

MCLK t10 RDY t13 CS t12 SCLK(o) t11 SDO
MSB MSB–1 LSB+1 LSB

t7

t8

t9

t14

Figure 2. SSC Mode - Read Timing, CS falling after RDY falls (Not to Scale)

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SWITCHING CHARACTERISTICS (CONTINUED)
TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF. Parameter Serial Port Timing in SEC Mode (SMODE = VLR) SCLK(in) Pulse Width (High) SCLK(in) Pulse Width (Low) CS hold time (high) after RDY falling CS hold time (high) after SCLK rising CS low to SDO out of Hi-Z Data hold time after SCLK rising Data setup time before SCLK rising CS hold time (low) after SCLK rising RDY rising after SCLK falling
16.
-

CS5571

Symbol

Min 30 30 10 10 10 10 -

Typ 10 10 10

Max 1 10 SCLK

Unit ns ns ns ns ns ns ns ns ns

t15 t16 (Note 16) t17 t18 t19 t20 t21

-

SDO will be high impedance when CS is high. In some systems SDO may require a pull-down resistor.

MCLK t21 RDY t15 CS t16 SCLK(i) t17 SDO t18 t19
MSB LSB

t20

Figure 3. SEC Mode - Continuous SCLK Read Timing (Not to Scale)

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CS5571

MCLK t21 RDY t15 CS t20

SCLK(i) t17 SDO t18 t19
MSB LSB

Figure 4. SEC Mode - Discontinuous SCLK Read Timing (Not to Scale)

DIGITAL CHARACTERISTICS
TA = TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V Parameter Input Leakage Current Digital Input Pin Capacitance Digital Output Pin Capacitance Symbol Iin Cin Cout Min Typ 3 3 Max 2 Unit ?A pF pF

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分销商库存信息:
CIRRUS-LOGIC CDB5571


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