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CS5463-ISZ;CS5463-ISZR;CS5463-IS;CRD5463PM;CDB5463U;中文规格书,Datasheet资料


CS5463 Single Phase, Bi-directional Power/Energy IC
Features
? Energy

Description
The CS5463 is an integrated power measurement device which combines two ?? analog-to-digital converters, power calculation engine, energy-to-frequency converter, and a serial interface on a single chip. It is designed to accurately measure instantaneous current and voltage, and calculate VRMS, IRMS, instantaneous power, apparent power, active power, and reactive power for single-phase, 2- or 3-wire power metering applications. The CS5463 is optimized to interface to shunt resistors or current transformers for current measurement, and to resistive dividers or potential transformers for voltage measurement. The CS5463 features a bi-directional serial interface for communication with a processor and a programmable energy-to-pulse output function. Additional features include on-chip functionality to facilitate system-level calibration, temperature sensor, voltage sag detection, and phase compensation.
ORDERING INFORMATION:
See Page 45.
VD+

Data Linearity: ±0.1% of Reading over 1000:1 Dynamic Range

? On-chip Functions: - Instantaneous Voltage, Current, and Power - IRMS and VRMS, Apparent, Reactive, and Active (Real) Power - Active Fundamental and Harmonic Power - Reactive Fundamental, Power Factor, and Line Frequency - Energy-to-pulse Conversion - System Calibrations and Phase Compensation - Temperature Sensor ? Meets

accuracy spec for IEC, ANSI, JIS. ? Low Power Consumption ? Current Input Optimized for Sense Resistor. ? GND-referenced Signals with Single Supply ? On-chip 2.5 V Reference (25 ppm/°C typ) ? Power Supply Monitor ? Simple Three-wire Digital Serial Interface ? “Auto-boot” Mode from Serial E2PROM ? Power Supply Configurations:
VA+ = +5 V; AGND = 0 V; VD+ = +3.3 V to +5 V
VA+ RESET

IIN+ IIN-

PGA

4th Order ?? Modulator

Digital Filter

HPF Option

MODE CS Power Calculation Engine SDI Serial Interface SDO SCLK INT

VREFIN

x1

Temperature Sensor

VIN+ VIN-

x10

2nd Order ?? Modulator

Digital Filter

HPF Option

E-to-F

E1 E2 E3

VREFOUT

Voltage Reference

Power Monitor

System Clock

/K

Clock Generator

Calibration

AGND

PFMON

XIN XOUT CPUCLK

DGND

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Copyright ? Cirrus Logic, Inc. 2011 (All Rights Reserved)

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CS5463
TABLE OF CONTENTS
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. Characteristics & Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Voltage and Current Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Power Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Linearity Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 14 15

5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1.1 Voltage Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.2 Current Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 IIR Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 High-pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Performing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Energy Pulse Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 16 17

5.5.1 Active Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 Apparent Energy Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3 Reactive Energy Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.4 Voltage Channel Sign Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.5 PFMON Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.6 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 Sag and Fault Detect Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 No Load Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 On-chip Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11 Power-down States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13 Event Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17 18 18 18 19 19
19 19 19 20 20 20 20 21

5.13.1 Typical Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.14 Serial Port Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.14.1 Serial Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.15 Register Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16.1 Start Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16.2 SYNC0 and SYNC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16.3 Power-up/Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16.4 Power-down and Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16.5 Register Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16.6 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Page 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Configuration Register ( Config ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 Current and Voltage DC Offset Register ( IDCoff , VDCoff ) . . . . . . . . . . . . 6.1.3 Current and Voltage Gain Register ( Ign , Vgn ) . . . . . . . . . . . . . . . . . . . . 6.1.4 Cycle Count Register ( Cycle Count ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.5 PulseRateE Register ( PulseRateE ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.6 Instantaneous Current, Voltage, and Power Registers ( I , V , P ) . . . . . . 22 23 23 23 23 23 24 25 26 26 27 27 27 27 28

6. Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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CS5463
6.1.7 Active (Real) Power Register ( PActive ) . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.8 RMS Current & Voltage Registers ( IRMS , VRMS ) . . . . . . . . . . . . . . . . . . 6.1.9 Epsilon Register ( e ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.10 Power Offset Register ( Poff ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.11 Status Register and Mask Register ( Status , Mask ) . . . . . . . . . . . . . . . 6.1.12 Current and Voltage AC Offset Register ( VACoff , IACoff ) . . . . . . . . . . . 6.1.13 Operational Mode Register ( Mode ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.14 Temperature Register ( T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.15 Average and Instantaneous Reactive Power Register ( QAVG , Q ) . . . . 6.1.16 Peak Current and Peak Voltage Register ( Ipeak , Vpeak ) . . . . . . . . . . . . 6.1.17 Reactive Power Register ( QTrig ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.18 Power Factor Register ( PF ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.19 Apparent Power Register ( S ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.20 Control Register ( Ctrl ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.21 Harmonic Active Power Register ( PH ) . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.22 Fundamental Active Power Register ( PF ) . . . . . . . . . . . . . . . . . . . . . . 6.1.23 Fundamental Reactive Power Register ( QH ) . . . . . . . . . . . . . . . . . . . . 6.1.24 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Page 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Energy Pulse Output Width ( PulseWidth ) . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 No Load Threshold ( LoadMin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3 Temperature Gain Register ( TGain ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.4 Temperature Offset Register ( TOff ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Page 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Voltage Sag & Current Fault Duration Registers . . . . . . . . . . . . . . . . . . . 6.3.2 Voltage Sag & Current Fault Level Registers . . . . . . . . . . . . . . . . . . . . . . . 28 28 28 29 29 30 30 31 31 31 32 32 32 33 33 33 34 34 35 35 35 35 35 36 36 36

7. System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1 Channel Offset and Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.1.1 Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1.1 Duration of Calibration Sequence . . . . . . . . . . . . . . . . . . . . . 7.1.2 Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.2.1 DC Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . 7.1.2.2 AC Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . 7.1.3 Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.3.1 AC Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . 7.1.3.2 DC Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . 7.1.4 Order of Calibration Sequences . . . . . . . . . . . . . . . . . . . . . . . . . .

37 37 37 37 38 38 38 39 39

8. Auto-boot Mode Using E2PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.2 Phase Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.3 Active Power Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.1 Auto-boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.2 Auto-boot Data for E2PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.3 Which E2PROMs Can Be Used? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9. Basic Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10. Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . 13. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

41 44 45 45 46

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CS5463
LIST OF FIGURES
Figure 1. CS5463 Read and Write Timing Diagrams.................................................................. 12 Figure 2. Timing Diagram for E1, E2, and E3....................................................................................... 13 Figure 3. Data Measurement Flow Diagram. .............................................................................. 14 Figure 4. Power Calculation Flow. .............................................................................................. 15 Figure 5. Active and Reactive Energy Pulse Outputs ................................................................. 17 Figure 6. Apparent Energy Pulse Outputs .................................................................................. 18 Figure 7. Voltage Channel Sign Pulse outputs ........................................................................... 18 Figure 8. PFMON Output to Pin E3....................................................................................................... 19 Figure 9. Sag and Fault Detect ................................................................................................... 19 Figure 10. Oscillator Connection................................................................................................. 20 Figure 11. CS5463 Memory Map ................................................................................................ 22 Figure 12. Calibration Data Flow ................................................................................................ 37 Figure 13. System Calibration of Offset ...................................................................................... 37 Figure 14. System Calibration of Gain. ....................................................................................... 38 Figure 15. Example of AC Gain Calibration ................................................................................ 38 Figure 16. Example of AC Gain Calibration ................................................................................ 38 Figure 17. Typical Interface of E2PROM to CS5463................................................................... 40 Figure 18. Typical Connection Diagram (Single-phase, 2-wire).................................................. 41 Figure 20. Typical Connection Diagram (Single-phase, 3-wire).................................................. 42 Figure 19. Typical Connection Diagram (Single-phase, 2-wire – Isolated from Power Line) ...... 42 Figure 21. Typical Connection Diagram (Single-phase, 3-wire – No Neutral Available) ............. 43

LIST OF TABLES
Table 1. Current Channel PGA Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 2. E2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 3. E3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4. Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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CS5463
1. OVERVIEW
The CS5463 is a CMOS monolithic power measurement device with a computation engine and an energy-to-frequency pulse output. The CS5463 combines a programmable gain amplifier, two ?? Analog-to-Digital Converters (ADCs), system calibration, and a computation engine on a single chip. The CS5463 is designed for power measurement applications and is optimized to interface to a current sense resistor or transformer for current measurement, and to a resistive divider or potential transformer for voltage measurement. The current channel provides programmable gains to accommodate various input levels from a multitude of sensing elements. With single +5 V supply on VA+/AGND, both of the CS5463’s input channels can accommodate common mode plus signal levels between (AGND - 0.25 V) and VA+. The CS5463 also is equipped with a computation engine that calculates instantaneous power, IRMS, VRMS, apparent power, active (real) power, reactive power, harmonic active power, active and reactive fundamental power, and power factor. The CS5463 additional features include line frequency, current and voltage sag detection, zero-cross detection, positive-only accumulation mode, and three programmable pulse output pins. To facilitate communication to a microprocessor, the CS5463 includes a simple three-wire serial interface which is SPI? and Microwire? compatible. The CS5463 provides three outputs for energy registration. E1, E2, and E3 are designed to interface to a microprocessor.

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CS5463
2. PIN DESCRIPTION
Crystal Out XOUT CPU Clock Output CPUCLK Positive Digital Supply VD+ Digital Ground DGND Serial Clock SCLK Serial Data Ouput SDO Chip Select CS Mode Select MODE Differential Voltage Input VIN+ Differential Voltage Input VINVoltage Reference Output VREFOUT Voltage Reference Input VREFIN 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 XIN SDI E2 E1 INT RESET E3 PFMON IIN+ IINVA+ AGND Crystal In Serial Data Input Energy Output 2 Energy Output 1 Interrupt Reset High Frequency Energy Output Power Fail Monitor Differential Current Input Differential Current Input Positive Analog Supply Analog Ground

Clock Generator Crystal Out Crystal In CPU Clock Output Control Pins and Serial Data I/O Serial Clock Input Serial Data Output Chip Select Mode Select Energy Output 5 6 7 8
SCLK – A Schmitt-trigger input pin. Clocks data from the SDI pin into the receive buffer and out of the transmit buffer onto the SDO pin when CS is low. SDO – Serial port data output pin.SDO is forced into a high-impedance state when CS is high. CS – Low, activates the serial port interface. MODE - High, enables the “auto-boot” mode. The mode pin has an internal pull-down resistor. figurable outputs for active, apparent, and reactive power, negative energy indication, zero cross detection, and power failure monitoring. E1, E2, E3 outputs are configured in the Operational Modes Register.

1,24

XOUT, XIN – The output and input of an inverting amplifier. Oscillation occurs when connected to a crystal, providing an on-chip system clock. Alternatively, an external clock can be supplied to the XIN pin to provide the system clock for the device. CPUCLK – Output of on-chip oscillator which can drive one standard CMOS load.

2

18,21,22 E3, E1, E2 – Active-low pulses with an output frequency proportional to the selected power. Con-

Reset Interrupt Serial Data Input Analog Inputs/Outputs Differential Voltage Inputs Differential Current Inputs Voltage Reference Output Voltage Reference Input Power Supply Connections Positive Digital Supply Digital Ground Positive Analog Supply Analog Ground Power Fail Monitor

19 20 23

RESET – A Schmitt-trigger input pin. Low activates Reset, all internal registers (some of which drive output pins) are set to their default states. INT - Low, indicates that an enabled event has occurred. SDI - Serial port data input pin. Data will be input at a rate determined by SCLK.

9,10 15,16 11 12

VIN+, VIN- – Differential analog input pins for the voltage channel. IIN+, IIN- – Differential analog input pins for the current channel. VREFOUT – The on-chip voltage reference output. The voltage reference has a nominal magnitude of 2.5 V and is referenced to the AGND pin on the converter. VREFIN – The input to this pin establishes the voltage reference for the on-chip modulator.

3 4 14 13

VD+ – The positive digital supply. DGND – Digital Ground. VA+ – The positive analog supply. AGND – Analog ground. PFMON – The power fail monitor pin monitors the analog supply. If the analog supply does not meet or falls below PFMON’s voltage threshold, a Low-supply Detect (LSD) event is set in the status register.

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CS5463
3. CHARACTERISTICS & SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter Positive Digital Power Supply Positive Analog Power Supply Voltage Reference Specified Temperature Range Symbol VD+ VA+ VREFIN TA Min 3.135 4.75 -40 Typ 5.0 5.0 2.5 Max 5.25 5.25 +85 Unit V V V °C

ANALOG CHARACTERISTICS
? ? ? ? Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C. VA+ = VD+ = 5 V ±5%; AGND = DGND = 0 V; VREFIN = +2.5 V. All voltages with respect to 0 V. MCLK = 4.096 MHz.

Parameter
Accuracy

Symbol PActive QAvg PF

Min

Typ

Max

Unit

Active Power (Note 1) Average Reactive Power (Note 1 and 2) Power Factor (Note 1 and 2) Current RMS (Note 1) Voltage RMS (Note 1)
Analog Inputs (Both Channels)

All Gain Ranges Input Range 0.1% - 100% All Gain Ranges Input Range 0.1% - 100% All Gain Ranges Input Range 1.0% - 100% Input Range 0.1% - 1.0% All Gain Ranges Input Range 0.2% - 100% Input Range 0.1% - 0.2% All Gain Ranges Input Range 5% - 100% (DC, 50, 60 Hz) All Gain Ranges (Gain = 10) (Gain = 50) (Gain = 50) (50, 60 Hz) (Gain = 10) (Gain = 50) (Gain = 10) (Gain = 50) (Note 3)

80 -0.25 80 30 -

±0.1 ±0.2 ±0.2 ±0.27 ±0.2 ±1.5 ±0.1 500 100 94 -115 32 52 22.5 4.5 4.0 ±0.4

VA+ -

% % % % % % % % dB V mVP-P mVP-P dB dB pF pF k? ?Vrms ?Vrms ?V/°C %

IRMS VRMS CMRR

Common Mode Rejection Common Mode + Signal
Analog Inputs (Current Channel)

Differential Input Range [(IIN+) - (IIN-)] Total Harmonic Distortion Crosstalk with Voltage Channel at Full Scale Input Capacitance Effective Input Impedance Noise (Referred to Input) Offset Drift (Without the High Pass Filter) Gain Error

IIN THD IC EII NI OD GE

Notes: 1. Applies when the HPF option is enabled. 2. Applies when the line frequency is equal to the product of the Output Word Rate (OWR) and the value of epsilon (?).

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CS5463
ANALOG CHARACTERISTICS (Continued)
Parameter
Analog Inputs (Voltage Channel)

Symbol [(VIN+) - (VIN-)] VIN THD IC EII NV OD GE T PSCA PSCD PSCD PC

Min 65 2 45 70 2.3 -

Typ 500 75 -70 0.2 140 16.0 ±3.0 ±5 1.1 2.9 1.7 21 11.6 8 10 65 75 2.45 2.55

Max -

Unit mVP-P dB dB pF M? ?Vrms ?V/°C % °C mA mA mA mW mW mW ?W dB dB V V

Differential Input Range

Total Harmonic Distortion Crosstalk with Current Channel at Full Scale (50, 60 Hz) Input Capacitance All Gain Ranges Effective Input Impedance Noise (Referred to Input) Offset Drift (Without the High Pass Filter) Gain Error
Temperature Channel

(Note 3)

Temperature Accuracy
Power Supplies

29 17.5 2.7

Power Supply Currents (Active State) IA+ ID+ (VA+ = VD+ = 5 V) ID+ (VA+ = 5 V, VD+ = 3.3 V) Power Consumption Active State (VA+ = VD+ = 5 V) (Note 4) Active State (VA+ = 5 V, VD+ = 3.3 V) Stand-by State Sleep State Power Supply Rejection Ratio (50, 60 Hz) (Note 5) Voltage Channel Current Channel PFMON Low-voltage Trigger Threshold (Note 6) PFMON High-voltage Power-on Trip Point (Note 7) Notes: 3. Applies before system calibration. 4. All outputs unloaded. All inputs CMOS level.

PSRR PMLO PMHI

5. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV (zero-to-peak) (60 Hz) sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to AGND. Then the CS5463 is commanded to continuous conversion acquisition mode, and digital output data is collected for the channel under test. The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB):

150 PSRR = 20 ? log --------V eq

6. When voltage level on PFMON is sagging, and LSD bit = 0, the voltage at which LSD is set to 1. 7. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on PFMON at which the LSD bit can be permanently reset back to 0.

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DS678F3

CS5463
VOLTAGE REFERENCE
Parameter
Reference Output

Symbol VREFOUT (Note 8) (Note 9) TCVREF ? VR VREFIN

Min +2.4 +2.4 -

Typ +2.5 25 6 +2.5 4 25

Max +2.6 60 10 +2.6 -

Unit V ppm/°C mV V pF nA

Output Voltage Temperature Coefficient Load Regulation
Reference Input

Input Voltage Range Input Capacitance Input CVF Current

Notes: 8. The voltage at VREFOUT is measured across the temperature range. From these measurements the following formula is used to calculate the VREFOUT Temperature Coefficient:.
TC VREF = - VREFOUT ( (VREFOUT VREFO UT
MAX AVG MIN )

(T

A

MAX

1 - T AM IN

( 1.0 x 10

6

9. Specified at maximum recommended output of 1 ?A, source or sink.

DIGITAL CHARACTERISTICS
? ? ? ? Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C. VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V. MCLK = 4.096 MHz.

Parameter
Master Clock Characteristics

Symbol

Min 2.5 40 40 -2.8 -

Master Clock Frequency Master Clock Duty Cycle CPUCLK Duty Cycle
Filter Characteristics

Internal Gate Oscillator (Note 11) MCLK (Note 12 and 13) (Voltage Channel, 60 Hz) DCLK = MCLK/K (Both Channels) -3 dB (Note 15) VIH OWR

4.096 DCLK/8 DCLK/1024 0.5 1.0

Phase Compensation Range Input Sampling Rate Digital Filter Output Word Rate High-pass Filter Corner Frequency

25

Full-scale DC Calibration Range (Referred to Input) (Note 14) FSCR Channel-to-channel Time-shift Error
Input/Output Characteristics

High-level Input Voltage All Pins Except XIN and SCLK and RESET XIN SCLK and RESET Low-level Input Voltage (VD = 5 V) All Pins Except XIN and SCLK and RESET XIN SCLK and RESET

0.6 VD+ (VD+) - 0.5 0.8?VD+ VIL -

DS678F3
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(
Typ Max 20 60 60 +2.8 100 Unit MHz % % ° Hz Hz Hz %F.S. ?s 0.8 1.5 0.2?VD+ V V V V V V 9

(

(

CS5463
Parameter Low-level Input Voltage (VD = 3.3 V) All Pins Except XIN and SCLK and RESET XIN SCLK and RESET High-level Output Voltage Low-level Output Voltage Input Leakage Current 3-state Leakage Current Digital Output Pin Capacitance Iout = +5 mA Iout = -5 mA (Note 16) Symbol VIL VOH VOL Iin IOZ Cout (VD+) - 1.0 ±1 5 0.48 0.3 0.2?VD+ 0.4 ±10 ±10 V V V V V ?A ?A pF Min Typ Max Unit

Notes: 10. All measurements performed under static conditions. 11. If a crystal is used, then XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is used, XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between 2.5 MHz - 5.0 MHz. 12. If external MCLK is used, then the duty cycle must be between 45% and 55% to maintain this specification. 13. The frequency of CPUCLK is equal to MCLK. 14. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is limited by the full-scale signal applied to the channel input. 15. Configuration Register bits PC[6:0] are set to “0000000”. 16. The MODE pin is pulled low by an internal resistor.

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DS678F3

分销商库存信息:
CIRRUS-LOGIC CS5463-ISZ CRD5463PM CS5463-ISZR CDB5463U CS5463-IS CDB5463U-Z


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