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ADCLK905BCPZ-R7;ADCLK925BCPZ-R7;ADCLK907BCPZ-R7;ADCLK905BCPZ-R2;中文规格书,Datasheet资料


Ultrafast SiGe ECL Clock/Data Buffers ADCLK905/ADCLK907/ADCLK925
FEATURES
95 ps propagation delay 7.5 GHz toggle rate 60 ps typical output rise/fall 60 fs random jitter (RJ) On-chip terminations at both input pins Extended industrial temperature range: ?40°C to +125°C 2.5 V to 3.3 V power supply (VCC ? VEE)

TYPICAL APPLICATION CIRCUITS
VREF VT VCC

D D

Q Q
06318-001

APPLICATIONS
Clock and data signal restoration and level shifting Automated test equipment (ATE) High speed instrumentation High speed line receivers Threshold detection Converter clocking

VEE

Figure 1. ADCLK905 ECL 1:1 Clock/Data Buffer

VREF 1 V T1 VCC D1 D1 VEE VEE D2 D2 VCC VREF 2
06318-002

GENERAL DESCRIPTION
The ADCLK905 (one input, one output), ADCLK907 (dual one input, one output), and ADCLK925 (one input, two outputs) are ultrafast clock/data buffers fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. The ADCLK905/ADCLK907/ADCLK925 feature full-swing emitter coupled logic (ECL) output drivers. For PECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For NECL (negative ECL) operation, bias VCC to ground and VEE to the negative supply. The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate, 10 Gbps data rate, and 60 fs random jitter (RJ). The inputs have center tapped, 100 Ω, on-chip termination resistors. A VREF pin is available for biasing ac-coupled inputs. The ECL output stages are designed to directly drive 800 mV each side into 50 Ω terminated to VCC ? 2 V for a total differential output swing of 1.6 V. The ADCLK905/ADCLK907/ADCLK925 are available in 16-lead LFCSP packages.

Q1 Q1

Q2 Q2

V T2

Figure 2. ADCLK907 ECL Dual 1:1 Clock/Data Buffer

VREF VT

VCC Q1 Q1

D D Q2
06318-003

Q2 VEE

Figure 3. ADCLK925 ECL 1:2 Clock/Data Fanout Buffer

Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ?2007 Analog Devices, Inc. All rights reserved.

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ADCLK905/ADCLK907/ADCLK925 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Typical Application Circuits........................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ..............................................8 Applications Information .............................................................. 11 Power/Ground Layout and Bypassing..................................... 11 Output Stages ............................................................................... 11 Optimizing High Speed Performance ..................................... 11 Buffer Random Jitter.................................................................. 11 Typical Application Circuits ......................................................... 12 Evaluation Board Schematic ......................................................... 13 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 14

REVISION HISTORY
8/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 16

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ADCLK905/ADCLK907/ADCLK925 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical (Typ) values are given for VCC ? VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum (Min) and maximum (Max) values are given over the full VCC ? VEE = 3.3 V ± 10% and TA = ?40°C to +125°C variation, unless otherwise noted. Table 1.
Parameter DC INPUT CHARACTERISTICS Input Voltage High Level Input Voltage Low Level Input Differential Range Symbol VIH VIL VID VID Input Capacitance Input Resistance, Single-Ended Mode Input Resistance, Differential Mode Input Resistance, Common Mode Input Bias Current DC OUTPUT CHARACTERISTICS Output Voltage High Level Output Voltage Low Level Output Voltage Differential Reference Voltage Output Voltage Output Resistance AC PERFORMANCE Propagation Delay CIN Min VEE + 1.6 VEE 0.2 0.2 0.4 50 100 50 20 VOH VOL VOD VREF VCC ? 1.26 VCC ? 1.99 610 (VCC + 1)/2 250 tPD 70 70 Propagation Delay Temperature Coefficient Propagation Delay Skew (Output to Output) ADCLK907 Propagation Delay Skew (Output to Output) ADCLK925 Propagation Delay Skew (Device to Device) Toggle Rate 95 95 50 15 10 35 6 7.5 6.5 Random Jitter Rise/Fall Time Additive Phase Noise 622.08 MHz RJ tR/tF 60 30 ?138 ?144 ?152 ?159 ?161 ?161 ?135 ?145 ?153 ?160 ?161 ?161
Rev. 0 | Page 3 of 16

Typ

Max VCC VCC ? 0.7 3.4 2.8

Unit V V V p-p V p-p pF Ω Ω kΩ μA

Conditions

?40°C to +85°C (±1.7 V between input pins) 85°C to 125°C (±1.4 V between input pins)

Open VT

VCC ? 0.76 VCC ? 1.54 1040

V V mV V Ω

50 Ω to (VCC ? 2.0 V) 50 Ω to (VCC ? 2.0 V) 50 Ω to (VCC ? 2.0 V) ?500 μA to +500 μA

125 125

ps ps fs/°C ps ps ps GHz GHz fs rms ps dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz

VCC = 3.3 V ± 10%, VICM = VREF, VID = 0.5 V p-p VCC = 2.5 V ± 5%, VICM = V REF, VID = 0.5 V p-p VID = 0.5 V VID = 0.5 V VID = 0.5 V >0.8 V differential output swing, VCC = 3.3 V ± 10% >0.8 V differential output swing, VCC = 2.5 V ± 5% VID = 1600 mV, 8 V/ns, VICM = 1.85 V 20%/80% @10 Hz offset @100 Hz offset @1 kHz offset @10 kHz offset @100 kHz offset >1 MHz offset @10 Hz offset @100 Hz offset @1 kHz offset @10 kHz offset @100 kHz offset >1 MHz offset

85

122.88 MHz

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ADCLK905/ADCLK907/ADCLK925
Parameter POWER SUPPLY Supply Voltage Requirement Power Supply Current ADCLK905 Negative Supply Current Positive Supply Current ADCLK907 Negative Supply Current Positive Supply Current ADCLK925 Negative Supply Current Positive Supply Current Power Supply Rejection 1 Output Swing Supply Rejection 2
1 2

Symbol VCC ? VEE

Min 2.375

Typ

Max 3.63

Unit V

Conditions 2.5 V ? 5% to 3.3 V + 10% Static VCC ? VEE = 2.5 V VCC ? VEE = 3.3 V ± 10% VCC ? VEE = 2.5 V VCC ? VEE = 3.3 V ± 10% VCC ? VEE = 2.5 V VCC ? VEE = 3.3 V ± 10% VCC ? VEE = 2.5 V VCC ? VEE = 3.3 V ± 10% VCC ? VEE = 2.5 V VCC ? VEE = 3.3 V ± 10% VCC ? VEE = 2.5 V VCC ? VEE = 3.3 V ± 10% VCC ? VEE = 3.0 V ± 20% VCC ? VEE = 3.0 V ± 20%

IVEE IVCC

24 25 47 48 48 50 94 96 29 31 76 77 3 26

40 63

mA mA mA mA mA mA mA mA mA mA mA mA ps/V dB

IVEE IVCC

80 126

IVEE IVCC PSRVCC PSRVCC

51 97

Change in TPD per change in VCC. Change in output swing per change in VCC.

Rev. 0 | Page 4 of 16

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ADCLK905/ADCLK907/ADCLK925 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage VCC ? VEE Input Voltage D (D1, D2), D (D1, D2) D1, D2, D1, D2 to VT Pin (CML or PECL Termination) D (D1, D2) to D (D1, D2) Maximum Voltage on Output Pins Maximum Output Current Input Termination, VT to D (D1, D2), D (D1, D2) Voltage Reference, VREF Temperature Operating Temperature Range, Ambient Operating Temperature, Junction Storage Temperature Range Rating 6.0 V VEE ? 0.5 V to VCC + 0.5 V ±40 mA ±1.8 V VCC + 0.5 V 35 mA ±2 V VCC ? VEE ?40°C to +125°C 150°C ?65°C to +150°C

THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance
Package Type 16-lead LFCSP θJA 70 Unit °C/W

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. 0 | Page 5 of 16

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ADCLK905/ADCLK907/ADCLK925 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
15 VREF 16 VT
PIN 1 INDICATOR

14 VEE 13 VCC
12 Q 11 Q 10 NC 9 NC

D 1 D 2 NC 3 NC 4 NC = NO CONNECT

ADCLK905
TOP VIEW (Not to Scale)

VCC 8

VEE 7

NC 5

NC 6

Figure 4. ADCLK905 Pin Configuration

Table 4. Pin Function Descriptions for 1:1 ADCLK905 Buffer
Pin No. 1 2 3, 4, 5, 6, 9, 10 7, 14 8, 13 11 12 15 16 Heat Sink Mnemonic D D NC VEE VCC Q Q VREF VT NC Description Noninverting Input. Inverting Input. No Connect. No physical connection to the die. Negative Supply Voltage. Positive Supply Voltage. Inverting Output. Noninverting Output. Reference Voltage. Reference voltage for biasing ac-coupled inputs. Center Tap. Center tap of 100 Ω input resistor. No Connect. The metallic back surface of the package is not electrically connected to any part of the circuit. It can be left floating for optimal electrical isolation between the package handle and the substrate of the die. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. Exposed metal at the corners of the package is connected to this back surface. Allow sufficient clearance to vias and other components.
15 VREF 1

16 VT1

D1 1 D1 2 D2 3 D2 4

PIN 1 INDICATOR

14 VEE

13 VCC

12 Q1 11 Q1 10 Q2 9 Q2

ADCLK907
TOP VIEW (Not to Scale)

VREF 2 6

VCC 8

VEE 7

V T2 5

Figure 5. ADCLK907 Pin Configuration

Table 5. Pin Function Descriptions for Dual 1:1 ADCLK907 Buffer
Pin No. 1 2 3 4 5 6 7, 14 8, 13 9 Mnemonic D1 D1 D2 D2 VT2 VREF2 VEE VCC Q2 Description Noninverting Input 1. Inverting Input 1. Noninverting Input 2. Inverting Input 2. Center Tap 2. Center tap of 100 Ω input resistor, Channel 2. Reference Voltage 2. Reference voltage for biasing ac-coupled inputs, Channel 2. Negative Supply Voltage. Positive Supply Voltage. Pin 8 and Pin 13 are not strapped internally. Inverting Output 2.
Rev. 0 | Page 6 of 16

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06318-005

06318-004

ADCLK905/ADCLK907/ADCLK925
Pin No. 10 11 12 15 16 Heat Sink Mnemonic Q2 Q1 Q1 VREF1 VT1 NC Description Noninverting Output 2. Inverting Output 1. Noninverting Output 1. Reference Voltage 1. Reference voltage for biasing ac-coupled inputs, Channel 1. Center Tap 1. Center tap of 100 Ω input resistor, Channel 1. No Connect. The metallic back surface of the package is not electrically connected to any part of the circuit. It can be left floating for optimal electrical isolation between the package handle and the substrate of the die. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. Exposed metal at the corners of the package is connected to this back surface. Allow sufficient clearance to vias and other components.
15 VREF 14 VEE

16 VT

D 1 D 2 NC 3 NC 4 NC = NO CONNECT

PIN 1 INDICATOR

13 VCC
12 Q1 11 Q1 10 Q2 9 Q2

ADCLK925
TOP VIEW (Not to Scale)

VCC 8

VEE 7

NC 5

NC 6

Figure 6. ADCLK925 Pin Configuration

Table 6. Pin Function Descriptions for 1:2 ADCLK925 Buffer
Pin No. 1 2 3, 4, 5, 6 7, 14 8, 13 9 10 11 12 15 16 Heat Sink Mnemonic D D NC VEE VCC Q2 Q2 Q1 Q1 VREF VT NC Description Noninverting Input. Inverting Input. No Connect. No physical connection to the die. Negative Supply Voltage. Positive Supply Voltage. Inverting Output 2. Noninverting Output 2. Inverting Output 1. Noninverting Output 1. Reference Voltage. Reference voltage for biasing ac-coupled inputs. Center Tap. Center tap of 100 Ω input resistor. No Connect. The metallic back surface of the package is not electrically connected to any part of the circuit. It can be left floating for optimal electrical isolation between the package handle and the substrate of the die. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. Exposed metal at the corners of the package is connected to this back surface. Allow sufficient clearance to vias and other components.

Rev. 0 | Page 7 of 16

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06318-006

ADCLK905/ADCLK907/ADCLK925 TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, VEE = 0.0 V, TA = 25°C, outputs terminated 50 Ω to VCC ? 2 V, unless otherwise noted.
2.37V Q

2.37V

Q

Q 1.37V 200ps/DIV
06318-007

100mV/DIV

100mV/DIV

Q 1.37V 100ps/DIV
06318-010

Figure 7. Output Waveform, VCC = 3.3 V
–90 –100 –110 –120 –130 –140 –150 –160 –170 10

Figure 10. Output Waveform, VCC = 3.3 V
–90 –100 –110 –120 –130 –140 –150 –160 –170 10

AGILENT E5500 CARRIER: 122.88MHz NO SPURS

AGILENT E5500 CARRIER: 622.08MHz NO SPURS

L[f] (dBc/Hz)

06318-008

f (Hz)

f (Hz)

Figure 8. Phase Noise at 122.88 MHz
–90 –100 –110 –120 –130 –140 –150 –160 –170 10 50 300

Figure 11. Phase Noise at 622.08 MHz

AGILENT E5500 CARRIER: 245.76MHz NO SPURS

250

RMS JITTER (fs)

200

L[f] (dBc/Hz)

150

100

06318-009

f (Hz)

INPUT SLEW RATE (V/ns)

Figure 9. Phase Noise at 245.76 MHz

Figure 12. RMS Jitter vs. Input Slew Rate

Rev. 0 | Page 8 of 16

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06318-012

100

1k

10k

100k

1M

10M

100M

0

0

1

2

3

4

5

6

7

8

06318-011

100

1k

10k

100k

1M

10M

100M

L[f] (dBc/Hz)

100

1k

10k

100k

1M

10M

100M

ADCLK905/ADCLK907/ADCLK925
1.1 1.0

0.09 0.08
POWER SUPPLY CURRENT (A)

+125°C

0.07 0.06 0.05 0.04 0.03

+25°C –55°C

OUTPUT SWING (V)

0.9 0.8 +125°C

0.7 0.6 0.5 +25°C

+125°C 0.02 0.01 +25°C 0 1 2 SUPPLY VOLTAGE (V)

–55°C

–55°C 3 4
06318-016 06318-018 06318-017

1

2

3

4

SUPPLY VOLTAGE (V)

Figure 13. VOD vs. Power Supply Voltage

06318-013

0.4

0

Figure 16. Power Supply Current vs. Supply Voltage, ADCLK925

0.07

100

0.06

POWER SUPPLY CURRENT (A)

+125°C 0.05

99

98
+25°C 0.04 0.03 –55°C

tPD (ps)
+125°C +25°C –55°C 3.0 3.5 4.0
06318-014

97

96
0.02 0.01 0 2.5

95

94 0.4

0.6

0.8

1.0

1.2 VID (V)

1.4

1.6

1.8

POWER SUPPLY VOLTAGE (V)

Figure 14. Power Supply Current vs. Power Supply Voltage, ADCLK905
110

Figure 17. Propagation Delay vs. VID
1.8 1.6

PROPAGATION DELAY (ps)

105 +125°C 100 +25°C 95

1.4 1.2
VOD (V)
3.1 3.6
06318-015

1.0 0.8 0.6

–55°C

0.4 0.2
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5

10.5

11.5

INPUT COMMON MODE (V)

FREQUENCY (GHz)

Figure 15. Propagation Delay vs. VICM; Input Swing = 200 mV

Figure 18. Toggle Rate, Differential Output Swing vs. Frequency

Rev. 0 | Page 9 of 16

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12.5

90 1.6

2.1

2.6

0

ADCLK905/ADCLK907/ADCLK925
1 1

C4 C4

2

2

17ps/DIV
06318-019 06318-023

58ps/DIV 3
23

3

Figure 19. 2.488 Gbps PRBS 2 ? 1 with OC-48/STM-16 Mask, Measured p-p Jitter 8.1 ps, Source p-p Jitter 3.5 ps

Figure 22. 8.50 Gbps PRBS 223 ? 1 with FC8500E ABS Beta Rx Mask, Measured p-p Jitter 10.9 ps, Source p-p Jitter 4.4 ps

1

1

C4

C4

2

2

06318-022

3

3

Figure 20. 9.95 Gbps PRBS 223 ? 1 with OC-193/STM-64 Mask, Measured p-p Jitter 10.5 ps, Source p-p Jitter 6.0 ps

Figure 23. 2.5 Gbps PRBS 223 ? 1 with PCI Express 2.5 Rx Mask, Measured p-p Jitter 8.1 ps, Source p-p Jitter 3.5 ps

1

1

C4
C4

2

2

06318-020

3
23

3

Figure 21. 4.25 Gbps PRBS 2 ? 1 with FC4250 (Optical) Mask, Measured p-p Jitter 8.2 ps, Source p-p Jitter 3.4 ps

Figure 24. 5.0 Gbps PRBS 223 ? 1 with PCI Express 5.0 Rx Mask, Measured p-p Jitter 8.7 ps, Source p-p Jitter 3.5 ps

Rev. 0 | Page 10 of 16

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06318-024

34ps/DIV

29ps/DIV

06318-021

15ps/DIV

58ps/DIV

分销商库存信息:
ANALOG-DEVICES ADCLK905BCPZ-R7 ADCLK905BCPZ-R2 ADCLK925BCPZ-WP ADCLK905/PCBZ ADCLK925BCPZ-R7 ADCLK905BCPZ-WP ADCLK907BCPZ-R2 ADCLK907/PCBZ ADCLK907BCPZ-R7 ADCLK925BCPZ-R2 ADCLK907BCPZ-WP ADCLK925/PCBZ


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